Advanced Power Electronics Corp. APE8903B 3A ULTRA LOW DROPOUT LINEAR REGULATOR FEATURES DESCRIPTION TYPICAL APPLICATION

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1 3A ULTRA LOW DROPOUT LINEAR REGULATOR FEATURES DESCRIPTION Ultra Low Dropout 2A Output Current for 1.2V Output Voltage Low ESR Output Capacitor (Multi-layer Chip Capacitors (MLCC)) Applicable Pull-low for MP-A Pull-high for MP-B Fast Transient Response Adjustable Output Voltage by External Resistors Power-On-Reset Monitoring on Both VCNTL and VIN Pins Internal Soft-Start Under-Voltage Protection Current-Limit and Thermal Shutdown Protection Power-OK Output with a Delay Time SO-8 with Exposed Pad Pb-Free Package. The series is a 3A ultra low dropout linear regulator. This product is specifically designed to provide well supply voltage for front-side-bus termination on motherboards and NB applications. The IC needs two supply voltages, a control voltage for the circuitry and a main supply voltage for power conversion, to reduce power dissipation and provide extremely low dropout. The series integrates many functions. A Power-On-Reset (POR) circuit monitors both supply voltages to prevent wrong operations. A thermal shutdown and current limit functions protect the device against thermal and current over-loads. A indicates the output status with time delay which is set internally. It can control other converter for power sequence. The series can be enabled by other power system. Pulling and holding the pin below 0.6V shuts off the output. The series is available in ESOP-8 package which features small size as SO-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in 2~3W applications. TYPICAL APPLICATION 1. Using an Output Capacitor with ESR 20mΩ R3 VCNTL=5V C1 1uF OFF ON U1 10K VCNTL VIN NC GND FB R1 1K C2 C3 100uF 0.1uF C6 12~48nF option C4 VIN=1.8V Vout=1.2V/2A C5 R2 2K 220uF 0.1 uf Data and specifications subject to change without notice

2 TYPICAL APPLICATION 2. Using an MLCC as the Output Capacitor R3 10K VCNTL=5V C1 1uF OFF ON U2 VCNTL VIN NC GND FB R1 39K C3 4.7uF C6 56pF option C5 10uF VIN=1.8V =1.2V/2A R2 78K =VFB x (1+R1/R2) VFB = 0.8V PACKAGE/ORDERING INFORMATION X-X 1 ( Top View) 8 GND Package Type MP : ESOP-8 Function A : Pull Low B : Pull High VIN VCNTL GND 7 FB 6 5 NC ESOP-8 ABSOLUTE MAXIMUM RATINGS (Note1) CNTL Supply Voltage (V CNTL ) V to 6.5V Input Supply Voltage (V IN ) V to 6.5V Output Voltage (V OUT ) V to 6V & FB Pin Voltage (V /V FB ) V to VCNTL+0.3V Power Good Voltage (V ) V to 6.5V Power Dissipation (P D ) W Storage Temperature Range (T ST ) C to 150 C Junction Temperature Range (T J ) C to 150 C Thermal Resistance Junction to Ambient (Rth ja ) Note 40 C/W Thermal Resistance Junction to Case (Rth jc ) C/W Note. Rth ja is measured with the PCB copper area (need connect to Expose-Pad) of approximately 1.5 in 2 (Multi-layer) RECOMMDED OPERATING CONDITIONS Operating Junction Temperature Range (T OJ ) C To 125 C Operating Ambient Temperature Range (T OA ) C To 85 C VCNTL Supply Voltage (V CNTL ) V To 6V Input Supply Voltage (V IN ) V To 5.5V Output Voltage (V OUT )@V CNTL =5V V To 2.8V Output Cunrrent (I OUT ) A To 3A 2

3 ELECTRICAL SPECIFICATIONS V CNTL = 5V, V IN =1.8V, V OUT =1.2V, T A =25 o C unless otherwise specified Parameter SYM TEST CONDITION MIN TYP MAX UNITS V CNTL POR Threshold V CNTL V V CNTL POR Hysteresis V CNTL(hys) V V IN POR Threshold V IN V V IN POR Hysteresis V IN(hys) V V CNTL Nominal Supply Current I CNTL = V CNTL ma V CNTL Shuntdown Current I SD = 0V -A ua -B ua Feedback Voltage V FB V CNTL =3 ~ 6V, I OUT =10mA, V IN =V OUT +0.5~5.5V V Load Regulation I OUT =0A ~ 2A % On Resistance R DS(ON) I OUT =100mA, V CNTL =V =5.0V, V OUT =1.2V mω Dropout Voltage V DROP I OUT = 2A, V CNTL =5V, V OUT = 1.2V V V OUT Pull Low Resistance =0V Ω Soft Start Time T SS ms Pin Logic High Threshold V H Enable Voltage V L Disable V Hysteresis mv Pin Pull-Up Current I =5V, MP-A =GND, MP-B ua Current Limit I LIM V CNTL =5V, V IN =V OUT +1V A Ripple Rejection V IN PSRR F=120Hz, I OUT =100mA V CNTL db Inrush current V CNTL =5V, C OUT =10uF, startup, I OUT =2A A Under-Voltage Threshold VFB Falling V Threshold Voltage for Power OK V VFB Rising 89% 92% 95% VFB Threshold Voltage for Power Not OK V PNOK VFB Falling 78% 81% 84% VFB Low Voltage sinks 5mA V Delay Time T DELAY ms Thermal Shutdown Temp TSD o C Thermal Shutdown Hysteresis o C 3

4 PIN DESCRIPTIONS PIN SYMBOL VIN VCNTL NC FB GND PIN DESCRIPTION Power OK Output Pin Internal Pull High (MP-B) or Pull Low (MP-A) =High or Floating Enable =Low Shutdown Mode Input Voltage. CNTL Pin Input Voltage No Connect Output Voltage Feedback Pin GND Pin BLOCK DIAGRAM MP-A VIN N-MOSFET VCNTL Power -ON Reset Enable Current Limit Soft-Start And Control Logic - + Error Amp Bandgap 10uA Thermal Shutdown 0.4V + UV - FB GND Delay % V REF MP-B VIN N-MOSFET VCNTL 10uA Power -ON Reset Enable Current Limit Soft-Start And Control Logic - + Error Amp Bandgap Thermal Shutdown 0.4V + UV - FB GND Delay % V REF 4

5 PIN DESCRIPTION FB Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by: VIN Main supply input pins for power conversions. The voltage at this pin is monitored for Power- On Reset purpose. VCNTL Where R1 is connected from to FB with Kelvin sensing and R2 is connected from FB to GND. A bypass capacitor may be connected with R1 in parallel to improve load transient response. The R2 range in 1K~4.7KΩ for AL output capacitor and 30K~100KΩ for MLCC output capacitor are recommended. Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On Reset purpose. Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the V threshold or the falling FB voltage is below the V threshold, indicating the output is not OK. Enable control pin. Pulling and holding this pin below 0.6V shuts down the output. When reenabled, the IC undergoes a new soft-start cycle. For MP-B, this pin is internal pulled up to VCNTL voltage, enabling the regulator. For MP-A, this pin is internal pulled down to GND voltage, shutdown the regulator. The pull-high or pull-low current is 10uA (typ.) Regulator output pin. Please connect Pin 6 using wide tracks. It is necessary to connect an output capacitor with this pin for closed-loop compensation and improving transient responses. FUNCTION DESCRIPTION Power-On-Reset A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR function also pulls low the pin regardless the output voltage when the VCNTL voltage falls below its falling POR threshold. Internal Soft-Start An internal soft-start function controls rise rate of the output voltage to limit the current surge at start-up. The typical soft-start interval is about 2ms. Output Voltage Regulation An error amplifier working with a temperature compensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to. Current-Limit The monitors the current via the output NMOS and limits the maximum current to prevent load and from damages during overload or short circuit conditions. 5

6 FUNCTION DESCRIPTION Under-Voltage Protection (UVP) Thermal Shutdown APPLICATION INFORMATION Capacitor Selection The monitors the voltage on FB pin after soft-start process is finished. Therefore the UVP is disabling during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the starts a new soft-start to regulate output. A thermal shutdown circuit limits the junction temperature of. When the junction temperature exceeds +160 C, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature cools by 40 C, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown designed. Normally, use a MLCC capacitor on the input and output of the. Larger input capacitor values provide better supply-noise rejection and transient response. A higher- value output capacitor may be necessary if large, fast transients are anticipated and the device is located several inches from the power source. The X5R and X7R type in MLCC is recommended. For aluminum electrolytic capacitor application, 100uF in input capacitor and 220uF in output capacitor (30mΩ < ESR < 200mΩ) are recommended. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. 6

7 TYPICAL PERFORMANCE CHARACTERISTICS Line Regulation Load Regulation VFB (V) VFB (V) VIN=1.8V, =1.2V IOUT=10mA V CNTL (V) IOUT (A) VCNTL=5V, VIN=1.8V, =1.2V 800 Dropout Voltage (V CNTL =3.3V) 600 Dropout Voltage (V CNTL =5V) Dropout Voltage (mv) =1.5V =1.2V Dropout Voltage (mv) V OUT=1.8V V OUT=2.5V V OUT=1.2V IOUT (A) IOUT (A) Temperature VS V FB 2 Temperature VS Quiescent Current VFB (V) VCNTL=5V, VIN=1.8V, V OUT=1.2V, I OUT=10mA ICNTL (ma) V CNTL=5V, V IN=1.8V, V OUT=1.2V, I OUT=0A Temperature ( ) Temperature ( ) 7

8 TYPICAL PERFORMANCE CHARACTERISTICS Enable Threshold Voltage (V) Temperature VS Enable Threshold Voltage V H V L V CNTL=5V Temperature ( ) VCNTL POR Threshold Voltage (V) Temperature VS V CNTL POR Threshold Rising Falling Temperature ( ) Line Transient Line Transient Load Transient VCNTL Power ON 8

9 TYPICAL PERFORMANCE CHARACTERISTICS VIN Power ON Enable ON with Delay 9

10 MARKING INFORMATION ESOP BMP-X YWWSSS Part Number Package Code Function Date Code (YWWSSS) Y:Last Digit Of The Year WW:Week SSS:Sequence 10