CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
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1 Data sheet acquired from Harris Semiconductor SCHS155C October Revised August 2003 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 High-Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register Features Description [ /Title (CD74 HC164, CD74 HCT16 4) /Subject (High Speed CMOS Logic 8-Bit Serial- In/Parallel- Buffered Inputs Asynchronous Master Reset Typical f MAX = 60MHz at V CC = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH The HC164 and HCT164 are 8-bit serial-in parallel-out shift registers with asynchronous reset. Data is shifted on the positive edge of Clock (CP). A LOW on the Master Reset (MR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (DS1 and DS2) are provided, either one can be used as a Data Enable control. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC164F3A -55 to Ld CERDIP CD54HCT164F3A -55 to Ld CERDIP CD74HC164E -55 to Ld PDIP CD74HC164M -55 to Ld SOIC CD74HC164MT -55 to Ld SOIC CD74HC164M96-55 to Ld SOIC CD74HCT164E -55 to Ld PDIP CD74HCT164M -55 to Ld SOIC CD74HCT164MT -55 to Ld SOIC CD74HCT164M96-55 to Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC164, CD54HCT164 (CERDIP) CD74HC164, CD74HCT164 (PDIP, SOIC) TOP VIEW DS V CC DS Q 7 Q Q 6 Q Q 5 Q Q 4 Q MR 7 8 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2003, Texas Instruments Incorporated 1
2 Functional Diagram CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 DS1 DS Q 0 Q 1 Q 2 6 Q 3 10 Q 4 11 Q 5 12 Q 6 13 Q 7 MR CP 9 8 = 7 V CC = 14 TRUTH TABLE INPUTS OUTPUTS OPERATING MODE MR CP DS1 DS2 Q 0 Q 1 - Q 7 RESET (CLEAR) L X X X L L - L Shift H l l L q 0 - q 6 H l h L q 0 - q 6 H h l L q 0 - q 6 H h h H q 0 - q 6 H= High Level. h= High Level One Set-up Time Prior To The Low-to-high Clock Transition. l= Low Level One Set-up Time Prior To The Low-to-high Clock Transition. L= Low Level. X= Don t Care. = Transition from Low to High Level. q n = Lower Case Letters Indicate The State Of the Reference Input Clock Transition. 2
3 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 Absolute Maximum Ratings DC Supply, V CC V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > V CC + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > V CC + 0.5V ±20mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < V CC + 0.5V ±25mA DC V CC or Ground Current, I CC or I ±50mA Thermal Information Thermal Resistance (Typical, Note 1) θ JA ( o C/W) E (PDIP) Package M (SOIC) Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range (T A ) o C to 125 o C Supply Range, V CC HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to V CC Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER HC TYPES SYMBOL V I (V) I O (ma) V CC (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input V IH V V V Low Level Input V IL V V High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads V OH V OL V V IH or V V IL V V V V V IH or V V IL V V V V Input Leakage Current I I V CC or ±0.1 - ±1 - ±1 µa Quiescent Device Current I CC V CC or µa 3
4 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 DC Electrical Specifications (Continued) PARAMETER HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load SYMBOL V IH to 5.5 V IL to 5.5 V OH V OL I I I CC I CC (Note 2) TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) V CC (V) MIN TYP MAX MIN MAX MIN MAX V V V IH or V V IL V V IH or V V IL V CC to V CC or V CC V ±0.1 - ±1 - ±1 µa µa to 5.5 NOTE: 2. For dual-supply systems theoretical worst case (V I = 2.4V, V CC = 5.5V) specification is 1.8mA. UNITS µa HCT Input Loading Table INPUT UNIT LOADS Date Shift-In (1, 2) 0.3 MR 0.9 Clock 0.7 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25 o C. Prerequisite For Switching Function 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL V CC (V) MIN MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency f MAX MHz MHz MHz MR Pulse Width t w ns ns ns 4
5 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 Prerequisite For Switching Function (Continued) PARAMETER SYMBOL V CC (V) CP Pulse Width t W ns ns ns Set-up Time t SU ns ns ns Hold Time t H ns ns ns MR to Clock, t REM ns Removal Time ns ns HCT TYPES Maximum Clock Frequency f MAX MHz MR Pulse Width t w ns CP Pulse Width t w ns Set-up Time t SU ns Hold Time t H ns MR to Clock, Removal Time t REM ns Switching Specifications Input t r, t f = 6ns 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN MAX MIN MAX MIN MAX UNITS PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX UNITS HC TYPES Propagation Delay, t PLH, t PHL C L = 50pF ns CP to Q n ns C L = 15pF ns C L = 50pF ns MR to Q n t PLH, t PHL C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Transition Times t TLH, t THL C L = 50pF ns ns ns Maximum Clock Frequency f MAX C L = 15pF MHz Input Capacitance C IN pf 5
6 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 Switching Specifications Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX UNITS Power Dissipation Capacitance (Notes 3, 4) C PD pf HCT TYPES Propagation Delay, t PLH, t PHL C L = 50pF ns CP to Q n C L = 15pF ns MR to Q n t PLH, t PHL C L = 50pF ns C L = 15pF ns Output Transition Times t TLH, t THL C L = 50pF ns Input Capacitance C IN pf Maximum Clock Frequency f MAX C L = 15pF MHz Power Dissipation Capacitance (Notes 3, 4) C PD pf NOTES: 3. C PD is used to determine the dynamic power consumption, per device. 4. P D =V 2 CC fi + (C L V 2 CC +fo ) where f i = Input Frequency, f O = Output Frequency, C L = Output Load Capacitance, V CC = Supply. Test Circuits and Waveforms CLOCK INPUT t r C L 90% 10% t f C L 50% V CC CLOCK INPUT t r C L 2.7V 0.3V t f C L 1.3V 3V t H(H) t H(L) t H(H) t H(L) DATA INPUT t SU(H) t SU(L) V CC 50% DATA INPUT t SU(H) 1.3V 1.3V t SU(L) 1.3V 3V OUTPUT 90% t TLH t THL 90% 50% 10% OUTPUT t TLH 90% 1.3V t THL 90% 1.3V 10% t PLH t PHL t PLH t PHL t REM V CC SET, RESET 50% OR PRESET t REM 3V SET, RESET OR PRESET 1.3V IC C L 50pF IC C L 50pF FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6
7 PACKAGE OPTION ADDENDUM 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to CA CD54HCT164F3A CD54HC164F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC164F (4/5) Samples CD54HC164F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to CA CD54HC164F3A CD54HCT164F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to CA CD54HCT164F3A CD74HC164E ACTIVE PDIP N Pb-Free (RoHS) CD74HC164EE4 ACTIVE PDIP N Pb-Free (RoHS) CD74HC164M ACTIVE SOIC D Green (RoHS CD74HC164M96 ACTIVE SOIC D Green (RoHS CD74HC164M96G4 ACTIVE SOIC D Green (RoHS CD74HC164ME4 ACTIVE SOIC D Green (RoHS CD74HC164MG4 ACTIVE SOIC D Green (RoHS CD74HC164MT ACTIVE SOIC D Green (RoHS CD74HCT164E ACTIVE PDIP N Pb-Free (RoHS) CD74HCT164EE4 ACTIVE PDIP N Pb-Free (RoHS) CD74HCT164M ACTIVE SOIC D Green (RoHS CD74HCT164M96 ACTIVE SOIC D Green (RoHS CD74HCT164M96E4 ACTIVE SOIC D Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC164E CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC164E CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT164E CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT164E CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M Addendum-Page 1
8 PACKAGE OPTION ADDENDUM 10-Jun-2014 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan CD74HCT164M96G4 ACTIVE SOIC D Green (RoHS CD74HCT164MG4 ACTIVE SOIC D Green (RoHS CD74HCT164MT ACTIVE SOIC D Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/5) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2
9 PACKAGE OPTION ADDENDUM 10-Jun-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC164, CD54HCT164, CD74HC164, CD74HCT164 : Catalog: CD74HC164, CD74HCT164 Military: CD54HC164, CD54HCT164 NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications Addendum-Page 3
10 PACKAGE MATERIALS INFORMATION 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CD74HC164M96 SOIC D Q1 CD74HC164MT SOIC D Q1 CD74HCT164M96 SOIC D Q1 CD74HCT164MT SOIC D Q1 Pack Materials-Page 1
11 PACKAGE MATERIALS INFORMATION 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC164M96 SOIC D CD74HC164MT SOIC D CD74HCT164M96 SOIC D CD74HCT164MT SOIC D Pack Materials-Page 2
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13 SCALE PACKAGE OUTLINE J0014A CDIP mm max height CERAMIC DUAL IN LINE PACKAGE PIN 1 ID (OPTIONAL) A 4X.005 MIN [0.13] TYP [ ] 12X.100 [2.54] X [ ] 14X [ ].010 [0.25] C A B [ ] 7 8 B [ ] [ ] AT GAGE PLANE.2 MAX TYP [5.08] C.13 MIN TYP [3.3] SEATING PLANE.015 GAGE PLANE [0.38] 0-15 TYP 14X [ ] /A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14.
14 J0014A EXAMPLE BOARD LAYOUT CDIP mm max height CERAMIC DUAL IN LINE PACKAGE SEE DETAIL A (.300 ) TYP [7.62] SEE DETAIL B X (.100 ) [2.54] SYMM 14X (.039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X.002 MAX [0.05] ALL AROUND (.063) [1.6] SOLDER MASK OPENING METAL (.063) [1.6] METAL (R.002 ) TYP [0.05] DETAIL A SCALE: 15X SOLDER MASK OPENING DETAIL B 13X, SCALE: 15X.002 MAX [0.05] ALL AROUND /A 05/2017
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CD54HC4015, CD74HC4015
CD54HC4015, CD74HC4015 Data sheet acquired from Harris Semiconductor SCHS198C November 1997 - Revised May 2003 High Speed CMOS Logic Dual 4-Stage Static Shift Register [ /Title (CD74 HC401 5) /Subject
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Data sheet acquired from Harris Semiconductor SCHS169C November 1997 - Revised October 2003 CD54HC251, CD74HC251, CD54HCT251, CD74HCT251 High-Speed CMOS Logic 8-Input Multiplexer, Three-State [ /Title
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283 [ /Title (CD74 HC283, CD74 HCT28 3) /Subject (High Speed CMOS Logic 4-Bit Binary Full Adder Data sheet acquired from Harris Semiconductor SCHS176D November
CD54HC14, CD74HC14, CD54HCT14, CD74HCT14
CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Data sheet acquired from Harris Semiconductor SCHS129F January 1998 - Revised May 2005 High-Speed CMOS Logic Hex Inverting Schmitt Trigger [ /Title (CD74H C14,
CD54HC280, CD74HC280, CD54HCT280, CD74HCT280
Data sheet acquired from Harris Semiconductor SCHS175D November 1997 - Revised October 2003 Features CD54HC280, CD74HC280, CD54HCT280, CD74HCT280 High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker
CD54HC10, CD74HC10, CD54HCT10, CD74HCT10
Data sheet acquired from Harris Semiconductor SCHS128C August 1997 - Revised September 2003 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 High-Speed CMOS Logic Triple 3-Input NAND Gate [ /Title (CD74 HC10,
CD54HC7266, CD74HC7266
CD54HC7266, CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219D August 1997 - Revised September 2003 High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate [ /Title (CD74H C7266) /Subject
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520 Data sheet acquired from Harris Semiconductor SCHS216D November 1997 - Revised October 2003 High-Speed CMOS Logic Dual Synchronous Counters [ /Title (CD74
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E March 1998 - Revised October 2003 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title
CD54HC147, CD74HC147, CD74HCT147
CD54HC147, CD74HC147, CD74HCT147 Data sheet acquired from Harris Semiconductor SCHS149F September 1997 - Revised November 2003 High-Speed CMOS Logic 10- to 4-Line Priority Encoder [ /Title (CD74 HC147,
CD54HC139, CD74HC139, CD54HCT139, CD74HCT139
Data sheet acquired from Harris Semiconductor SCHS148D September 1997 - Revised October 2003 CD54HC139, CD74HC139, CD54HCT139, CD74HCT139 High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer [
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Data sheet acquired from Harris Semiconductor SCHS124D January 1998 - Revised September 2003 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger Features
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 Data sheet acquired from Harris Semiconductor SCHS157C February 1998 - Revised October 2003 High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
CD54HC73, CD74HC73, CD74HCT73
CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E February 1998 - Revised September 2003 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Data sheet acquired from Harris Semiconductor SCHS135F March 1998 - Revised October 2003 Dual 2-Bit Bistable Transparent Latch [ /Title (CD74 HC75, CD74 HCT75 )
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
Data sheet acquired from Harris Semiconductor SCHS145E August 1997 - Revised March 2004 CD54HC132, CD74HC132, CD54HCT132, CD74HCT132 High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger [ /Title (CD74
CD54HC194, CD74HC194, CD74HCT194
Data sheet acquired from Harris Semiconductor SCHS164G September 1997 - Revised May 2006 CD54HC194, CD74HC194, CD74HCT194 High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register Features Description
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205I February 1998 - Revised February 2005 High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting
CD54HC273, CD74HC273, CD54HCT273, CD74HCT273
Data sheet acquired from Harris Semiconductor SCHS174B February 1998 - Revised May 2003 CD54HC273, CD74HC273, CD54HCT273, CD74HCT273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset [ /Title (CD74
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189C January 1998 - Revised July 2004 High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Data sheet acquired from Harris Semiconductor SCHS142F September 1997 - Revised October 2003 High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators
CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS
Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking Typical f MAX = 60 MHz at = 5 V, = 5 pf, T A = 25 C Fanout (Over Temperature Range) Standard
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210G August 1997 - Revised June 2006 High-Speed CMOS Logic Triple 3-Input OR Gate [ /Title (CD74H C4075,
CD54HC40103, CD74HC40103, CD74HCT40103
CD54HC40103, CD74HC40103, CD74HCT40103 Data sheet acquired from Harris Semiconductor SCHS221D November 1997 - Revised October 2003 High-Speed CMOS Logic 8-Stage Synchronous Down Counters [ /Title (CD74H
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Data sheet acquired from Harris Semiconductor SCHS183C February 1998 - Revised May 2004 Features High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State
CD54/74HC74, CD54/74HCT74
CD54/74HC74, CD54/74HCT74 Data sheet acquired from Harris Semiconductor SCHS124A January 1998 - Revised May 2000 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger Features Description [ /Title
Data sheet acquired from Harris Semiconductor SCHS083B Revised March 2003
Data sheet acquired from Harris Semiconductor SCHS083B Revised March 2003 The CD4536B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 High-Speed CMOS Logic Octal Buffer/Line Drivers, Three-State
Data sheet acquired from Harris Semiconductor SCHS167E November 1997 - Revised October 2004 CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 High-Speed CMOS Logic Octal
CD54/74AC283, CD54/74ACT283
Data sheet acquired from Harris Semiconductor SCHS251D August 1998 - Revised May 2000 Features Buffered Inputs Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process and
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Data sheet acquired from Harris Semiconductor SCHS188 January 1998 CD74HC534, CD74HCT534, CD74HC564, CD74HCT564 High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Data sheet acquired from Harris Semiconductor SCHS178C January 1998 - Revised May 2003 High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State [ /Title
CD54HC194, CD74HC194, CD74HCT194
Data sheet acquired from Harris Semiconductor SCHS164F September 1997 - Revised October 2003 CD54HC194, CD74HC194, CD74HCT194 High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register Features
CD74HC73, CD74HCT73. Dual J-K Flip-Flop with Reset Negative-Edge Trigger. Features. Description. Ordering Information. Pinout
Data sheet acquired from Harris Semiconductor SCHS134 February 1998 CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74 HCT73 ) /Subject Dual -K liplop Features
CD74HC4067, CD74HCT4067
CD74HC4067, CD74HCT4067 Data sheet acquired from Harris Semiconductor SCHS209C February 1998 - Revised July 2003 High-Speed CMOS Logic 16-Channel Analog Multiplexer/Demultiplexer [ /Title (CD74 HC406 7,
CD54/74AC164, CD54/74ACT164
CD54/74AC164, CD54/74ACT164 Data sheet acquired from Harris Semiconductor SCHS240A September 1998 - Revised May 2000 8-Bit Serial-In/Parallel-Out Shift Register [ /Title (CD74 AC164, CD74 ACT16 4) /Subject
CD54/74HC30, CD54/74HCT30
CD54/74HC30, CD54/74HCT30 Data sheet acquired from Harris Semiconductor SCHS121D August 1997 - Revised September 2003 High Speed CMOS Logic 8-Input NAND Gate [ /Title (CD54H C30, CD74H C30, CD74H CT30)
CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060
CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 Data sheet acquired from Harris Semiconductor SCHS207G February 1998 - Revised October 2003 High-Speed CMOS Logic 14-Stage Binary Counter with Oscillator
CD54HC273, CD74HC273, CD54HCT273, CD74HCT273
Data sheet acquired from Harris Semiconductor SCHS174B February 1998 - Revised May 2003 CD54HC273, CD74HC273, CD54HCT273, CD74HCT273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset [ /Title (CD74
1 to 4 Configurable Clock Buffer for 3D Displays
1 S3 GND S4 4 5 6 CLKIN 3 CLKOUT3 S1 2 Top View CLKOUT4 S2 1 7 8 9 OE 12 11 10 CLKOUT1 VDD CLKOUT2 CDC1104 SCAS921 SEPTEMBER 2011 1 to 4 Configurable Clock Buffer for 3D Displays Check for Samples: CDC1104
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
CD5/7HC13, CD5/7HCT13, CD7HC3, CD7HCT3 Data sheet acquired from Harris Semiconductor SCHS1A September 1997 - Revised May 000 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets
CD74AC251, CD74ACT251
Data sheet acquired from Harris Semiconductor SCHS246 August 1998 CD74AC251, CD74ACT251 8-Input Multiplexer, Three-State Features Buffered Inputs Typical Propagation Delay - 6ns at V CC = 5V, T A = 25
CD54/74AC280, CD54/74ACT280
CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A August 1998 - Revised May 2000 9-Bit Odd/Even Parity Generator/Checker Features Buffered Inputs Typical Propagation Delay
SN74LV04A-Q1 HEX INVERTER
SN74LV04A-Q1 HEX INVERTER Qualified for Automotive Applications ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pf, R = 0) 2-V to 5.5-V Operation
74ACT11244 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS
3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed
CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538
CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Data sheet acquired from Harris Semiconductor SCHS123E June 1998 - Revised October 2003 High-Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator
CD54HC4017, CD74HC4017
CD54HC4017, CD74HC4017 Data sheet acquired from Harris Semiconductor SCHS200D November 1997 - Revised October 2003 High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs [ /Title (CD74 HC401
CD54/74HC139, CD54/74HCT139
Data sheet acquired from Harris Semiconductor SCHS148B September 1997 - Revised May 2000 CD54/74HC139, CD54/74HCT139 High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer [ /Title (CD74 HC139, CD74
CD54HC4059, CD74HC4059
CD54HC4059, CD74HC4059 Data sheet acquired from Harris Semiconductor SCHS206B February 1998 - Revised May 2003 High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter Features Description [ /Title
CD54/74HC10, CD54/74HCT10
Data sheet acquired from Harris Semiconductor SCHS128A August 1997 - Revised May 2000 CD54/74HC10, CD54/74HCT10 High Speed CMOS Logic Triple 3-Input NAND Gate [ /Title (CD74 HC10, CD74 HCT10 ) /Subject
CD54/74HC02, CD54/74HCT02
Data sheet acquired from Harris Semiconductor SCHS125A March 1998 - Revised May 2000 CD54/74HC02, CD54/74HCT02 High Speed CMOS Logic Quad Two-Input NOR Gate [ /Title (CD74H C02, CD74H CT02) /Subject High
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Data sheet acquired from Harris Semiconductor SCHS183C February 1998 - Revised May 2004 Features High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189C January 1998 - Revised July 2004 High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State
CD74HC123, CD74HCT123, CD74HC423, CD74HCT423
Data sheet acquired from Harris Semiconductor SCHS1 September 1997 CD7HC13, CD7HCT13, CD7HC3, CD7HCT3 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets Features Description
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Data sheet acquired from Harris Semiconductor SCHS222C February 1998 - Revised October 2003 High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register [ /Title
CD54/74HC175, CD54/74HCT175
CD54/74HC175, CD54/74HCT175 Data sheet acquired from Harris Semiconductor SCHS160A August 1997 - evised May 2000 High Speed CMOS Logic uad D-Type Flip-Flop with eset [ /Title (CD74 HC175, CD74 HCT17 5)
ua9637ac DUAL DIFFERENTIAL LINE RECEIVER
ua9637ac DUAL DIFFERENTIAL LINE RECEIVER Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11 Operates From Single 5-V Power Supply
SN75150 DUAL LINE DRIVER
SN75150 DUAL LINE DRIVER Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs
GENERAL-PURPOSE LOW-VOLTAGE COMPARATORS
1 LMV331-Q1 SINGLE, LMV393-Q1 DUAL SLOS468D MAY 2005 REVISED AUGUST 2011 GENERAL-PURPOSE LOW-VOLTAGE COMPARATORS Check for Samples: LMV331-Q1 SINGLE, LMV393-Q1 DUAL 1FEATURES Qualified for Automotive Applications
Data sheet acquired from Harris Semiconductor SCHS038C Revised October 2003
Data sheet acquired from Harris Semiconductor SCHS038C Revised October 2003 The CD4035B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages
CD74HC4538-Q1 HIGH-SPEED CMOS LOGIC DUAL RETRIGGERABLE PRECISION MONOSTABLE MULTIVIBRATOR
Qualified for Automotive Applications Retriggerable/Resettable Capability Trigger and Reset Propagation Delays Independent of R X, C X Triggering From the Leading or Trailing Edge Q and Q Buffered Outputs
CD54/74HC221, CD74HCT221
Data sheet acquired from Harris Semiconductor SCHS166B November 1997 - Revised May 2000 CD54/74HC221, CD74HCT221 High Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description [ /Title
CD54HC194, CD74HC194, CD74HCT194
Data sheet acquired from Harris Semiconductor SCHS164G September 1997 - Revised May 2006 CD54HC194, CD74HC194, CD74HCT194 High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register Features Description
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 High Speed CMOS Logic Octal Buffer/Line Drivers, Three-State
Data sheet acquired from Harris Semiconductor SCHS167A November 1997 - Revised May 2000 CD54/74HC240, CD54/74HCT240, HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 High Speed CMOS Logic Octal Buffer/Line
SN54AC04, SN74AC04 HEX INVERTERS
SN54AC04, SN74AC04 HEX INVERTERS 2-V to 6-V V CC Operation Inputs Accept Voltages to 6 V Max t pd of 7 ns at 5 V SN54AC04...J OR W PACKAGE SN74AC04...D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1Y 2A 2Y
ORDERING INFORMATION T A PACKAGE ORDERABLE PART NUMBER. SOIC D Tape and reel SN74CBTD3306DR 40 C to85 C
5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Designed to Be Used in Level-Shifting Applications description/ordering information The SN74CBTD3306 features two independent line switches.
SN54ALS09, SN74ALS09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS
SN54ALS09, SN74ALS09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS SDAS084B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip
SN74LV374A-Q1 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Qualified for Automotive Applications Typical V OLP (Output Ground Bounce) 2.3 V at = 3.3 V, T A = 25 C Supports Mixed-Mode Voltage
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
1 SN74LVC1G126-Q1 www.ti.com... SCES467B JULY 2003 REVISED APRIL 2008 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT 1FEATURES Qualified for Automotive Applications ESD Protection Exceeds 2000 V Per MIL-STD-883,
SN54ALS38B, SN74ALS38B QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
SN54ALS38B, SN74ALS38B QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS SDAS196B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic
CD4541B. CMOS Programmable Timer High Voltage Types (20V Rating) Features. [ /Title (CD45 41B) /Subject. (CMO S Programmable. Timer High Voltage
CD4541B Data sheet acquired from Harris Semiconductor SCHS085E Revised September 2003 CMOS Programmable Timer High Voltage Types (20V Rating) [ /Title (CD45 41B) /Subject (CMO S Programmable Timer High
3.3 V Dual LVTTL to DIfferential LVPECL Translator
1 SN65LVELT22 www.ti.com... SLLS928 DECEMBER 2008 3.3 V Dual LVTTL to DIfferential LVPECL Translator 1FEATURES 450 ps (typ) Propagation Delay Operating Range: V CC 3.0 V to 3.8 with GND = 0 V
CD74HC221, CD74HCT221
Data sheet acquired from Harris Semiconductor SCHS66A November 997 - Revised April 999 CD74HC22, CD74HCT22 High Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description [ /Title (CD74
CD54HC4538, CD74HC4538, CD74HCT4538
Data sheet acquired from Harris Semiconductor SCHS123 June 1998 CD54HC4538, CD74HC4538, CD74HCT4538 High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator Features Description [ /Title
description/ordering information
µ SLVS060K JUNE 1976 REVISED APRIL 2005 3-Terminal Regulators Output Current Up To 500 ma No External Components High Power-Dissipation Capability Internal Short-Circuit Current Limiting Output Transistor
AM26C31-EP QUADRUPLE DIFFERENTIAL LINE DRIVER
1 1FEATURES Controlled Baseline One Assembly One Test Site One Fabrication Site Extended Temperature Performance of 55 C to 125 C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change
PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp
AVAILABLE OPTIONS PACKAGE VIOmax SMALL OUTLINE. PLASTIC DIP at 25 C (D) (P) 0 C to 70 C 5 mv LM306D LM306P
SLCS8A OCTOBER 979 REVISED OCTOBER 99 Fast Response Times Improved Gain and Accuracy Fanout to Series 5/7 TTL Loads Strobe Capability Short-Circuit and Surge Protection Designed to Be Interchangeable With
CD4070B, CD4077B. CMOS Quad Exclusive-OR and Exclusive-NOR Gate. Features. Ordering Information. [ /Title (CD40 70B, CD407 7B) /Subject
[ /Title (CD40 70B, CD407 7B) /Subject (CMO S Quad Exclu- sive- OR and Exclu- sive- NOR Gate) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS, pdip, cerdip, mil, Data sheet acquired
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State Description Features
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 [ /Title (CD74H C173, CD74H CT173) /Subject (High Speed CMOS Logic Quad D- Type Data sheet acquired from Harris Semiconductor SCHS158E February 1998 - Revised
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Data sheet acquired from Harris Semiconductor SCHS158E February 1998 - Revised October 2003 High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State [ /Title
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H March 1998 - Revised October 2003 Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger [ /Title
5-V Dual Differential PECL Buffer-to-TTL Translator
1 1FEATURES Dual 5-V Differential PECL-to-TTL Buffer 24-mA TTL Ouputs Operating Range PECL V CC = 4.75 V to 5.25 V with GND = 0 V Support for Clock Frequencies of 250 MHz (TYP) 3.5-ns Typical Propagation
SN74CBT3861DWR 10-BIT FET BUS SWITCH. description. logic diagram (positive logic)
SN74CBT3861 10-BIT FET BUS SWITCH SCDS061D APRIL 1998 REVISED OCTOBER 2000 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Latch-Up Performance Exceeds 250 ma Per JESD 17 description
AVAILABLE OPTIONS PACKAGE SMALL OUTLINE (D) The D package is available taped and reeled. Add the suffix R to the device type (i.e., LT1030CDR).
LT1030C QUADRUPLE LOW-POWER LINE DRIVER Low Supply Voltage... ±5 V to ±15 V Supply Current...500 µa Typical Zero Supply Current When Shut Down Outputs Can Be Driven ±30 V Output Open When Off (3-State)
description logic diagram (positive logic) logic symbol
SDAS074B APRIL 1982 REVISED JANUARY 1995 AS1004A Offer High Capacitive-Drive Capability Driver Version of ALS04B and AS04 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers
SN75124 TRIPLE LINE RECEIVER
SN75124 TRIPLE LINE RECEIER Meets or Exceeds the Requirements of IBM System 360 Input/Output Interface Specification Operates From Single 5- Supply TTL Compatible Built-In Input Threshold Hysteresis High
SN75157 DUAL DIFFERENTIAL LINE RECEIVER
SN75157 DUAL DIFFERENTIAL LINE RECEIVER Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendation V.1 and V.11 Operates From Single 5-V Power Supply Wide
LF411 JFET-INPUT OPERATIONAL AMPLIFIER
LF411 JFET-INPUT OPERATIONAL AMPLIFIER Low Input Bias Current, 50 pa Typ Low Input Noise Current, 0.01 pa/ Hz Typ Low Supply Current, 2 ma Typ High Input impedance, 10 12 Ω Typ Low Total Harmonic Distortion
ORDERING INFORMATION. SOIC DW Tape and reel SN74CBT3384ADWR
SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004L NOVEMBER 1992 REVISED JANUARY 2004 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels description/ordering information The SN74CBT3384A provides
CD54HC221, CD74HC221, CD74HCT221. High-Speed CMOS Logic Dual Monostable Multivibrator with Reset. Features. Description
Data sheet acquired from Harris Semiconductor SCHS166F November 1997 - Revised October 2003 CD54HC221, CD74HC221, CD74HCT221 High-Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210G August 1997 - Revised June 2006 High-Speed CMOS Logic Triple 3-Input OR Gate [ /Title (CD74H C4075,
CD54/74AC257, CD54/74ACT257, CD74ACT258
CD54/74AC257, CD54/74ACT257, CD74ACT258 Data sheet acquired from Harris Semiconductor SCHS248A August 1998 - Revised May 2000 Quad 2-Input Multiplexer with Three-State Outputs Features AC257, ACT257.............
SN74LVC1G32-Q1 SINGLE 2-INPUT POSITIVE-OR GATE
FEATURES Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval Supports 5-V V CC Operation Inputs Accept Voltages to 5.5 V Low
SN54ALS139, SN74ALS139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SN54ALS9, SN74ALS9 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Two Enable Inputs to Simplify Cascading and/or
SN74LVC2G32-EP DUAL 2-INPUT POSITIVE-OR GATE
www.ti.com SN74LVC2G32-EP DUAL 2-INPUT POSITIVE-OR GATE SCES543A FEBRUARY 2004 REVISED AUGUST 2006 FEATURES Controlled Baseline Typical V OHV (Output V OH Undershoot) >2 V at V CC = 3.3 V, T A = 25 C One
CD54HC221, CD74HC221, CD74HCT221. High-Speed CMOS Logic Dual Monostable Multivibrator with Reset. Features. Description
Data sheet acquired from Harris Semiconductor SCHS166F November 1997 - Revised October 2003 CD54HC221, CD74HC221, CD74HCT221 High-Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Data sheet acquired from Harris Semiconductor SCHS158E February 1998 - Revised October 2003 High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State [ /Title
CD54HC221, CD74HC221, CD74HCT221. High-Speed CMOS Logic Dual Monostable Multivibrator with Reset. Features. Description
Data sheet acquired from Harris Semiconductor SCHS166F November 1997 - Revised October 2003 CD54HC221, CD74HC221, CD74HCT221 High-Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description
description/ordering information
3-Terminal Regulators Output Current Up To 100 ma No External Components Required Internal Thermal-Overload Protection Internal Short-Circuit Current Limiting Direct Replacement for Industry-Standard MC79L00
CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060
CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 Data sheet acquired from Harris Semiconductor SCHS207G February 1998 - Revised October 2003 High-Speed CMOS Logic 14-Stage Binary Counter with Oscillator