High Efficiency Transformerless MOSFET Inverter for Grid-tied Photovoltaic System

Transcription

1 High Efficiency Transformerless MOSFET Inverter for Grid-tied Photovoltaic System Monirul Islam Power Electronics and Renewable Energy Research Laboratory (PEARL) Department of Electrical Engineering University of Malaya Kuala Lumpur, Malaysia S. Mekhilef, Senior Member, IEEE Power Electronics and Renewable Energy Research Laboratory (PEARL) Department of Electrical Engineering University of Malaya Kuala Lumpur, Malaysia Abstract This paper proposes a new high efficiency single phase transformer-less grid-tied photovoltaic (PV) inverter by using super-junction MOSFETs as main power switches. No reverse recovery issues are required for the main power switches and the blocking voltages across the switches are half of the DC input voltage in the proposed topology. Therefore, the superjunction MOSFETs have been used to improve the efficiency. Two additional switches with the conventional full H-bridge topology, make sure the disconnection of PV module from the grid at the freewheeling mode. As a result, the high frequency common mode (CM) voltage which leads leakage current is minimized. PWM dead time is not necessary for the proposed topology which reduces the distortion of the AC output current. The efficiency at light load is increased by using MOSFET as main power switches which increases the European Union (EU) efficiency of the proposed topology. The proposed inverter can also operate with high frequency by retaining high efficiency which enables reduced cooling system. The total semiconductor device losses for the proposed topology and several existing topologies are calculated and compared. Finally, the proposed new topology is simulated by MATLAB/Simulink software to validate the accuracy of the theoretical explanation. It is being manufactured to verify the experimental results. I. INTRODUCTION The interest in renewable-energy sources is successively increasing because of rising demand of the world s energy and increasing price of the other energy sources, together with considering the environmental pollution. Many renewable energy sources are now available; among them, PV is the most up-to-date technique to address the energy problems. Due to the large-scale manufacturing capability of the PV module, it is becoming increasingly cheaper during these last years. So the attempt to decrease the total grid-tied PV system cost is mostly depend on the price of grid-tied inverter [1-3]. Gridtied PV inverters which consists a line frequency transformer are large in size, make the entire system extensive and difficult to install. It is also a challenging task to increase the efficiency and reduce the cost by using high frequency transformer which requires several power stages [4, 5]. On the other hand, transformer-less grid-tied inverters have the benefits of lower cost, higher efficiency, smaller size, and weight [6-12]. However, there exist a galvanic connection between the power grid and the PV module due to the exclusion of transformer which form a CM leakage current. This CM leakage current increases the grid current harmonics and system losses and also creates strong conducted and radiated electromagnetic interference [13-15]. In order to minimize the CM leakage current of the transformer-less grid-tied PV inverters, depth research have been pursued by many researchers of different countries [6-11, 13, 16-19]. Most of the inverters described in literature and commercially available show the European Union (EU) efficiency in the range of 96%-98% [16]. Hence, to improve the efficiency of the transformer-less inverters, several topologies by using MOSFETs as main switches have been proposed in [16, 20]. Super-junction MOSFETs can escape the fixed voltage drop and turn-off losses caused by tail current. Yu et al. proposed a H6_type MOSFET inverter by removing the use of low proficient IGBTs as shown in Fig. 1(a) [20]. The indicated peak and EU efficiencies of H6_type inverter on 300W prototype circuit with 180V DC bus voltage and 30 khz operating frequency were 98.3% and 98.1%, respectively. In active mode of H6_type MOSFET inverter, the grid current flows through three switches, as a result, higher conduction losses still remain. Another difficulty is that the anti-parallel diodes of MOSFETs will be activated if a phase shift is occurred in the inverter output voltage and current. Accordingly, the dependability of the system is reduced because of MOSFET anti-parallel diode reverse recovery issues. GU et al. proposed high reliability and efficiency (HRE) MOSFET inverter shown in Fig. 1(b) [16]. HRE topology splits the ac sides into two independent parts in the positive and negative half cycle of grid current if compared with HERIC topology. The reported maximum and California energy commission (CEC) efficiencies of the HRE inverter on a 5kw prototype circuit with 20 khz switching The authors wish to acknowledge the financial support from the University of Malaya through HIR-MOHE project UM.C/HIR/MOHE/ENG/24 and UMRG project no. RP015A-13AET /14/$ IEEE 3356

2 (a) (b) (c) Figure 1. Some existing transformer-less topologies for grid connected PV inverter (a) H6 topology proposed in [20] (b) Topology proposed in [16] (c) Topology proposed in [6] frequency were 99.3% and 99%, respectively. The main topology consist six MOSFETs and six diodes which increase the complexity of the circuit and the initial cost. Another high efficiency inverter called dual-parallel-buck converter shown in Fig. 1(c), which consist four CoolMOS switches and four SiC diodes. The indicated peak and EU efficiencies of dualparallel-buck converter on a 4.5kW prototype circuit with 345V input voltage and 16 khz operating frequency were 99% and 98.8%, respectively. The main drawback of this topology is that the grid will be short circuit if no dead time is present between the switches S3 and S4, through which grid is directly connected. The main two key issues for the transformer-less PV inverters are that (1) the inverter should not cause of any leakage current and (2) achieve higher efficiency over a wide load range. In order to hold these two main issues, a new single phase transformer-less grid-tied PV inverter topology is proposed in this paper. The key features of the presented inverter are: (1) No dead time is required because the switches in the same phase leg never turned-on all during the same SPWM cycle, as a result, AC current distortion at output is lower (2) Two additional switches and two diodes make sure the disconnection of PV module from the grid at the freewheeling mode which minimize the CM leakage current, (3) The blocking voltage of all the MOSFETs are half of the DC input voltage and the inductor current flows through two switches in the positive half cycle as well as three switches in the negative half cycle of grid current. Therefore, the switching and conduction losses are reduced. Detail operation principle of the proposed inverter with three-level output by employing unipolar SPWM is described in this paper. The efficiency of the proposed inverter is computed with 20 khz and 40 khz switching frequencies and compared. This paper is prepared as follows: The new converter structure and operating principle with the unipolar SPWM control scheme is investigated in section II. The total device losses and efficiency of the proposed converter have been calculated and compared in section III. Results are narrated in section IV and section V concludes the paper. II. PROPOSED UNIPOLAR SPWM MODULATED CONVERTER A. Circuit Configuration Fig. 2(a) shows the proposed transformer-less PV inverter topology which consist six MOSFET switches (G1-G6) and two diodes (D1-D2). Switches G5 and G6 are commutates with the switching frequency to de-couple the converter from the grid in the freewheeling mode. L A, L B, and C o make up the LCL type filter connected to the grid. V pv and C dc represent the input voltage and DC link capacitor. Unipolar SPWM can employ to the proposed topology with three-level output. The super-junction MOSFETs can be utilized in the proposed topology because no reverse-recovery issues are required in proposed configuration of the inverter. Consequently, the efficiency of the entire PV system is increased. (a) (b) Figure 2. Proposed transformer-less grid connected PV inverter (a) Structure of the converter (b) Gate drive signals B. Operating Principle of the Proposed Topology Grid tied photovoltaic system generally operate at unity power factor. Fig. 2(b) shows the waveform of the switching pattern for the proposed topology. As can be seen, (G1, G4) and (G2, G5) commutates at the switching frequency with the identical commutation order in the positive and negative half cycle of grid current, respectively. Four operation modes are proposed that generate the output voltage state of +V PV, 0, and V PV. Fig. 3 shows the operating principles of the proposed topology, where V AN and V BN are the voltages of the full H- bridge inverter from mid-point A and B of the bridge leg to the reference point N. 1) Mode 1 is the active mode in the positive half cycle of grid current. When G1 and G4 are turned-on, the voltage V AN = V PV and V BN = 0, thus V AB = V PV and the CM voltage, V cm = (V AN + V BN )/2 = V PV /

3 Figure 3. Operation principle of the proposed topology 2) Mode 2 is the freewheeling mode in the positive half cycle of grid current as indicated in Fig. 3(b). The freewheeling current flows through G6 and D2. In this mode, V AN = V BN = V PV /2, thus V AB = 0 and the CM voltage, V cm = (V AN + V BN )/2 = V PV /2. 3) Mode 3 is the active mode in the negative half cycle of grid current. Like as mode 1, when G2, G3 and G5 are turned-on, the voltage V AN = 0 and V BN = V PV, thus V AB = - V PV and the CM voltage, V cm = (V AN + V BN )/2 = V PV /2. 4) Mode 4 is the freewheeling mode in the negative half cycle of grid current. When G5 and G2 are turned-off, the freewheeling current flows through G3 and D1. In this mode, V AN = V BN = V PV /2, thus V AB = 0 and the CM voltage, V cm = (V AN + V BN )/2 = V PV /2. As analysis above, the CM voltage remains constant during the four commutation modes of the proposed inverter and equals to V PV /2. As a result, the inverter is hardly to generate CM leakage current. Furthermore, the blocking voltages across all switches are half of the DC bus voltage; thus, the switching losses are reduced significantly. TABLE I. PARAMETERS FOR LOSS CALCULATION Inverter Parameter Value Input Voltage 400VDC Grid Voltage / Frequency 230V / 50Hz Rated Power 5000 W AC output current 21.1A Switching Frequency 20kHz III. POWER DEVICE LOSSES AND EFFICIENCY CALCULATION AND COMPARISON WITH SEVERAL EXISTING TOPOLOGIES It is difficult to estimate the total power device losses in the power electronic circuit for predicting the maximum efficiency. In this section, the power losses by the switches of the proposed topology and the topologies proposed in [16, 20] are calculated with the same circuit parameters given in TABLE I. It is necessary to take into account that the calculation of the losses is based on theory and its accuracy depends on the device data sheet accuracy. A. Switching and Conduction Losses for IGBT switch: Fig. 4 shows the turn-on and turn-off behavior of the selected IGBTs. The turn-on and turn-off losses of the IGBTs are calculated using the equation (1) and (2), respectively [10, 21]. W IGBT, turn -on VCE ( IL + IRR )( tr + ta ) IL IRR = + VCEtb ( + ) (1) V 11. CEILt VCEILt d f VCEILttail W + + IGBT, turn -off = (2) where I L = load current; I RR = reverse recovery current; t r = rise time; t f = fall time; t a & t b = diode reverse recovery time; t d = turn-off delay time; t tail = tail time; V CE = blocking voltage of the IGBT switches. Figure 4. Hard switching waveform of IGBT switches The conduction losses for IGBTs can be calculated using equation (3) IGBT, on - state ( ) ( ) W = V on I CE L DT t t t s r + a + b (3) where V CE (on) is the IGBT on state voltage. The total IGBT power losses are calculated by integrating in a grid period P IGBT, loss 1 () () N W i + W i IGBT, turn - on IGBT, turn -off = (4) T g i= 1 + W () i IGBT, on state where T g is the grid period, i denote the switching process and N represent the total number of switching time within a grid period. B. Switching and Conduction Losses for Diode: In order to calculate the switching losses of the diode, only the turn-off losses are taken into account and turn-on losses are neglected [22]. Fig. 4 shows the turn-on and turn-off behavior of the diode. The turn-off losses of the diode can be computed using equation (5) [10, 23] W Diode, turn -off VF( IL + IRR)( tr + ta) IRRtb ( Vd + VF ) = + (5)

4 where V F is the on-state voltage of the diode and V d is the diode s blocking voltage across the cathode and anode. The conduction losses of diode can be calculated using equation (6) ( 1 ) ( + + ) W = F L s d f tail Diode _ con V I D T t t t (6) The total diode power losses can be calculated by integrating in a grid period 1 = N ( () + ()) (7) T i = 1 P W i W i Diode, loss g Diode, turn - off Diode _ con C. Switching and Conduction Losses for MOSFET switch: The duty cycle for on-stage and off-stage of unipolar sinusoidal pulse width modulated inverter is calculated using equation (8) and (9), respectively = M sin( ωt) (8) D active D zero = 1 M sin( ωt) (9) where M is the modulation index and ω is the angular frequency of the inverter output current. The output current of the inverter can be expressed as i() t I ( ωt) = m sin (10) where I m is the peak output current of the inverter. The conduction losses for the MOSFET switches can be computed by the equation (11) [16] 1 P = itv () () td () tdωt Con _ MOSFET ds active 2π 0 = 2 ImRds 2M 3π π (11) For MOSFET devices, the switching losses are mainly the capacitive turn-on losses resulting from the discharge of the output capacitor of MOSFET during turn-on. Usually, energy losses for turn-on of the MOSFET can be achieved from device data sheet. So the switching power losses for MOSFET can be defined as P = f E (12) sw_ MOSFET sw oss switch and MURP8100E (1000V, 8A) as diode were chosen. By fixing the parameters from the data sheets of the selected devices, the total device losses at different EU output power for the proposed topology, H6_type MOSFET inverter topology [20], and high reliability and efficiency (HRE) inverter topology [16] have been calculated and shown as histogram in Fig. 5. It is clear that the total semiconductor device losses in the H6_type MOSFET inverter are highest due to higher conduction losses in the active mode. On the other hand, total device losses in the proposed topology are very close to the HRE topology. Figure 5. Total device losses distribution for the proposed topology, H6_type MOSFET topology and HRE topology at different EU output power D. Loss Reduction by Replacing IGBTs with MOSFETs as Main Power Switches for the Proposed Topology: In this section, loss reduction by replacing IGBTs with MOSFETs as main power switches for the proposed topology is investigated to highlight the benefit of super-junction MOSFETs. (a) Another cause of switching losses is the diode reverserecovery losses of the off-state diode. The reverse-recovery losses of diode can be defined as IRR IRR W = V Diode _ RR d IL + ta + t b 2 3 (13) The total switching losses in the entire grid cycle for the causes of diode reverse-recovery is computed by integrating (13) as Im IRR IRR P = V Diode _ RR d fsw + ta + tb π 4 (14) 6 CoolMOS TM power transistor IPW60R041C6 (600V, 75A) as MOSFET switch, STGW20NC60VD (600V, 30A) as IGBT (b) Figure 6. Total device losses for the proposed topology by employing IGBTs and MOSFETs as power switches (a) 20kHz operating frequency (b) 40kHz operating frequency. The total semiconductor power device losses in the proposed topology by using MOSFETs and IGBTs as main power switches are calculated at different EU output power with 20 khz and 40 khz operating frequencies which is illustrated in Fig. 6. It is clear that the total power device 3359

5 Figure 7. Drain-source voltage waveform of the switches G1, G4, and G6. Figure 9. Waveforms of grid current i g, CM leakage current i cm, and differential voltage V AB by applying unipolar SPWM. Figure 8. Waveforms of V AN, V BN, and V cm by employing unipolar SPWM. losses in the proposed topology are more than 2.5% for all EU output power with 40 khz operating frequency, when IGBTs are used as main power switches as shown in Fig. 6(b). The total losses of the proposed inverter will be more than 3% if the gate driver loss, control board loss, and output filter loss are included. Consequently, the efficiency of the proposed inverter will be less than 97% which is lower if compared with the conventional transformer-less grid-tied PV inverter. On the other hand, if MOSFETs are employed as main power switches, the total semiconductor power device losses are less than 1% for the output power more than 10% of rated 5kw inverter and even less than 1.5% for all EU output power. Consequently, the EU efficiency of the inverter will not be less than 98.5% with including the other losses which is more than the commercially available transformer-less PV inverter. Therefore, the proposed MOSFET inverter can be operated with high switching frequency as well as lower output current ripples by maintaining high-level system efficiency. IV. RESULTS In order to verify theoretical analysis, the proposed inverter has been simulated in MATLAB/Simulink software environment by using the parameters given in Table II. Fig. 7 shows the drain-source voltage waveforms of G1, G4 and G6. It can be seen that the blocking voltages of all the switches are half of the DC input voltage. Therefore, the switching losses are minimized, and the results fulfill the theoretical analysis. Figure 10. Efficiency of the proposed topology with 20kHz and 40kHz switching frequencies. TABLE II. PARAMETERS USED IN SIMULATION Inverter Parameter Value Input Voltage 400VDC Grid Voltage / Frequency 230V / 50Hz Rated Power 1000 W AC output current 4.1A Switching Frequency 20kHz DC bus capacitor 470µF Filter capacitor 2µF Filter Inductor L A, L B 2mH PV parasitic capacitor Cpv1, Cpv2 75nF The waveforms of V AN, V BN, and V cm by employing unipolar SPWM are shown in Fig. 8. It indicates that the CM voltage remains constant during all commutation modes. As a result, the generating CM leakage current shown in Fig. 9 is effectively limited within the peak value 50mA and RMS value 10mA. This peak and RMS values are lower in magnitude corresponding to German standard VDE The waveform of grid current i g under 230V rms grid voltage shown in Fig. 9, shows that the proposed inverter presents low harmonic distortion which meet the requirement of IEEE Std [24]. As seen in Fig. 9, the inverter output voltage V AB has three levels, +V PV, 0, and -V PV. It designates that the proposed topology is modulated with unipolar SPWM with excellent differential mode characteristics. 3360

6 The efficiency of the proposed topology with 20 khz and 40 khz operating frequencies are calculated and compared which is illustrated in Fig. 10. Note that the presented efficiency diagram covers the total power device losses but it does not contain the losses for the control circuit. It is obvious that the efficiency of the proposed topology with 40 khz operating frequency is very close to the efficiency with 20 khz which allows the proposed inverter to operate at higher switching frequency. The EU efficiency is calculated by combining several weighted factors at various output powers as expressed in equation (15) [11]. The EU efficiency of the proposed topology, H6_type MOSFET inverter topology and the HRE topology are 99.18, 99.11, and 99.24, respectively. η = 0.03η η η η η η (15) EU 5% 10% 20% 30% 50% 100% V. CONCLUSION In this paper, a new high efficiency transformer-less gridtied inverter is presented. The main advantages of the proposed topology are as follows: (1) High efficiency over a wide load range is achieved by using MOSFETs as main power switches because their anti-parallel diodes are inactive, (2) The CM mode voltage remains constant during all operation modes, so the leakage current is well suppressed, (3) The excellent differential mode characteristics are achieved with unipolar SPWM, (4) Output current distortion is lower because PWM dead time is not required for the proposed topology, (5) Proposed inverter can operate with high operating frequency to reduce the size of the output filter, while maintaining high efficiency. The proposed topology has been validated by simulation with MATLAB/Simulink software and it is being manufactured to verify the experimental results. As a conclusion, the proposed inverter is enormously suitable for single phase grid-tied PV application. REFERENCE [1] R. Mechouma, B. Azoui, and M. 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