IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER Monirul Islam and Saad Mekhilef, Senior Member, IEEE

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1 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER Efficient Transformerless MOSFET Inverter for a Grid-Tied Photovoltaic System Monirul Islam and Saad Mekhilef, Senior Member, IEEE Abstract The unipolar sinusoidal pulse width modulation fullbridge transformerless photovoltaic (PV) inverter can achieve high efficiency by using latest superjunction metal oxide semiconductor field-effect transistor (MOSFET) together with silicon carbide (SiC) diodes. However, the MOSFETs are limited to use in transformerless PV inverter due to the low reverse-recovery characteristics of the body diode. In this paper, a family of new transformerless PV inverter topology for a single-phase grid-tied operation is proposed using superjunction MOSFETs and SiC diodes as no reverse-recovery issues are required for the main power switches for unity power operation. The added clamping branch clamps the freewheeling voltage at the half of dc input voltage during the freewheeling period. As a result, the common-mode voltage kept constant during the whole grid period that reduces the leakage current significantly. In addition, dead time is not necessary for main power switches at both the high-frequency commutation and the grid zero crossing instant, results low-current distortion at output. Finally, a 1-kW prototype is built and tested to verify the theoretical analysis. The experimental results show 98.5% maximum efficiency and 98.32% European efficiency. Furthermore, to show the effectiveness, the proposed topology is compared with the other transformerless topologies. Index Terms Common-mode (CM) voltage, converter, European efficiency, grid connected, high efficiency, leakage current, photovoltaic (PV), transformerless. I. INTRODUCTION RECENTLY, transformerless inverter has been found as one of the excellent solutions for grid-tied photovoltaic (PV) application because of its higher conversion efficiency, lower cost, smaller size, and light weight if compare with one s consist transformer [1], [2]. However, the main drawback of transformerless inverter is the leakage current issues that need to be addressed very carefully. Due to the loss of galvanic isolation between the PV module and the grid, a direct path is formed to flow leakage current which generally depends on the nonnegligible parasitic capacitance between the PV module and the ground, and the amplitude of fluctuating common-mode (CM) voltage. The fluctuation of CM voltage depends on the topology structure and the control scheme. As a result of leakage current flowing through the system, the grid current harmonics and system losses Manuscript received August 20, 2014; accepted November 4, Date of publication November 17, 2015; date of current version March 25, This work was supported by the University of Malaya through HIR-MOHE Project UM.C/HIR/MOHE/ENG/24 and UMRG Project RP015D-13AET. Recommended for publication by Associate Editor J. A. Cobos. The authors are with the Power Electronics and Renewable Energy Research Laboratory, Department of Electrical Engineering, University of Malaya, Kuala Lumpur 50603, Malaysia ( monir04eee@yahoo.com; saad@um.edu. my). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TPEL increase, strong conducted and radiated electromagnetic interference are created, and more significantly, gives rise to safety issues [3], [4]. Another important concern of transformerless inverter is the efficiency that can be improved by the optimal design. Most of the inverters described in the literature and commercially available show the European efficiency in the range of 96% 98% [5], [6]. These two issues (efficiency and leakage current) are the major force in pushing progressive development of a transformerless grid-tied PV inverter [1], [5], [6]. In order to reduce the leakage current, a lot of in-depth researches have been conducted in the literature [6] [22], where a new freewheeling path has been introduced to decouple the PV module from the grid during freewheeling period. However, the switches junction capacitance that cannot be ignored in the practical application may have an impact on the leakage current [13], [23]. It is presented in [24] that to completely eliminate the leakage current, the CM voltage needs to be clamped to the midpoint of the dc input voltage instead of only disconnecting the PV module from the grid. On the other hand, to improve the efficiency, the transformerless inverter can be implemented using superjunction MOSFET and SiC diodes. The superjunction MOSFETs can avoid the fixed voltage drop and turn-off losses caused by tail current, thereby reducing the conduction and switching losses. However, due to poor reverse recovery of MOSFETs slow body diode, it is limited to use in transformerless inverter. In the following, MOSFET-based transformerless topologies for grid-tied PV application will be reviewed and discussed based on their circuit structure, efficiency, and CM voltage clamping capability. The most attractive transformerless topology is the highly efficient and reliable inverter concept (HERIC) topology which is shown in Fig. 1(a). This topology has been implemented in some commercial inverters, especially those from Sunway s converter [25]. Two switches are added in the ac side of a full-bridge (FB) topology to decouple the PV module from the grid during the freewheeling period [26]. Though the PV module is decoupled from the grid, a fluctuating CM voltage could be observed because the freewheeling path potential is not clamped at the half of dc input voltage. As seen in Fig. 1(b), the topology which has been proposed in [10] replaces the two switches freewheeling branch with one bidirectional switch and four diodes called H- bridge zero-voltage rectifier (HB-ZVR) topology. Also, another diode (D 5 ) has been added for better eliminating the leakage current. The clamping function of this topology has been done using D 5 which allows one-directional clamping, only if the freewheeling path potential (V AN V BN ) is higher than the dclink midpoint voltage. As a result, CM voltage fluctuation could be observed when the reverse condition is occurred which is very less than HERIC topology. In these two topologies, the IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See standards/publications/rights/index.html for more information.

2 6306 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016 Fig. 1. Some existing MOSFET-based transformerless topologies for grid-tied PV application: (a) HERIC topology proposed in [26]. (b) HB-ZVR topology proposed in [10]. (c) H5 topology proposed in [27]. (d) oh5 topology proposed in [9]. (e) H6 topology proposed in [16]. grid current flows through two switches during the whole grid period; as a result, conduction loss is low. Fig. 1(c) shows another explicit transformerless topology proposed in [27] called H5 topology, made up by adding an extra switch in the dc side of an FB inverter. In this topology, the freewheeling current flows through S 1 and body diode of S 3 during positive half cycle, and S 3 and body diode of S 1 during negative half cycle. As a result, the switches S 1 and S 3 could not be implemented with MOSFETs due to the low reverse recovery of the MOSFET body diode. Another disadvantage is that the output current flows through three switches in the active mode for the complete grid cycle, thus higher conduction losses are present. A fluctuating CM voltage could also be observed because the freewheeling path potential is not clamped at the midpoint of dc link. An extension of H5 topology is presented in [9] called optimized H5 (oh5) topology, where an extra switch (S 6 ) has been added with the H5 topology to clamp the CM voltage at the half of input voltage as demonstrated in Fig. 1(d). Unfortunately, a dead time must have to be added between the gate signals of the switches S 5 and S 6 to avoid the short-circuit of the input split capacitor C dc1. As a result, CM voltage fluctuates in dead time [9]. Another disadvantage of this topology is that higher conduction losses still remain due to the grid current flows through three switches in the active mode. Gonzalez et al. proposed another topology in [16] called full-bridge with dc bypass which is also named as H6 topology. It employs two switches and two diodes in the dc side of FB inverter. The CM characteristics of this topology are better than other topologies because of the bidirectional clamping branch. During freewheeling mode, either diode D 1 or D 2 can be conducted based on whether the freewheeling path potential (V AN V BN ) is higher or lower than half of the dc-link voltage. In this topology, leakage current removal effect depends only on the turn-on speed of the clamping diodes. However, this topology can be implemented with two MOSFET switches (S 5 and S 6 ) only. In addition, the grid current flows through four switches, thus higher conduction losses are also present. Considering the advantages and the drawbacks of the transformerless inverter mentioned earlier, a family of new transformerless topologies for a single-phase grid-tied PV system is proposed based on two asymmetric phase legs in this paper. The key features of the proposed inverter are: 1) no dead time is required because the switches in the same phase leg are never all turned-on during the same SPWM cycle; as a result, current distortion at output is lower, 2) the CM voltage is kept constant at half of the dc input voltage because of the added clamping branch, and 3) during the positive and negative half cycle, the inductor current flows through two and three switches, respectively, thus the conduction loss is lower. The detailed operation principles and the control scheme to reduce the dc current injection are described in this paper. An investigation has been conducted to calculate the device power losses and to make a detail comparison with the topologies presented in Fig. 1. Finally, the experimental results validate the proposed topology. At last, a comparison table has been summarized based on the experimental data to show the effectiveness of the proposed topology. This paper is structured as follows. The family of the new topology structure, operating principle, and the control scheme is presented in Section II. The leakage current for the proposed topology, and the power device loss calculation and comparison are investigated in Section III. The experimental results are given in Section IV and Section V concludes the paper.

3 ISLAM AND MEKHILEF: EFFICIENT TRANSFORMERLESS MOSFET INVERTER FOR A GRID-TIED 6307 Fig. 2. MOSFET-based phase legs for transformerless inverter: (a) HERIC method. (b) H5 method. (c) Modification of an HERIC method. (d) Modification of an H5 method. II. PROPOSED TOPOLOGY AND MODULATION STRATEGY A. Derivation Method of the Proposed Topology The traditional MOSFET-based phase legs of transformerless inverter are shown in Fig. 2(a) and (b). In order to ensure high efficiency, a modification is made in Fig. 2(a) and (b) by replacing IGBTs with MOSFETs and diodes which is shown in Fig. 2(c) and (d). By combining these two phase legs, a family of new transformerless topologies is derived based on the ac decoupling and asymmetric phase legs. The followings are the derivation steps of the proposed new topologies: 1) first, IGBT switches of the HERIC and H5 methods are replaced with MOSFETs and diodes to boost the efficiency; 2) next, combine these two phase legs to derive new topology. By changing the position of the freewheeling switches (S 3 and D 1 ), the family of the new topologies is derived; 3) finally, to clamp the CM voltage at the half of the dc input voltage, a clamping branch consisting of a switch and a diode with a capacitor divider is introduced. B. Circuit Configuration The family of the proposed transformerless PV inverter topology is depicted in Fig. 3 which is derived according to the derivation method described in the prior section, where S 1,S 2, S 4, and S 5 are high-frequency switches, and S 3 and S 6 are lowfrequency freewheeling switches. The unidirectional clamping branch is constructed using switch S 7 and diode D 3 with a capacitor divider (C dc1 and C dc2 ) which clamps the CM voltage at the midpoint of dc link. L A,L B, and C o make up the LCtype filter connected to the grid and V pv represent the input dc voltage. The unipolar SPWM can be employed to the proposed topology with three-level output voltage. The MOSFET power Fig. 3. Family of the proposed transformerless grid-connected PV inverter topologies: (a) Circuit structure A, (b) circuit structure B, (c) circuit structure C, and (d) circuit structure D. switches are utilized as no reverse-recovery issues are required for the proposed configuration of the inverter for unity power factor operation. Consequently, the efficiency of the entire PV system is increased. C. Operating Principle In order to analysis and verify, the circuit structure A is taken as an example. Fig. 4 shows the switching pattern for unity power factor operation, where the G 1,G 2,G 3,G 4,G 5,G 6, and G 7 are the gate signals of the switches S 1,S 2,S 3,S 4,S 5, S 6, and S 7. As can be seen S 1,S 4 and S 2,S 5 commutate at the switching frequency with the identical commutation order in the

4 6308 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016 Fig. 4. Gate drive signals of the proposed topology for circuit structure A. positive and negative half cycle of the grid current, respectively. In Fig. 5, the operating principles of the proposed topology are shown. Four operation modes are proposed to generate the output voltage state of +V PV, 0, and V PV, which can be explained as follows. 1) Mode 1 is the active mode in the positive half cycle of the grid current. When S 1 and S 4 are turned-on, the inductor current i L increases linearly through grid. In this mode, V AN = V PV and V BN =0, thus V AB = V PV and the inductor current i L (t) = V PV v g (t). (1) L 2) Mode 2 is the freewheeling mode in the positive half cycle of the grid current, as indicated in Fig. 5(b). The inductor current i L flows through S 6 and D 2, and reduces linearly under the effect of grid voltage. In this state, V AN falls and V BN rises until their values are equal. If the voltages (V AN V BN ) are higher than half of the dc-link voltage, freewheeling current flows through S 7 and D 3 to the midpoint of the dc link, results V AN and V BN are clamped at V PV /2. Therefore, at mode 2, V AN = V PV /2,V BN = V PV /2, the inverter output voltage V AB =0and the inductor current i L (t) = v g (t). (2) L 3) Mode 3 is the active mode in the negative half cycle of grid current. Similar to mode 1, when S 2,S 3, and S 5 are turnedon, the inductor current increases in the opposite direction. In this mode, the voltage V AN =0and V BN = V PV, thus V AB = V PV and the inductor current i L (t) = V PV v g (t). (3) L 4) Mode 4 is the freewheeling mode in the negative half cycle of grid current. When S 5 and S 2 are turned-off, the inductor current flows through S 3 and D 1. Similar to mode 2, if the voltages (V AN V BN ) are higher than half of the dc-link voltage, freewheeling current flows through S 7 and D 3 to the midpoint of the dc link, results the voltages V AN and V BN are clamped at V PV /2. Therefore, in this Fig. 5. Operating principle of the proposed topology: (a) Active and (b) freewheeling modes in the positive half cycle of the grid current, (c) active and (d) freewheeling modes in the negative half cycle of the grid current. mode, V AN = V BN = V PV /2,V AB =0, and the inductor current i L (t) = v g L (t). (4) As described above, the freewheeling path potential is clamped at the midpoint of the dc link during freewheeling period of positive and negative half cycle. As a result, the inverter hardly generates any leakage current. It can also be seen that the antiparallel diodes of the MOSFETs remained inactive during the whole operation period. Therefore, the proposed topology could be implemented utilizing MOSFET switches. However, the body diode will be activated if a phase shift is occurred in the inverter output voltage and current. Accordingly, the dependability of the system will be reduced because of the MOSFET antiparallel diode low reverse-recovery issues.

5 ISLAM AND MEKHILEF: EFFICIENT TRANSFORMERLESS MOSFET INVERTER FOR A GRID-TIED 6309 Fig. 9. domain. Complete control diagram of the proposed topology in a Laplace Fig. 6. Control block of the proposed topology. Fig. 7. (a) Block diagram of the PR controller. (b) Block diagram of the dc suppression loop. Fig. 8. Equivalent model of the output filter in a Laplace domain. D. Control Technique In case of transformerless inverter, dc current injection into the utility grid is an important issue that may cause saturation of distribution transformer, increased loss, and abnormal operation of the load connected to the grid. In order to suppress the dc current injection into the utility grid, several control strategies have been investigated in the literature [28] [30]. Based on the control technique proposed in [28], an improved control strategy, as depicted in Fig. 6, is implemented to control the proposed topology. The control block consists of a dc suppression loop, a grid current controller, and a phase-locked loop to synchronize with the grid current. The dc suppression loop is composed of a differential amplifier, a low-pass filter, and a dc controller. Since the output of the low-pass filter of dc suppression loop is constant in steady state, so a proportional-integral (PI) controller is used to control the dc-offset voltage. On the other hand, grid current is sinusoidal and the proportional-resonant (PR) controller has better performance of tracking the reference signal if compared to the normal PI controller and repetitive controller. Therefore, if compared with the control scheme proposed in [28], a PR controller is selected to control the grid current of the proposed topology. The block diagram of the PR controller and dc suppression loop is shown in Fig. 7, where G PR (s),g d (s), and G PI (s) are the transfer function of fundamental current controller, processing and PWM delay, and offset voltage controller, respectively. The transfer functions are given below [31], [32] G PR (s) =K pi + Kii s s 2 + ωf 2 (5) 1 G d (s) = (6) 1+1.5T s s G PI (s) =K pdc + Kidc 1 (7) s where K pi and K ii are the proportional and resonant gain of the current controller, K pdc and K idc are the proportional and integral gain of the offset voltage controller, ω f is the fundamental frequency, and T s is the sampling period. Since an LC filter (LC f ) has been used as an output filter; thus the system at ac side can be described as follows: di g (t) dt = v AB (t) L C f d 2 v g (t) dt 2 In Laplace domain, (8) can be rewritten as I g (s) = V AB (s) Ls C f s 2 V g (s) V g (s) Ls v g (t) L. (8) where i g and v g are grid current and voltage, and V AB is the inverter output voltage. Consequently, the equivalent model of the output filter can be drawn as Fig. 8. Henceforth, according to the above illustration, the overall control diagram can be depicted as shown in Fig. 9, where G dc (s) is the feedback gain of the dc suppression loop. III. LEAKAGE CURRENT ANALYSIS AND POWER DEVICES LOSS CALCULATION A. Leakage Current Analysis for the Proposed Topology The PV module generates an electrically chargeable surface area which faces a grounded frame. In case of such configuration, a capacitance is formed between the PV module and the ground. Since this capacitance occurs as an undesirable side effect, it is referred as parasitic capacitance. Due to the loss of galvanic separation between the PV module and the grid, a CM resonant circuit can be created. An alternating CM voltage that depends on the topology structure and control scheme, can electrify the resonant circuit and may lead to high ground leakage (9)

6 6310 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016 TABLE I ANALYSIS OF POWER DEVICES OPERATION Parameters H5 HERIC H6 oh5 Proposed Fig. 10. Equivalent CM model of the proposed topology. Total MOSFET Semiconductors IGBT Diodes Voltage stress of the switches V PV V PV / Switching loss MOSFET IGBT Conduction loss v g > 0 MOSFET IGBT v g < 0 MOSFET IGBT Freewheeling MOSFET loss IGBT Diodes TABLE II CALCULATEDDEVICES TOTAL POWER LOSS Total power device losses (W) Fig. 11. Simplified CM model at switching frequency. Output Power (W) H5 topology HERIC topology H6 topology oh5 topology Proposed topology TABLE III SPECIFICATION OF THE PROTOTYPE Fig. 12. Simplified single-loop CM model. Inverter Parameter Value current [12], [24], [33]. In order to analyze the CM characteristics, an equivalent circuit of the proposed topology as shown in Fig. 10 can be drawn, where V AN, and V BN are the controlled voltage source connected to the negative terminal N, L CM and C CM are the CM inductor and capacitor, C PVg is the parasitic capacitance, and Z g is the grid impedance. According to the definition of CM and differential-mode (DM) voltage V CM = 1 2 (V AN + V BN ) (10) V DM = V AN V BN (11) where V CM and V DM are, respectively, the CM and DM voltages. Solving (10) and (11), V AN and V BN can be expressed as follows: V AN = V CM V DM (12) V BN = V CM 1 2 V DM. (13) In order to illustrate the CM model at switching frequency, (12) and (13) have been replaced for the bridge leg in Fig. 10. The grid is a low-frequency (50 60 Hz) voltage source; thus, Input Voltage 400 V DC Grid Voltage/Frequency 230 V/50 Hz Rated Power 1000 W AC output current 4.2 A Switching Frequency 20 khz DC bus capacitor 1 mf Filter capacitor 2.2 μf Filter Inductor L A,L B 1mH PV parasitic capacitor Cpv1, Cpv2 75 nf IGBT switches STGW20NC60VD MOSFET switches SPW47N60C3 Diode (D 1 D 2 ) IDH08SG60C Controller dspace 1104 the impact of grid on the leakage current can be neglected [33]. The DM capacitor C o can also be removed since it has no effect on the leakage current. Consequently, the simplified highfrequency CM model of the proposed topology could be drawn as Fig. 11. The equation for the total CM voltage can easily be derived from Fig. 11 as V tcm = V CM + V DM 2 L B L A L A + L B (14) where V tcm represent total CM voltage. Finally, the simplified single-loop CM model of the proposed topology is derived in

7 ISLAM AND MEKHILEF: EFFICIENT TRANSFORMERLESS MOSFET INVERTER FOR A GRID-TIED 6311 Fig. 13. Total devices power loss distribution for the H5, HERIC, H6, oh5, and proposed topologies at different output power. Fig. 14. Laboratory prototype. Fig. 12. In the proposed inverter if L A = L B for a well-designed circuit with symmetrically structured magnetics, (14) can be rewritten as follows: V tcm = V CM = 1 2 (V AN + V BN ) = constant. (15) According to the operation principle of the proposed topology presented in Section II-C, the total CM voltages can be calculated for each mode of operation as follows: Mode 1 : V tcm = 1 2 (V AN + V BN )= 1 2 (V PV +0)= 1 2 V PV (16) Mode2 : V tcm = 1 2 (V AN + V BN )= 1 2 (1/2V PV +1/2V PV ) = 1 2 V PV (17) Mode3 : V tcm = 1 2 (V AN + V BN )= 1 2 (0 + V PV)= 1 2 V PV (18) Mode4 : V tcm = 1 2 (V AN + V BN )= 1 2 (1/2V PV +1/2V PV ) = 1 2 V PV. (19) It is clear from (16) (19) that the total CM voltage for the proposed topology during the whole operation period is kept constant at V PV /2. Therefore, the ground leakage current is reduced significantly. B. Power Devices Loss Calculation and Comparison In this section, the device power losses for the H5, HERIC, H6, oh5, and proposed topologies are calculated for 5-kW rated power with the same circuit parameters given in Table III. It is necessary to take into account that the calculation of the losses is based on theory and its accuracy depends on the device datasheet accuracy. In Table I, the device type and their voltage stress, and distribution of the device number for different types of losses are given. It can be seen that the devices for switching loss for all the topologies are same but the other losses are different. The lowest conduction loss would be observed for HERIC topology as grid current flows only two switches, while the proposed topology takes place second position. However, it is noticeable that the zero-vector conduction loss of MOSFET + SiC diode freewheeling path for the proposed topology is less than the IGBT + body-diode freewheeling path of the HERIC, H5, H6, and oh5 topologies. In order to calculate the power device losses, the IG- BTs are evaluated by STGW20NC60VD from STMICRO- ELECTRONICS with very soft ultrafast recovery antiparallel diode. MOSFETs and diodes have been selected from Infineon with the model no SPW47N60C3 (70-mΩ on-resistance) and IDH08SG60C with no reverse recovery, respectively. The total power device losses at different output power for the H5, HERIC, H6, oh5, and proposed topologies are calculated under the same condition by extracting the parameters from the datasheet of the selected devices, which are given in Table II and shown as a histogram in Fig. 13. The calculation process and the theories are studied in details in the literature [9], [12], [14], but not the contribution of this paper. Since all of the topologies have been implemented with the unipolar SPWM technique with three-level output voltage as +V PV, 0, and V PV, and also identical filter inductor and capacitor values have been used; therefore, the losses across the output filter will be same for all the topologies which is neglected in this loss comparison. It can be seen that HERIC topology is with the least device loss, and the H5 and H6 topologies have the highest device loss as expected, while the proposed topology are in the second position

8 6312 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016 Fig. 17. Enlarged view of drain-source voltage waveform of the switches S 1, S 4,andS 6. Fig. 15. Experimental gate signals of the switches S 1,S 4,S 6,andS 7. (a) Grid cycle. (b) PWM cycle. Fig. 18. Current stress on the switches S 1,S 4,andS 6. and freewheeling losses if compared with the H5, H6, and oh5 topologies. Fig. 16. Drain-source voltage waveform of the switches S 1,S 4,andS 6. at 5-kW output power which validate the theoretical analysis. Compared with the HERIC, the proposed topology increases the conduction losses and reduces the freewheeling losses as shown in Fig. 13. As a result, the total device loss for the HERIC topology at low power is higher than the proposed topology. On the other hand, the proposed topology cuts the conduction IV. EXPERIMENTAL RESULTS In order to verify the performance of the proposed topology and to compare with other topologies, a universal prototype is built and tested. The photograph of the laboratory prototype is given in Fig. 14 and the specifications are listed in Table III. The capacitance between the PV module and the ground is emulated using a thin-film capacitor of 75 nf. The experimental gate signals of the proposed inverter are shown in Fig. 15. It is clear that the gate signals are in agreement with the theoretical analysis made in Section II and the gate drive voltages are kept constant at the desired level. It also can be observed from Fig. 15(b) that the gate signals G 1 and G 4 are well synchronized, while G 7 is the contrary gate pulse of G 1 and G 4 with a small dead band. Fig. 16 shows the drain-source voltage waveforms of the switches S 1,S 4, and S 6. This shows that the switching voltages of the switches are half of the dc input voltage without any overstress. The partial expansion of Fig. 16 is provided in Fig. 17, showing that the switches S 1 and S 4 almost share the dc-link voltage when they commutate with

9 ISLAM AND MEKHILEF: EFFICIENT TRANSFORMERLESS MOSFET INVERTER FOR A GRID-TIED 6313 Fig. 19. Current stress on the switches S 2,S 3,andS 5. Fig. 22. topology. Experimental waveforms of V AN,V BN,V CM,andi CM for the H5 Fig. 20. topology. Experimental waveforms of V AN,V BN,V CM and i CM for the H6 Fig. 23. Experimental waveforms of V AN,V BN,V CM,andi CM for the HERIC topology. Fig. 21. Experimental waveforms of V AN,V BN,V CM,andi CM for the oh5 topology. high frequency. Therefore, the switching losses are minimized, and the results fulfill the theoretical analysis. The current stress on all the switches is shown in Figs. 18 and 19. It is clear that the current stress of all the switches is smooth and the peak is same as grid peak current I m. The experimental waveform of CM voltage and leakage current for the H6, oh5, H5, HERIC, and proposed topologies are shown in Figs The voltage V AN, CM voltage 2V CM = V AN + V BN, voltage V BN, and leakage current i CM are shown from top to bottom in Figs , respectively. It can be seen that the CM voltage fluctuation for the H5 and HERIC topologies are more if compare with the other three topologies due to the lack of clamping branch which satisfies the theoretical analysis. The lowest fluctuation of CM voltage could be observed with the H6 topology due to the bidirectional clamping branch and also the clamping performance which depends on the turn-on speed of the clamping diode only, while oh5 topology has been placed in the second position. The CM characteristic of the proposed topology is seen to be worse than the H6 and oh5 topologies due to the unidirectional clamping branch as shown in Fig. 24. The expansion waveform of CM voltage and leakage current for the proposed topology is shown in Fig. 25. A small fluctuation in the CM voltage waveform could be observed which corresponds to the lack of bidirectional clamping branch and also the dead band of the clamping switch. However, the measured value of leakage current for the proposed topology is effectively limited within the peak value of 50 ma and RMS value of 20 ma. This can well satisfy the recently published grid codes and standards. In the case of H6 and

10 6314 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016 Fig. 24. Experimental waveforms of V AN,V BN,V CM,andi CM for the proposed topology. Fig. 26. Experimental waveform of grid current i g, grid voltage V g,and differential voltage V AB. Fig. 25. Expansion waveforms of V AN,V BN,V CM,andi CM for the proposed topology. oh5 topologies, the RMS value of leakage current is measured 15.5 and 18 ma, respectively. On the other hand, the RMS value of leakage current for the H5 and HERIC topologies reaches 45 and 48.8 ma, respectively. Therefore, it is clear that the leakage current flowing through the H5 and HERIC topologies is almost double compared to the proposed topology. In practical, additional CM filter is employed to the HERIC and H5 topologies to further suppress the leakage current. The experimental waveform of the grid current i g and grid voltage v g are shown in Fig. 26 in case of full-load condition. It can be seen that v g and i g are in the same phase. The current harmonic distribution is depicted in Fig. 27, which shows that the total harmonic distribution is 1.7%. Therefore, it is clear that the proposed inverter can deliver PV power into the utility grid with low-harmonic distortion and unity power factor that can meet the requirement of IEEE Std As seen in Fig. 26, the inverter output voltage V AB has three levels, +V PV, 0, and V PV. This designates that the proposed topology is modulated with unipolar SPWM and the DM characteristics is excellent. The efficiency of the H5, HERIC, oh5, H6, and proposed topologies are measured for power up to 2 kw and compared to Fig. 27. Fig. 28. Current harmonic distributions. Measured efficiency comparison curve as a function of output power. verify the analysis made in Section III-B as illustrated in Fig. 28. The YOKOGAWA WT1800 precision power analyzer is used to measure the efficiency of the proposed inverter. Note that the presented efficiency diagram covers the total power device losses and the filter inductor losses but it does not contain the losses for the control circuit. It is obvious that the efficiency of

11 ISLAM AND MEKHILEF: EFFICIENT TRANSFORMERLESS MOSFET INVERTER FOR A GRID-TIED 6315 TABLE IV PERFORMANCE COMPARISON AMONG H5,HERIC,H6,OH5, AND PROPOSED TOPOLOGIES Topologies H5 HERIC H6 oh5 Proposed Leakage current (RMS) 45 ma 48.8 ma 15.5 ma 18 ma 20 ma European efficiency (%) the proposed topology at low power (<1200 W) is highest. This is due to low-freewheeling loss compared to the other topologies as described in Section III-B. However, at 2 kw, the efficiency of the HERIC topology is higher than the proposed topology which is due to the increased conduction loss. The maximum efficiency of the proposed topology is measured at 600 W and found to be 98.5%. It is clear that the lowest efficiency is measured with the H6 topology. On the other hand, H5 and oh5 topologies ensure almost same efficiency which is lower than HERIC and proposed topologies but exceeding H6 topology. The European efficiency is calculated by combining several weighted factors at various output power as expressed in (20) [16] η EU = 0.03η 5% +0.06η 10% +0.13η 20% +0.10η 30% +0.48η 50% +0.2η 100%. (20) The European efficiency for the H5, HERIC, H6, oh5, and proposed topologies is calculated 97.59%, 98.16%, 97.24%, 97.55%, and 98.32%, respectively. It can be seen that the European efficiency of the proposed topology for 2-kW prototype exceeds the HERIC topology. Furthermore, the maximum conversion efficiency of the proposed topology (98.5%) is slightly higher than European efficiency (98.32%), indicating an optimal inverter topology. Finally, the performance comparison among these five topologies is summarized in Table IV. It can be seen that H6 topology has the best CM characteristics but low efficiency, while HERIC topology shows better efficiency with high leakage current. It is clear that only the proposed topology presents high efficiency with low leakage current. Therefore, the proposed topology can combine the superior performance of CM characteristics and efficiency. V. CONCLUSION In this paper, a family of new efficient transformerless inverter for a grid-tied PV power generation system is presented using superjunction MOSFETs as main power switches. The main advantages of the proposed topology are as follows: 1) High efficiency over a wide load range is achieved by using MOS- FETs and SiC diodes, 2) CM voltage remains constant during all operation modes due to the added clamping branch, results low leakage current, 3) like as isolated FB inverter, excellent DM characteristics are achieved with unipolar SPWM, and 4) PWM dead time is not required for main power switches, results low distortion at output. Finally, the proposed topology has been validated by a prototype rated 240/50 Hz 1 kw. The experimental results show 98.5% maximum efficiency and 98.32% European efficiency. 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12 6316 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 9, SEPTEMBER 2016 [23] M. Islam and S. Mekhilef, An improved transformerless grid connected photovoltaic inverter with reduced leakage current, Energy Convers. Manage., vol. 88, pp , [24] X. Huafeng and X. Shaojun, Leakage current analytical model and application in single-phase transformerless photovoltaic grid-connected inverter, IEEE Trans. Electromagn. Compat., vol. 52, no. 4, pp , Nov [25] S. V. Araujo, P. Zacharias, and R. Mallwitz, Highly efficient single-phase transformerless inverters for grid-connected photovoltaic systems, IEEE Trans. Ind. Electron., vol. 57, no. 9, pp , Sep [26] D. Schmidt, D. Siedle, and J. Ketterer, Inverter for transforming a DC voltage into an AC current or an AC voltage, EP Patent , Dec. 10, [27] M. Victor, F. Greizer, S. Bremicker, and U. Hübler, Method ofconverting a direct current voltage from a source of direct current voltage, more specifically from a photovoltaic source of direct current voltage, into a alternating current voltage, U.S. Patent , Aug. 12, [28] H. Guofeng, X. Dehong, and C. Min, A novel control strategy of suppressing DC current injection to the grid for single-phase PV inverter, IEEE Trans. Power Electron., vol. 30, no. 3, pp , Mar [29] Z. Tao, H. Guofeng, C. Min, and X. Dehong, A novel control strategy to suppress DC current injection to the grid for three-phase PV inverter, in Proc. Int. Power Electron. Conf., 2014, pp [30] S.-H. Hwang, L. Liu, H. Li, and J.-M. Kim, DC offset error compensation for synchronous reference frame PLL in single-phase grid-connected converters, IEEE Trans. Power Electron., vol. 27, no. 8, pp , Aug [31] M. Monfared and S. Golestan, Control strategies for single-phase grid integration of small-scale renewable energy sources: A review, Renew. Sustainable Energy Rev., vol. 16, pp , [32] W. Yong and L. Rui, Novel high-efficiency three-level stacked-neutralpoint-clamped grid-tied inverter, IEEE Trans. Ind. Electron., vol. 60, no. 9, pp , Sep [33] E. Gubía, P. Sanchis, A. Ursúa,J.López, and L. Marroyo, Ground currents in single-phase transformerless photovoltaic systems, Prog. Photovoltaics, Res. Appl., vol. 15, pp , Monirul Islam received the B.Sc. degree in electrical and electronic engineering degree from the Rajshahi University of Engineering and Technology, Rajshahi, Bangladesh, in 2009, and the M.Eng.Sc. degree in electrical engineering degree from the University of Malaya, Kuala Lumpur, Malaysia, in He is currently a full-time Research Assistant at the Power Electronics and Renewable Energy Research Laboratory, University of Malaya. His research interest includes power converter topologies and control for grid-tied photovoltaic application. Saad Mekhilef (M 01 SM 12) received the B.Eng. degree in electrical engineering from the University of Setif, Setif, Algeria, in 1995, and the M.Eng.Sc. and Ph.D. degrees from the University of Malaya, Kuala Lumpur, Malaysia, in 1998 and 2003, respectively. He is currently a Professor at the Department of Electrical Engineering, University of Malaya. He is the Author and Coauthor of more than 200 publications in international journals and proceedings. He is actively involved in industrial consultancy for major corporations in the power electronics projects. His research interests include power conversion techniques, control of power converters, renewable energy, and energy efficiency.