TIAJEIA STANDARD. Electrical Characteristics for an Interface at Data Signaling Rates TIAIEIA-612. up to 52 Mbit/s

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1 EIA TIA-bL2 93 = Lô7 972 = ANSI/ TIA/ EIA APPROVED: November 2, 1993 TIAJEIA STANDARD Electrical Characteristics for an Interface at Data Signaling Rates up to 52 Mbit/s TIAIEIA-612 DECEMBER 1993 TELECOMMUNICATIONS INDUSTRY ASSOCIATION

2 EIA TIA-b12 93 W NOTICE WEIA Engineering Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Publications shau not in any respect preclude any member or nonmember of TIAíEIA from manufacturing or seliing products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than WEIA members, whether the standard is to be used either domestically or internationally. Recommended Standards and Publications are adopted by TINEIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, W EIA does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the Recommended Standard or Publication. This Standard does not purport to address all safety problems associated with its use or ail applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and health practices and to determine the applicability of regulatory limitations before its use. Published by %LECOMMUNICATIONS INDUSTRY ASSOCIATION 1993 Standards and Technology Department 2001 Pennsylvania Ave. N. W., Washington, D.C PRICE: Please refer to current Catalog of EL4 & JEDEC STANDARDS & ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada ( ) International ( ) All rights reserved Printed in U.S.A.

3 EIA TIA-bL2 93 = b7 ELECTRICAL CHARACTERISTICS FOR AN INTERFACE AT DATA SIGNALING RATES UP TO 52 Mbiüs (From Standards Proposai Nos and formulated under the cognizance of TIA TR30.2 Subcommittee on Data Transmission Interfaces) Contents Page O SCOPE... 1 APPLICABILITY... 2 ELECTRICAL CHARACTERISTICS... 3 Generator Characteristics... 3 Open Circuit Measurement... 4 Test Termination Measurements... 5 Short Circuit Measurement... 5 Output Signal Waveform... 6 Load Characteristics... 7 Input Current-Voltage Measurements... 7 Input Sensitivity Measurements... 7 Cable Termination... 9 Failsafe Operation... 9 Interconnecting Cable Electrical Characteristics ENVIRONMENTAL CONSTRAINTS CIRCUIT PROTECTION Annex A (informative) A. 1 Interconnecting Cable A.l.l Length A.1.2 Cable Physical Characteristics A.1.3 Cable Termination A.2 A.2.1 A.2.2 ECL Generators and Receivers ECL - Emitter Coupled Logic Technology Failsafe Biasing of Receivers a Annex B (informative) References i

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5 EIA TIA-h32 93 m 3234h T = FOREWORD (This foreword is not part of this Standard) This Standard was formulated under the cognizance of TIA Subcommittee TR-30.2 on Data Transmission Interfaces. It is intended to be used with ANSIKIAEIA , High Speed Serial Interface for Data Terminal Equipment and Data Circuit- Terminating Equipment. This Standard specifies generators and receivers capable of operating at data signaling rates up to 52 Mbitís. This Standard was developed in response to a demand from the data communications community for a high speed general purpose DTE-DCE interface. Annex A of this Standard is informative and provides guidelines for application. Annex B of this Standard is also informative and provides references to this Standard. Neither Annex is considered part of this Standard. I iii

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7 EIA TIA-b32 93 m O02 m ANSI/TIA/EIA SCOPE This Standard sdecifies the electrical characteristics of the balanced diaital interface circuit,' normally implemented in integrated circuit technology,?hat may be employed when specified for the interchange of serial binary signals between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) or in any point-to-point interconnection of serial binary signals between data equipments. The interface circuit includes a generator connected by a balanced interconnecting cable to a load consisting of a receiver and a termination. The electrical characteristics of the circuit are specified in terms of required voltage, and current values obtained from direct measurements of the generator and receiver components at the interface points. The logic function of the generator and the receiver is not defined by this Standard, as it is ap pl cat io n -dependent. Minimum electrical requirements for the interconnecting cable are f u rnis h ed. It is intended that this Standard will be referenced by ANSI/TIA/EIA , High Speed Serial Interface for Data Terminal Equipment and Data Circuit- Terminating Equipment, that specifies the other necessary components of an interface (e.g., connector, pin assignments, function) for applications where the electrical characteristics of a high speed balanced digital circuit are required. 1

8 EIA TIA-bL T49 D ANSI/TIA/EIA APPLICABILITY The provisions of this Standard may be applied to the circuits employed at the interface between equipments where information being conveyed is in the form of binary signals. Typical points of applicability for this Standard are depicted in figure 1. D T E Id D C E L Legend: DTE = Data Terminal Equipment DCE = Data Circuit-Terminating Equipmc E = Interface = Interface Receiver - = Balanced Interface Circuit Figure 1 - Applications of balanced digital interface circuit The balanced digital interface circuit will normally be utilized on data and timing, or control circuits where the data signaling rate is up to a maximum limit of 52 Mbiîís. In this Standard, the term: data signaling rate, expressed in the units bit/s (bits per second), is the significant parameter. It may be different from the equipment's data transfer rate, which employs the same units. Data signaling rate is defined as 1/T where T is the minimum interval between two significant instants. In a binary system for which this Standard is designed, the data signaling rate in bitk and the modulation rate in bauds are numerically equal when the unit interval used in each determination is the minimum interval. star (*) represents the opposite input condition for a parameter. For example, the symbol Q represents the receiver output state for one input condition, while Q' represents the output state for the opposite input state. 2

9 EIA TIA-bL b 985 = ANSITTINEIA ELECTRICAL CHARACTERISTICS The balanced digital interface circuit is shown in figure 2. The circuit consists of three parts: the generator (G), the balanced interconnecting cable, and the load. The load is composed of a receiver (R) and a cable termination/faiisafe network. The electrical Characteristics of the generator and receiver are specified in terms of direct electrical measurements while the interconnecting cable is described in terms of its electrical characteristics. + GENERATOR )+BALANCED INTERFACL LOAD b CABLE Cable Vee B 755- Q B' 1 Rt = 110 R Rrp = 1.5 k(l I I Legend: G = Generator Rgp = Generator Pull Down Resistor R = Receiver Rt = Termination Resistor A,B = Generator Interface Points A,B' = Receiver Interface Points C = Generator Circuit Common C' = Receiver Circuit Common Rrp = Receiver Bias Resistor (Optional, Receiver Dependent) Vcpd = Common Potential Difference Vee = Negative Voltage Power Supply NOTE: All resistors f 2% Figure 2 - Balanced digital interface circuit 3.1 Generator Characteristics The generator 'electrical characteristics are specified in accordance with the measurements illustrated in figures 3 to 6 and described in through The generator circuit meeting these requirements results in a low impedance 3

10 EIA TIA-bL2 93 m 3234b BLL ANSITTINEIA balanced source that will produce a differential voltage applied to the interconnecting cable in the range of 590 mv to 1500 mv. The signaling sense of the voltages appearing across the interconnecting cable are defined as follows: a. The A terminal of the generator shall be negative with respect to the B terminal for a binary O (SPACE or OFF) state. b. The A terminal of the generator shall be positive with respect to the B terminal for a binary 1 (MARK or ON) state. NOTE -, The sense of data binary O (SPACE) and data binary 1 (MARK) are inverted from that specified in ElMIA-422-A. The logic function of the generator and the receiver is beyond the scope of this Standard, and therefore is not defined Open Circuit Measurement (Figure 3) For either binary state, the magnitude of the differential voltage (VOC or VOC') measured between the two generator output terminals shall not exceed 1.5 V. Vee OPEN CIRCUIT MEASUREMENT T- I VOC I 51.5 v, I VOC' I V 0 = Measured Parameter I Vee Figure 3 - Open circuit measurement 4

11 ANSITTINEIA Test Termination Measurements (Figure 4) With a test load of the resistors shown in figure 4, the magnitude of the differential output voltage (Vt), shall be 590 mv or greater. For the opposite binary state, the polarity of Vt shall be reversed (Vt*). The magnitude of the difference between Vt and Vt' shall be less than 100 mv. The magnitude of the generator offset voltage (Vos), measured between the center point of the test load and the generator circuit common shall be -1.6 V or more positive for either binary state. The magnitude of the difference of Vos for one binary state and Vos' for the opposite binary state shall be 1 O0 mv or less. Vee TEST TERMINATION MEASUREMENTS I Vt I mv, I Vt' I mv I I Vt I - I Vt' I I I 100 mv O V 2 VOS V, O V 2 VOS' I Vos - Vos' I I 100 mv I Vee = Measured Parameter Figure 4 - Test termination measurements Short-Circuit Measurement (Figure 5) With the generator output terminals short-circuited to each other, the magnitude of the current (los) following between each output terminal shall not exceed 50 ma in magnitude, for either binary state. SHORT CIRCUIT MEASUREMENT I los I s 50 ma, I los' I I50 ma = Measured Parameter Vee Figure 5 - Short-circuit measurement 5

12 EIA TIA-bL2 73 ANSI/TIA/EIA b Output Signal Waveform (Figure 6) During transitions of the generator output between alternating binary states (one-zero-one-zero, etc.), the differential voltage measured across the 1 1 O Q test load connected between the generator output terminals shall be such that the voltage monotonically changes between 0.2 and 0.8 of Vss within 0.5 ns to 2.3 ns. Thereafter, the signal voltage shall not vary more than 10% of Vss from the steady state value, until the next binary transition occurs, and at no time shall the instantaneous magnitude of Vt or Vt* exceed 1500 mv nor be less than 590 mv. Vss is defined as the voltage difference between the two steady state values of the generator output. Legend: t b = Time duration of the unit interval at the applicable data signaling rate. 0.5 ns 5 tr or tf 22.3 ns Vss = Difference in the steady state voltages vss = 1 Vt - Vt* I Vee Vee Figure 6 - Output signal waveform 6

13 EIA TIA-bL2 93 W b ANSITTINEIA Load Characterfstics The load is composed of a receivers (R) and a termination/failsafe network as shown in figure 2. The electrical characteristics of a receiver without termination or failsafe provision are specified in terms of measurements illustrated in figures 7 to 9 and described in and A circuit meeting these requirements results in a differential receiver having a high input impedance, and a small input threshold between f 150 mv Input Current-Voltage Measurements (Figure 7) With the voltage Via (or Vib) ranging from -0.5 V to -2.0 V while Vib (or Via) is held at V, the resultant input current lia (or lib) shall be no greater than 350 PA. These measurements apply with the receiver's power supply(s) in both power-on and power-off conditions (as defined by the Integrated Circuit manufacturer). Note that these measurements are made with any termination resistor or failsafe provision disconnected. Figure 7 - Receiver input current-voltage measurements Input Sensitivity Measurements (Figure 8) Over an entire input voltage range of -0.5 V to -2.0 V (referenced to receiver circuit common), the receiver shall not require a differential input voltage of more than 150 mv to correctly assume the intended binary state. Reversing the polarity of Vi shall cause the receiver to assume the opposite binary state. The receiver is required to maintain correct operation for differential input voltages ranging between 150 mv and 1.5 V in magnitude. Note that these measurements are made with any termination resistor or failsafe provision disconnected. Figure 9 illustrates the minimum and maximum operating voltages of the receiver. Note that the logic function of the receiver is not defined by this Standard. 7

14 EIA TIA ANSITTINEIA Vcm = V to Y... h. 5 V Vi (V) measured from B' to A' Figure 8 - Input sensitivity measurements I A' B' C' d = Measured Parameter to = Applied Voltage Note: Vcrn = (Via + Vib)M, Vid = IVia - Vibl Via V V Applied Voltages I Vib Resulting Resulting Input Common I Voltage Mode Voltage Vid Vcrn V +150 mv V V -150 mv V I V V V V V V V V V V V +150 mv V V -150 mv V Figure 9 - Receiver input sensitivity table 8

15 EIA TIA m TO9 m ANSI/TIA/EIA Cable Termination For all applications, the use of a cable termination is required. The recommended value is 110 R f 2%. The termination resistor is connected across the cable at the load end of the cable, as close to the receiver input pins as possible Failsafe Operation Other standards and specifications using this electrical characteristics of the balanced digital interface circuit may require that specific interchange circuits be made failsafe to certain fault conditions. Such fault conditions.may include one or more of the following: 1 ) open-circuited interconnecting cable 2) generator in power-off condition When detection of one or more of the above fault conditions is required by specific applications, additional provisions are required in the load and the following items must be determined and specified. 1) which interchange circuits require fault detection 2) what faults must be detected 3) what action must be taken when a fault is detected The method of detection of fault conditions is application-dependent and is therefore not further specified. (see Annex A.2.2) 9

16 ~ EIA TIA-bL2 93 m m ANSITTINEIA Interconnecting Cable Electrical Characteristics The cable shall consist of 25 twisted pairs of conductors of 28 AWG. The cable has an overall foil/braid shield which serves the purpose of a signal shield. The two wires of each pair shall be connected to the same signal, one to the NA' and the other to the B/B' signal pins. Maximum DC Resistance (DCR) at 20 OC Differential Impedance at 50 MHz Maximum Signal Attenuation at 50 MHz Mutual Capacitance within pair at 1 khz Propagation Delay maximum: skew (pair to pair) 3.5 n 110 alt 11R 4.5 db pf/m (14.5 i 2.0 pf/ft) 79 ns 2.0 ns See Annex A.l for further guidance on the interconnecting cable. 4 ENVIRONMENTAL CONSTRAINTS A balanced digital interface circuit conforming to this Standard will perform satisfactorily at data signaling rates up to 52 MbiVs providing that the following operational constraints are simultaneously satisfied: a. The interconnecting cable meets the recommended cable characteristics and the cable is appropriately terminated. b. The input voltage at the receiver is between -0.5 V and -2.0 V with respect to receiver circuit common. 10

17 EIA TIA-bL2 93 = 3234b ôôl W ANSI/TIA/EIA CIRCUIT PROTECTION Balanced digital interface generator and receiver devices, under either the power-on or power-off condition, complying to this Standard shall not be damaged under the following conditions: a. Generator open circuit. b. Short-circuit across the balanced interconnecting cable. c. Short-circuit to circuit common. 11

18 EIA TIA m ANSI/TIA/EIA A ANNEX A (Informative) a GUIDELINES FOR APPLICATION A.l Interconnecting Cable The following section provides further information to Section 3.3 and is additional guidance concerning operational constraints imposed by the cable parameters of length and termination. A.1.1 Length The nominal length of cable separating the generator and the load is 15 meters (50 ft). A.1.2 Cable Physical Characteristics The following physical characteristics apply to the cable: Conductor Insulation Foil Shield Braid Shield 28 AWG, 7 strands of 36 AWG, tinned annealed copper, nominal diameter 0.38 mm ( in.) polyethylene or polypropylene; 0.24 mm ( in.) nominal wall thickness; 0.86 mm +_ mm ( in +_ in.) outside diameter mm (0.002 in.) nominal aluminum/polyester laminated tape spiral wrapped around the cable core braided 36 AWG, tinned plated copper in accordance with 80% minimum coverage, in electrical contact with the aluminum of the foil shield Outside Diameter I 10.6 mm (I in.) A.1.3 Cable Termination The characteristic impedance of twisted pair cable is a function of frequency, wire size and type as well as the kind of insulating materials employed. For example, the characteristic impedance of average 28 AWG, copper conductor, plastic insulated twisted pair cable, to a 50 MHz sine wave will be on the order of 110 a. 12

19 EIA TIA-bL2 93 = b b54 = ANSI/TIA/EIA A.2 ECL Generators and Receivers A.2.1 ECL - Emitter Coupled Logic Technology Emitter Coupled Logic (ECL) families such as lok, 10H, and 100K have been developed that meet the requirements of this Standard by a number of Integrated Circuit manufacturers. The 1 OOK family is compensated for both Power Supply Voltage and Operating Temperature variations, offering constant thresholds and output levels over both ranges. Some other families are only Power-Supply-Voltage-compensated. The 1 OOK family also accepts a wide range of power supply voltages (Vee) from -4.2 V to -5.7 V. A.2.2 Failsafe Biasing of Receivers (Figure A.l) In the event that the interface cable is not present, the receiver must default to a known state. The method of failsafe biasing is application and component specific, and therefore is beyond the scope of this Standard. External resistors can be used to bias the receiver's input into a known state (2150 mv differential) for the case of the disconnected cable. For example, a 1.5 kn pull up and pull down resistor will bias the receiver to 177 mv,defaulting the receiver to a OFF state. A' Vee I 1.5 k@.l o B' Figure A.1 - Receiver failsafe biasing It should be noted that it is not necessary to use external resistors on ail families of receivers. Some receiver integrated circuits have this feature incorporated internal to the integrated circuit. 13

20 EIA TIA D ANSITTINEIA ANNEX B (informative) e REFERENCES ANSIíTIA/EIA , High Speed Serial Intedace for Data Terminai Equipment and Data Circuit- Terminating Equipment E IA-422-A, Electrical Characteristics of Balanced Voltage Digital Interface Circuits 14