CXA1315M/P. 8-bit D/A Converter Supporting with I 2 C Bus

Transcription

1 8-bit D/A Converter Supporting with I 2 C Bus Description The is developed as a 5-channel 8- bit D/A converter supporting with I 2 C bus. CXAM pin SOP (Plastic) CXAP pin DIP (Plastic) Features Serial control through I 2 C bus 5-channel 8-bit D/A converter Built-in general-purpose I/O ports (Digital I/O) I/O can be specified to respective ports independently Selection of 8 slave addresses possible through address select pins ( pins) Applications The IC, which cannot support I 2 C bus, can support it by connecting its control pin to the. Structure Bipolar silicon monolithic lc Absolute Maximum Ratings (Ta = 25 C) Supply voltage Operating temperature Topr 2 to +75 C Storage temperature Tstg 65 to + C Allowable power dissipation PD 6 mw Operating Conditions Supply voltage 8.2 to.8 Operating temperature Topr 2 to +75 C Purchase of Sony's I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specifications as defind by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. E88Z5D78-PS

2 SW SW DAC DAC DAC2 DAC DAC GND SAD2 SAD SAD SW SW2 Pin Configuration (Top iew) I 2 C bus Slave address select pin SW I/O SW I/O DAC output Block Diagram SAD2 SAD SAD SW to Open collector Level Conversion Level Conversion Level Conversion I 2 C Decoder Power On Reset DAC DAC DAC DAC DAC REG AMP AMP AMP AMP AMP GND DAC DAC DAC2 DAC DAC 2

3 Pin Description No. Symbol Equivalent circuit Description 2 SW SW SW2 SW I/O pin for genera-purpose I/O port ILmax:.5 IHmin: OLmax:..5k I/O pin for I 2 C bus DAC DAC DAC2 DAC DAC 56 2k 2k 22k D/A converter output pin 8 GND GND pin SAD SAD SAD2 Slave address input pin Input at positive logic ILmax:.5 IHmin:.5k input pin for I 2 C bus Power supply pin Electrical Characteristics (Ta = 25 C, = ) Test No. Item Symbol Test conditions Min. Typ. Max. Unit circuit Circuit current lcc DAC to = 7 8 ma D/A Converter Block 2 Differential linearity DLE (DAC to = n + ) (DAC to = N) 8 (DAC to = ) (DAC to = 6) n = to 7 +. LSB Minimum output voltage min DAC to =...62 Maximum output voltage max DAC to = Output current Iout 2 Current that can be flowed from Pins to 7 + ma 6 Output impedance Zo 2 DAC to = 7, ( ma) (ma) 2mA 6 Ω 7 Repple rejection Grip DAC to = 7, REF = Superimose Hz to, p-p 6 db

4 SW, SAD Pins No. Item Symbol Test circuit Test conditions Min. 8 8 Low level input voitage High level input voltage Low level input current High level input current IL IH IIL IIH Input voltage where ST to ST become "" Input voltage where ST to ST become "" lnput current when. is applied lnput current when.5 is applied. Low level input voltage OL 5 SW to =, Output voltage when ma flows in Typ. Max. Unit µa µa I 2 C Bus Block Items (, ) No. Item Symbol Min. Typ. Max. Unit High level input voltage Low level input voltage High level input current Low level input current Low level output voltage, at ma flow to (Pin ) Maximum flowing current lnput capacitance Maximum clock frequency Data change minimum waiting time Data transfer start minimum waiting time Low level clock pulse width High level clock pulse width Minimum start preparation waiting time Minimum data hold time Minimum data preparation time Rise time Fall time Minimum stop preparation waiting time IH IL IIH IIL OL IOL CI f tbuf thd; STA tlow thigh tsu; STA thd; DAT tsu; DAT tr tf tsu; STO µa µa ma pf khz ns ns I 2 C bus load conditions: Pull-up resistance kω (Connected to +5) Load capacitance 2pF (Connected to GND) I 2 C Bus Control Signal tbuf tr tf thd; STA tlow thd; DAT thigh tsu; DAT tsu; STA tsu; STO P S thd; STA Sr P

5 Electrical Characteristics Measurement Circuit Measurement Circuit Measurement Circuit µ µ µ µ p p p p p p p p p p ±ma Measurement Circuit Measurement Circuit Hz, p-p +.22µ +.22µ µ µ p p p p p =.5 (No.8) 2. (No.). (No.).5 (No.) Measurement Circuit µ ma µ

6 Definition of I 2 C Bus Register <SIave address> MSB LSB SAD2 SAD SAD R/W R/W : SLAE RECEIER : SLAE TRANSMITTER SAD to 2: to pin : "Low" : "High" <Register table> With the lc reset all registers are reset to "" : Not defined x: Don't care Sub address is auto incremented lt can be used as a 6-bit D/A converter by setting the lower two bits of DAC to registers to "", but take care that the max. voltage of DA output will lower about m compared with the use of 8 bits. Control Register Sub address Bit 7 Bit 6 Bit 5 Bit Bit Bit 2 Bit Bit x x x x x REF SW SW2 SW SW x x x x x DAC (8) x x x x x DAC (8) x x x x x DAC2 (8) x x x x x DAC (8) x x x x x DAC (8) Status Register Bit 7 Bit 6 Bit 5 Bit Bit Bit 2 Bit Bit PONRES ST ST2 ST ST 6

7 <Registers> In brackets ( ) number of bits REF () : Switches D/A converter reference voltage : Standardizes the inner regulator : Standardizes voltage resistance divided from cc SW to () : Selects ON/OFF of Pins, 2, and (Each pin is the open collector output of NPN transistor) : OFF : ON DAC to (8) : Digital data input register of D/A converter : Output voltage turns to minimum 255: Output voitage turns to maximum PONRES () : Detects POWER ON RESET : Master passes from the bus and is reset to "" after having read this status : Sets to "" when power supply is turned on or when there has been a power dip ST to () : Detects and registers the voltage condition of Pins, 2, and :.5 and below :. and above Note) SW to effective during "" I 2 C Bus Signal There are 2 signals in I 2 C bus. (Serial Data) and (Serial Clock). is double-way. As is bidirectional it has state outputs, H, L and. H L L I 2 C transfer begins with Start Condition and ends with Stop Condition. Start Condition S Stop Condition P 7

8 I 2 C data write (Write from I 2 C controller to IC) MSB At "L" during write MSB LSB S Address ACK Sub Address ACK MSB LSB 8 8 DATA (n) ACK DATA (n + ) ACK DATA (n + 2) DATA 8 8 ACK DATA ACK P The number of data that can be transferred at a time is confined to units of 8-bit that can be set as required. Sub Address is incremented automatically. I 2 C data read (Read from IC to I 2 C controller) At "H" during read S Address ACK DATA ACK P Read timing MSB LSB IC output Read timing ACK DATA ACK Data read is performed with rise. 8

9 oltage variation at. 25 C [] oltage variation at. 25 C [] Application Circuit + µ.22µ k k General-purpose output port k k 2SC2785 k D/A converter output General-purpose input port k k 2SC2785 Slave address for Ch and Dh k Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Characteristics Diagram. D/A converter output temperture characteristics (REF: ) =. D/A converter output temperture characteristics (REF: ) = Data: Data: Data: Data: 8 Data: 8 Data: 8 Data: 255 Data: 8 Data: 255 Data: Data: 255 Data: T [ C] T [ C]

10 .5 ± ±. 6. Package Outline Unit: mm CXAM PIN SOP (PLASTIC) ± M PACKAGE STRUCTURE SONY CODE EIAJ CODE JEDEC CODE SOP-P-L SOP-P- PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY.2g

11 . MIN.58 MIN 5.8 MAX ±.7. MIN.5 MIN CXAP PIN DIP (PLASTIC) to ±. Two kinds of package surface:.all mat surface type. 2.All mirror surface type..2 ±. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-P- LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP-P- LEAD MATERIAL COPPER ALLOY JEDEC CODE Similar to MO--AE PACKAGE MASS. g PIN DIP (PLASTIC) mil.5 ± to ± ±.76 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-P- LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP-P--AU LEAD MATERIAL COPPER JEDEC CODE MS--AA PACKAGE WEIGHT.g