Research Article Effects of Annealing Time on the Performance of OTFT on Glass with ZrO 2 as Gate Dielectric

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1 Hindawi Publishing Corporation Active and Passive Electronic Coponents Volue 202, Article ID 90076, 5 pages doi:5/202/90076 Research Article Effects of Annealing Tie on the Perforance of OTFT on Glass with ZrO 2 as Gate Dielectric W. M. Tang,, 2 M. G. Helander, M. T. Greiner, Z. H. Lu,, 3 and W. T. Ng 2 Departent of Materials Science and Engineering, University of Toronto, 84 College Street, Toronto, ON, Canada M5S 3E4 2 Departent of Electrical and Coputer Engineering, University of Toronto, 0 King s College Road, Toronto, ON, Canada M5S 3G4 3 Departent of Physics, Yunnan University, 2 Cuihu Beilu, Yunnan, Kuing 65009, China CorrespondenceshouldbeaddressedtoW.M.Tang,wtang@vrg.utoronto.ca Received 5 July 20; Accepted 6 October 20 Acadeic Editor: Hsiao W. Zan Copyright 202 W. M. Tang et al. This is an open access article distributed under the Creative Coons Attribution License, which perits unrestricted use, distribution, and reproduction in any ediu, provided the original work is properly cited. Copper phthalocyanine-based organic thin-fil transistors (OTFTs with zirconiu oxide (ZrO 2 asgatedielectrichavebeen fabricated on glass substrates. The gate dielectric is annealed in N 2 at different durations (5, 5, 40, and 60 in to investigate the effects of annealing tie on the electrical properties of the OTFTs. Experiental results show that the longer the annealing tie for the OTFT, the better the perforance. Aong the devices studied, OTFTs with gate dielectric annealed at 350 CinN 2 for 60 in exhibit the best device perforance. They have a sall threshold voltage of 8 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 na. These characteristics deonstrate that the fabricated device is suitable for low-voltage and low-power operations. When copared with the TFT saples annealed for 5 in, the ones annealed for 60 in have 20% higher obility and nearly two ties saller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k fil and produces a better insulator/organic interface. This results in lower aount of carrier scattering and larger CuPc grains for carrier transport.. Introduction Owing to light weight, echanical flexibility, and low-cost fabrication, organic thin-fil transistors (OTFTs have a wide range of applications such as sensors, flat-panel displays, and RFID tags [ 3]. The first OTFT based on organic seiconductor polythiophene was reported in 986 [4]. Heavily doped silicon substrates are generally used for the fabrication of OTFT as they are highly conductive and can act as the gate of the devices. In addition, high-quality gate dielectric SiO 2 can be therally grown directly on the Si substrate. However, for the next generation of OTFTs and oxide TFTs fabricated on glass or plastic substrates, a etal gate electrode is necessary. By fabricating OTFTs on flexible plastic substrates, there is a potential in the future for producing roll-up displays that can be integrated into a sall device such as a pen. There are three ajor types of dielectric used in OTFTs: inorganic dielectric, polyeric dielectric, and self-asseble layer. For inorganic dielectric aterials, silicon dioxide is coonly used as the gate insulator in OTFT. However, this kind of OTFT requires a relatively high voltage (about 00 V for operation. In order to reduce the operating voltage and hence the power consuption, high-k aterial is often used as a gate dielectric in OTFTs. Several high-k dielectrics have been eployed to fabricate OTFT, for exaple, HfO 2 [5], Al 2 O 3 [6], TiO 2 [7], Ta 2 O 5 [8], and BaTiO 3 [9]. The perforance of organic transistors depends largely on the quality of the gate insulator, the insulator/organic interface, the orphology of the organic thin fil, and the charge injection process. It is essential to develop a suitable and high-quality gate insulator with appropriate orphology to achieve a sooth insulator/organic interface. The as-deposited high-k fils are usually loosely packed and contain ipurities and defects such as oxygen vacancies, oxygen interstitials, and/or oxygen deficiency [0]. These defects and ipurities will cause transient charge trapping in the high-k dielectric and leakage current []. Various surface passivation ethods have been developed in order to achieve high-quality high-k OTFTs, such as annealing in ultraviolet (UV ozone and nitridation gases, surface

2 2 Active and Passive Electronic Coponents treatent with octadecyltrichlorosilane (OTS, polyethylethacrylate (PMMA, polyvinyl acetate and ion-bea irradiation, and using stack insulator structure. In this study, one of the ost proising high-k dielectric for widespread application, zirconiu oxide (ZrO 2, is used as the gate dielectric. ZrO 2 is a stable etal oxide with a high dielectric constant ( 5 25 [2] and a large band gap (5.8 ev. It has been reported that ZrO 2 has the lowest leakage current [3]. Moreover, it is a proising aterial for the fabrication of large-area flexible displays because the ZrO 2 fils can be transparent and have good adhesion with plastic substrates [4]. The effects of ZrO 2 annealing treatent tie in nitrogen abient on the electrical properties of CuPc-based organic thin fil transistors are investigated. The electrical and physical characteristics of the devices are presented. 2. Experiental Details Corning 2947 glass substrates ( were used in this study as they are echanical stable, low cost, and copatible with large area applications such as plasa televisions. The substrates were cleaned with a standard regient of Alconox, acetone, ethanol, and deionized water followed by UV ozone treatent for 5 in. The substrates were then loaded into a sputtering chaber with a base pressure of Torr. A 50 n thick Al gate was then deposited at roo teperature with a deposition rate of 0.4 Å/sec. A 40 n thick ZrO 2 was then deposited by sputtering fro a zirconiu target (99.95% purity with an RF power of 30 W in a ixed Ar/O 2 abient (Ar to O 2 ratio = 4:.The chaber pressure during deposition was 5.67 Torr. The saples then underwent annealing on a hotplate at 350 C in N 2 for different durations (0 in, 5 in, 5 in, 40 in, and 60 in. A layer of 40 n p-type seiconductor, copper phthalocyanine (CuPc was then deposited by vacuu evaporation through a patterned shadow ask at roo teperature. CuPc is a stable and proising p-type organic seiconductor with the ajor charge carriers as holes. It can be easily obtained in large quantity and high purity and hence particularly attractive for low-cost applications in dye processing, cheical sensors, and optical data storage [5, 6]. The source and drain gold pads, 50 n thick, were then deposited on top of the organic layer by theral evaporation through a stainless steel ask with a channel length L of 36 μ and a channel width W of 96 μ. The cross-section of the OTFT structure is as shown in Figure. The currentvoltage (I-V characteristics were easured by an HP 455A seiconductor paraeter analyzer. All the easureents were taken by a probe station at roo teperature in the abient atosphere. An atoic force icroscopy (Veeco Diension 300 in tapping ode was eployed to analyze the surface orphology, grain size, and rs roughness of the high-k ZrO 2 and CuPc fils. 3. Results and Discussion Figure 2 shows the output characteristics of the OTFTs with ZrO 2 fil annealed for 0 in and 60 in. Typical I d -V d curves were obtained when a negative V g was applied to the Table : Device paraeters of the OTFTs. 0 in 5 in 5 in 40 in 60 in μ ( 0 3 c 2 /Vs SS (V/decade I off (na N ax ( 0 3 c devices. At a gate voltage of 3 V and a drain voltage of 4.5 V, the device with ZrO 2 fil annealed for 0 in has a drain current of 77 na, while the one annealed for 60 in has a larger drain current of 07 na. The operating principle of OTFT is siilar to that of traditional p-type MOSFET. The current flowed between the source and drain electrodes is odulated by the gate voltage V g. The carrier obility of the devices in the saturation regie can be calculated using the following equation: μ = 2L( I /2 2 d / V g, ( WC ox where C ox is the unit capacitance of the insulator and μ is the carrier obility. Figure 3 shows the transfer characteristics of I d versus V g at a fixed V d of 2.5 V for the devices. The subthreshold slope, SS, is a very iportant paraeter for OTFTs as it can be used to evaluate the switching characteristics of the OTFTs. SS is defined as V g / log 0 (I d evaluated at the steepest slope of the plot. Fro SS, the axiu density of the surface states N ax at the organic seiconductor/dielectric interface can be estiated as [ ] SS log(e Co N ax = ( kt/q q, (2 where q is the electronic charge, k the Boltzann constant, and T the teperature in Kelvin. The iportant paraeters of the devices extracted fro the transistor characteristics are suarized in Table.Itis found that the perforances of the OTFTs including obility, subthreshold slope, surface states density, and off-state current I off iprove with annealing duration. This should be due to the fact that the OTFT annealed for longer duration can have a denser ZrO 2 fil and a thicker interfacial layer [7, 8] with lower interface-trap density to suppress the leakage associated with high-k aterials. In addition, longer annealing can reove ore deep traps, oxide charges, and unsaturated bonds in the ZrO 2 dielectric and thus lead to a significant reduction of S, N ax and I off.ithasbeenreported that dielectric roughness can affect the perforance of OTFT [9, 20]. Figure 4 shows the AFM iages of the ZrO 2 fils with different annealing ties. It is found that extending the annealing tie fro 0 in to 60 in can reduce the gate-dielectric surface roughness (by 9% as easured using AFM. This can contribute to the reduction of trap states, interface defects, and surface scattering on charge carriers leading to higher obility and saller subthreshold slope. A soother insulator surface is also ore favorable for the growth of better quality organic fil resulting in larger grains

3 Active and Passive Electronic Coponents 3 Au Au CuPc ZrO 2 Al Glass (corning 2947 Figure : Scheatic diagra of a CuPc transistor. 0 0,, V V 20.5 V 40 2 V 40 2V Id (na V Id (na V 80 V g = 3 V in V g = 3 V 60 in V d (V V d (V (a (b Figure 2: Output characteristic curves of OTFTs with ZrO 2 gate dielectric annealed in N 2 for (a 0 in and (b 60 in. V d = 2.5 V E 8 Id (A E V g (V 0 in 5 in 5 in 40 in 60 in Figure 3: Transfer characteristic curves of OTFTs with ZrO 2 gate dielectric annealed for various durations.

4 4 Active and Passive Electronic Coponents.5.5 x µ/div z 200 n/div (a x µ/div z 200 n/div (b.5 x µ/div z 200 n/div (c Figure 4: AFM iages (scan area of 2 μ 2 μ of ZrO2 surface with different annealing treatent ties: (a 0 in, (b 5 in, and (c 60 in. CuPc fil grown on the surface of ZrO2 ( 9% larger. This reduces the grain boundaries in the conduction channel for higher obility of the device [2, 22]. 4. Conclusions In suary, CuPc-based OTFT on glass substrate with highk ZrO2 as gate insulator has been fabricated and studied. The effects of annealing tie on the electrical properties of the devices are investigated. The study has deonstrated that ZrO2 is a proising gate dielectric aterial for obtaining low operating voltage and low power consuption. Experiental results show that the OTFTs with ZrO2 gate-dielectric annealed for 60 in have 20% higher obility, 50% saller subthreshold slope, 72% lower off-state current and 50% saller axiu density of surface states than the one annealed for 0 in. The possible reasons are that longer annealing tie can enhance the densification of the ZrO2 fil, the dielectric properties of the ZrO2 fil, and the quality of the CuPc/ZrO2 interface, resulting in less carrier scattering and better grain growth. Acknowledgent The authors would like to acknowledge funding for this research fro the Natural Sciences and Engineering Research Council (NSERC of Canada, and Science and Technology Prootion Project of Yunnan Province (Grant nos. 2009CI30 and 2007A007z.

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