13607CP 13 GHz Latched Comparator Data Sheet

Transcription

1 13607CP 13 GHz Latched Comparator Data Sheet Applications Broadband test and measurement equipment High speed line receivers and signal regeneration Oscilloscope and logic analyzer front ends Threshold and/or peak detectors Window comparators High speed triggers Mono-bit receivers Digital Phase and Frequency Detection Features Supports clock rates up to 13 GHz Hysteresis <5 mv Propagation delay (Clk-to-Q): 65 ps typ. Output amplitude 1.2 Vpp differential Low power consumption: 550 mw typ. Supports single-ended and differential operation Fast rise and fall times: 15 ps typ. Single +3.3 V power supply Deterministic Jitter: 2.0 ps p-p typ. Available in plastic QFN package Random Jitter 60 fs RMS typ. Evaluation board available Description The 13607CP is an exceptionally fast latched voltage comparator with very low thermal hysteresis that operates with clock rates from DC to 13 GHz. The part is nominally positive-edge triggered; however, by reversing the positive and negative clock connections, a negative-edge triggered application can be accommodated. All differential analog inputs and differential clock inputs are DC coupled on-chip and terminated with resistors to V CC. The differential data outputs should be terminated off chip with 50 Ω resistors to V CC. The 13607CP operates from a single +3.3 V power supply and is available in a 3 X 3 mm, plastic, QFN package. The packaged part is also available on an evaluation board with SMA connectors. For customers requiring a comparator that operates from a -3.3 V power supply Inphi offers the 13606CP. Block Diagram VCC IN+ IN- In Out 25706CP 13607CP Latch Clk In OUTp OUTn CLKINp CLKINn GND CP_DS_Ver1.0 Inphi Proprietary Page 1 of 11

2 Absolute Maximum Ratings Stresses beyond those listed here may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions and Electrical Specifications of this datasheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Symbol Conditions Min Max Unit Power Supply Voltage V CC 10 sec. stress time V Analog and Clock Input Signals IN+, IN-, CLKIN 10 sec. stress time V CC 4.0 V CC +1.0 V Output Signals DOUT 10 sec. stress time V CC 3.0 V CC +1.0 V Junction Temperature Die T J C Case Temperature Package Paddle T C C Shipping/Storage Temperature T STORE C Humidity RH % V CC, GND > V ESD protection (HBM) 1 Notes: 1 As per JESD22-A114-B. V ESD Outputs > V Clock & analog inputs > V Operating Conditions Important Note: Unused I/O should be terminated with 50 Ω to V CC for all specifications to be met. Parameter Symbol Conditions Min Typ Max Unit Power Supply Voltage V CC ± 5% Tolerance V Power Supply Current I CC ma On-Chip Power Dissipation P D mw Operating Temperature (Junction) Die T J C Operating Temperature (Case) Package T C Bottom of Paddle C Thermal Resistance junction to paddle R JC (θ JC ) Bottom of paddle C/W CP_DS_Ver1.0 Inphi Proprietary Page 2 of 11

3 DC Electrical Specifications! WARNING To prevent damage to the part: DC power must be turned off prior to connecting or disconnecting any cables. Electrical specifications guaranteed when the part is operated within the specified operating conditions Parameter Symbol Conditions Min Typ Max Unit Analog Input Specification Input High Level V IH V CC referenced V CC V CC +0.3 V Input Low Level V IL V CC referenced V CC V CC V Input Amplitude 1 VIN pp Differential peak-to-peak Single ended peak-to-peak Input Offset Voltage 2 V OS --- ±1.5 ±6.0 mv mvpp V OS Temperature Coefficient ΔV OS /ΔT μv/ C DC Input Resistance R IN Input to V CC Ω Hysteresis (DC) Clock Input Specification Measured with DC input and 100 MHz clock mv Input High Level V IH V CC referenced V CC V CC +0.5 V Input Low Level V IL V CC referenced V CC V CC V Input Amplitude 1,3 (Important: See note #3) VCLK pp Differential peak-to-peak Single ended peak-to-peak DC Input Resistance R CLKIN Input to V CC Ω Data Output Specification 4 mvpp Data Output Amplitude D OUT Differential peak-to-peak mvpp Output High Voltage V OH DC coupled, V CC referenced V CC -85 V CC -55 V CC mv Output Common Mode V OCM DC coupled, V CC referenced V CC -425 V CC -360 V CC -300 Output Eye Cross V OEC Single-ended measurement % DC Output Resistance R OUT Output to V CC Ω Notes: 1 Analog and clock input amplitudes <300 mvpp may cause part to fail the following AC electrical specifications: Clock Phase Margin, Deterministic Jitter, Random Jitter, Clock to Data Output Delay. 2 Typical refers to variance or 1-sigma value. Expectation value is 0 mv. 3 For optimum performance in the frequency range of 10.5 GHz to 12.5 GHz, the clock input amplitude should be reduced. Decision accuracy may be degraded and the output data eye may be distorted for clock amplitudes greater than 300 mvpp (single-ended) or 600 mvpp (differential). It is left to the customer to determine the best amplitude for optimum system operation. 4 Outputs are CML and, when direct coupled, must be DC terminated with 50 Ω to V CC. When AC-coupled, no external DC termination is required. Furthermore, the output high and common mode levels are not applicable. mv CP_DS_Ver1.0 Inphi Proprietary Page 3 of 11

4 AC Electrical Specifications! WARNING To prevent damage to the part: DC power must be turned off prior to connecting or disconnecting any cables. Electrical specifications guaranteed when the part is operated within the specified operating conditions Analog Input Specification Parameter Symbol Conditions Min Typ Max Unit Input Analog Bandwidth BW IN 400 mvpp single-ended sine wave GHz Input Return Loss 1 RL IN 0 to 13 GHz db Thermal Hysteresis 2 Clock Input Specification V THYS Soak time = 0.01 μs Soak time = 1 μs Soak time = 100 μs Maximum Clock Frequency f MAX GHz Minimum Clock Slew Rate 3 S MIN At CLKIN zero crossing V/ns Clock Input Return Loss 4 RL CLK 0 to 13 GHz db Clock Phase Margin CPM at 12.5 GHz deg Data Output Specification Output Rise/Fall Time t r /t f 20 80% ps Output Return Loss 5 RL OUT 0 to 11 GHz db 11 to 13 GHz db Added Deterministic Jitter 6,7 J D Peak-to-peak ps Random Jitter 6,7 J R RMS at 10 GHz fs Clock to Data Output Delay 6 t Q QFN Package ps Notes: 1 The Analog inputs are designed to be a broadband impedance match to 50 Ω and are DC terminated, on chip, with a 63 Ω resistor to V CC. Refer to the 13607CP application note and the HSL IO AN application note for various I/O interconnection and termination methods. 2 See Hysteresis Specification section. 3 Minimum Clock Slew Rate specification ensures sufficiently fast clock edge rates on sine wave clock signals to maintain given specifications. This device will operate with lower slew rates, though some performance specifications may be degraded. 4 The Clock inputs are designed to be a broadband impedance match to 50 Ω and are DC terminated with a 70 Ω resistor to V CC. Refer to the 13607CP application note and the HSL IO AN application note for various I/O interconnection and termination methods. 5 The data outputs are designed to be a broadband impedance match to 50 Ω and are DC back-terminated with a 62 Ω resistor to V CC. Refer to the 13607CP application note and the HSL IO AN application note for various I/O interconnection and termination methods. 6 Valid when clock to data phase is near center of CPM window. t Q specifications are not fully characterized. 7 It should be noted that the random and deterministic jitter of Inphi's high-speed logic parts are "in the noise" of standard oscilloscope measurement technique. The deterministic jitter (J D ) specified above is the measured peak-to-peak total jitter, using a PRBS data pattern, less the measured source peak-to-peak total jitter. The random jitter (J R ) is based on phase noise measurements. mv CP_DS_Ver1.0 Inphi Proprietary Page 4 of 11

5 Timing Diagram Input and Output Equivalent Circuits CP_DS_Ver1.0 Inphi Proprietary Page 5 of 11

6 Typical DC Operating Characteristics Output Amplitude (OutP, single-ended) vs. Supply with Temperature as parameter VOUTp VOH vs. Supply with Temperature as parameter OutP Amplitude (V) VOUTp VOH (mv) Figure 1. Output amplitude (Vpp) vs. V CC and temperature. Source is 12.5 Gbps PRBS pattern. VOUTp Common Mode Voltage (mv) VOUTp Common Mode Voltage vs. Supply with Temperature as parameter -376 Figure 3. Output common mode voltage (below V CC ) vs. V CC and temperature, 12.5 Gbps PRBS pattern. -64 Figure 2. Output high voltage level (below V CC ) vs. V CC and temperature. Source is 12.5 Gbps PRBS pattern. Eye Crossing (OutP) (%) Eye Crossing (OutP) vs. Supply with Temperature as parameter 40.0 Figure 4. Output data eye crossing vs. V CC and temperature. Source is 12.5 Gbps PRBS pattern. Power Dissipation (W) Power Dissipation vs. Supply with Temperature as parameter Figure 5. Power dissipation (W) vs. V CC and temperature CP_DS_Ver1.0 Inphi Proprietary Page 6 of 11

7 Typical AC Operating Characteristics Gain vs. Frequency of CP in QFN 5.0 Gain (db) Nominal Pin -4 dbm Figure 6. Output data eye. Source is 12.5 Gbps PRBS pattern Freq (GHz) Figure 7. 3 db Bandwidth. Source is sine wave with Pin = -4 dbm (~400 mvpp) single-ended. Peak-to-Peak Jitter (ps) Peak-to-Peak Jitter (OutP, 2^7-1 patt.) vs. Supply with Temperature as parameter 1.0 Figure 8. Output peak-to-peak jitter vs. V CC and temperature. Measurement includes total peak-topeak jitter of source and test equipment. Random Jitter (RMS in fs) Random Jitter (outp) vs. Supply with Temp. as parameter 185 Figure 9. Output random jitter vs. V CC and temperature. Measurement includes random jitter of source and test equipment. Rise Time (OutP) (ps) Rise Time (OutP) vs. Supply with Temperature as parameter 14.0 Figure 10. Output rise time (ps) vs. V CC and temperature. Source is 12.5 Gbps PRBS pattern. Phase Margin (degrees) Phase Margin vs. Supply with Temperature as parameter 310 Figure 11. Analog input to clock input phase margin (degrees) vs. V CC and temperature. Source is 12.5 Gbps PRBS pattern CP_DS_Ver1.0 Inphi Proprietary Page 7 of 11

8 Typical Hysteresis Characteristics Delta Vout (V) Delta V OUT versus Delta V IN C C C 85 C Delta Vin (mv) Figure 12. Typical analog input (IN+) DC hysteresis on the 13606CP. For this measurement, the offset voltage was calculated from the swept data by taking the average of the threshold for the positive and negative sweep. The difference between the thresholds is the hysteresis. Hysteresis versus Soak Time Data Hysteresis (mv) (μs) (Mbps) Data Soak Figure 13. Analog input (IN+) thermal hysteresis on the 13606CP is shown as a function of input soak time in μs (and equivalent data rate in Mb/s). Input used was a 1010 square wave pattern at varying data rates. Clock frequency set to 1 GHz CP_DS_Ver1.0 Inphi Proprietary Page 8 of 11

9 S-Parameter Characteristics CP S11 of IN+ on Three Devices -10 S11 (db) SN1 IN+ SN3 IN+ SN5 IN+ IN+/- Spec Frequency (GHz) Figure 14. Input Return Loss under typical V CC and temperature conditions CP S11 of CLKINp on Three Devices -10 S11 (db) SN1 CLKINp SN3 CLKINp SN5 CLKINp CLKINp/n Spec Frequency (GHz) Figure 15. CLKINp/n Input Return Loss under typical V CC and temperature conditions CP S22 of Three Devices -10 db SN1 DOUTn Low SN3 DOUTn Low SN5 DOUTn Low SN1 DOUTp High SN3 DOUTp High SN5 DOUTp High ORL Spec GHz Figure 16. Output Return Loss under typical V CC and temperature conditions CP_DS_Ver1.0 Inphi Proprietary Page 9 of 11

10 QFN Package Outline Drawing and Pin Assignment Name Pin Description Function IN- 2 Inverting analog input. Internally terminated 65 Ω to V CC. Input IN+ 3 CLKINp 6 CLKINn 7 DOUTp 11 DOUTn 10 GND 1, 4, 5, 8, 9, 12, 14, Paddle Non-inverting analog input. Internally terminated 65 Ω to V CC. Non-inverting clock input. Analog input is latched on the rising edge of this input signal. Internally terminated 50 Ω to V CC. Inverting clock input. Analog input is latched on the falling edge of this input signal. Internally terminated 50 Ω to V CC. Non-inverting data output. Back terminated 60 Ω to V CC. Terminate to 50 Ω to V CC (see note below). Inverting data output. Back terminated 60 Ω to V CC. Terminate to 50 Ω to V CC (see note below). Ground Input Input Input Output Output Supply V CC 13, 15, 16 Power Supply: Connect to +3.3 V Supply Note: for additional information on interconnecting and terminating these I/O see the product application note or the general HSL IO AN application note CP_DS_Ver1.0 Inphi Proprietary Page 10 of 11

11 Order Information Part No CP-S01QFN 13607CP-S01QFN-EVB Description 13 GHz Latched Comparator (+3.3 V Supply) in QFN Package 13 GHz Latched Comparator (+3.3 V Supply) in QFN Package on an Evaluation Board with SMA Connectors Contact Information Inphi Corporation 2393 Townsgate Road, Suite 101 Westlake Village, CA Phone: (805) Fax: (805) products@inphi-corp.com Visit us on the Internet at: For each customer application, customer s technical experts must validate all parameters. Inphi Corporation reserves the right to change product specifications contained herein without prior notice. No liability is assumed as a result of the use or application of this product. No circuit patent licenses are implied. Contact Inphi Corporation s marketing department for the latest information regarding this product. Qualification Notification The 13607CP is fully qualified. Please contact Inphi for the qualification report. Inphi Corporation will honor the full warranty as outlined in Section 5 of Inphi s Standard Customer Purchase Order Terms and Conditions. Version Updates: Version 1.0 (dated ): Initial Release CP_DS_Ver1.0 Inphi Proprietary Page 11 of 11