HDL Implementation of New Performance Improved CSLA Gate Level Architecture

Transcription

1 International Journal for Modern Trends in Science and Technology Volume: 03, Issue No: 07, July 2017 ISSN: HDL Implementation of New Performance Improved CSLA Gate Level Architecture S.Sai Kiran 1 M.Srinivasa Rao 2 1PG Student, Department of ECE, Vasireddy Venkatadri Institute of Technology, Nambur, Andhra Pradesh, India. 2Assistant Professor, Department of ECE, Vasireddy Venkatadri Institute of Technology, Nambur, Andhra Pradesh, India. To Cite this Article S.Sai Kiran and M.Srinivasa Rao, HDL Implementation of New Performance Improved CSLA Gate Level Architecture, International Journal for Modern Trends in Science and Technology, Vol. 03, Issue 07, July2017, pp ABSTRACT In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the con-ventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35% less area delay product (ADP) than the BEC-based SQRT-CSLA, which is best among the existing SQRT-CSLA designs, on average, for different bit-widths. The application-specified integrated circuit (ASIC) synthesis result shows that the BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRT-CSLA, on average, for different bit-widths. Index Terms: Adder, arithmetic unit, low-power design. Copyright 2017 International Journal for Modern Trends in Science and Technology All rights reserved. I. INTRODUCTION VLSI stands for Very large scale integration which refers to those integrated circuits that contain more than 107 transistors. Designing such circuit is difficult and that design needs to overcome the VLSI design problem like Area, Speed, Power dissipation, Design time and Testability.In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder.the sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position.the early years carry look ahead adder used to overcome the delay it will produce all produce all the carries at time but it requires more circuitry, next those are replaced by carry select adders using dual RCAs. In this sum is generated for Cin=1 and Cin=0, depends on input carry one sum is passed as final sum using multiplexer. The problem is again, it requires more circuitry because it requires two full adders at each stage of three bits addition.that is replaced by one RCA and one add-one circuit. There again the same problem that is eliminated by this proposed system CSLA using BEC.The basic idea of this work is to use Binary to Excess-1 Converter (BEC)instead of RCA with Cin= 338 International Journal for Modern Trends in Science and Technology

2 1 in the regular CSLA to achieve lower area and power consumption. The Ripple Carry Adder (RCA) provides the most compact design but takes longer computing time. If there is N-bit RCA, the delay is linearly proportional to N.Thus for large values of N the RCA gives highest delay of all adders. The Carry Look Ahead Adder (CLA) gives fast results but consumes large area. If there is N-bit adder, CLA is fast for N 4, but for large values of N its delay increases more than other adders.so for higher number of bits, CLA gives higher delay than other adders due to presence of large number of fan-in and a large number of logic gates.the Carry Select Adder (CSA) provides a compromise between small area but longer delay RCA and a large area with shorter delay CLA.In rapidly growing mobile industry, faster units are not the only concern but also smaller area and less power become major concerns for design of digital circuits. In mobile electronics, reducing area and power consumption are key factors in increasing portability and battery life. Even in servers and desktop computers power dissipation is an important design constraint. Design of area- and power-efficient high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. Figure bit BEC 2.2 Delay and Area Evaluation Methodology Modified 16-Bit CSLA To optimize the area and power we are using BEC for RCA with Cin=1 for the 16-bit CSLA is shown in the Figure 4.3. The structure is again divided into five groups, and the delay and area estimation of each group are shown. (a) (b) II. MODIFIED 16-BIT CARRY SELECT ADDER 2.1 Introduction In order to reduce the area and power consumption of the regular CSLA, we will use BEC instead of the RCA with Cin=1, which is our main idea of the work. An n+1 -bit BEC is required to replace the n-bit RCA. Figure 2.1 and Table 4.1 shows a structure and the function table of a 4-b BEC and Figure 4.2 illustrates how the basic function of the CSLA is obtained by using the 4-bit BEC together with the multiplexer (mux). One input of the 2:1 mux gets as it input (A3, A2, A1, and A0) and another input of the mux is the BEC output. There by we get two possible partial results in parallel and according to the control signal Cin the mux is used to select either the BEC output or the direct inputs. When the CSLA with large number of bits are designed, the BEC logic stems from the large silicon area reduction. (c) (d) Figure 2.2. Delay and area evaluation of modified CSLA: (a) group2 (b)group3 (c) group4 and (d) group5.h is a half adder. 339 International Journal for Modern Trends in Science and Technology

3 The steps leading to the evaluation are given here. 1) In the Figure 2.2 (a) i.e. the group2 consist of 1 FA and 1 HA for Cin=0 in one 2-bit RCA. We are using a 3-bit BEC instead of another 2-bit RCA with Cin=1 which adds one to the output consideration of delay values of Table 1, the arrival time of selection input the s3(t=9) is harder than the arrival time of selection input c1(time(t)=7) of 2:1 mux and c3(t=10) and later than the s2(t=4).the s3 and mux and partial c3 (input to mux) and mux are responsible for getting the sum3 and final c3 (output from mux).the sum2 depends on c1 and mux. 2) The arrival time of data inputs from the BEC s is always lesser than the arrival time of mux selection input for the remaining group s. The arrival time of mux selection input and the mux delay will decides the delay of the remaining groups. 3) The area count of group2 is determined as follows: Gate count = 36(FA + HA + Mux + BEC) FA = 1(1*9 = 9) HA = 1 (1*5 = 5) AND = 1 NOT = 1 XOR = 2 (2*4 = 8) Mux = 3 (3*4 = 12) 4) Similarly, the Table 4.4 shows the estimated maximum delay and area of the other groups of the modified CSLA. By considering only 11 increases in gate delays, it is clear that the proposed modified CSLA saves 56 gate areas than the regular CSLA, which is clear by comparing Table 1 and Table 2.To further evaluate the performance, we have resorted to ASIC implementation and simulation. Table 1 Delay and area count of modified CSLA groups Group Delay Area Group Group Group Group OPERATION : Carry Select Adders (CSA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. The carry-select adder partitions the adder into several groups, each of which performs two additions in parallel. Therefore, two copies of ripple-carry adder act as carry evaluation block per select stage. One copy evaluates the carry chain assuming the block carry-in is zero, while the other assumes it to be one. Once the carry signals are finally computed, the correct sum and carry-out signals will be simply selected by a set of multiplexers. The 4-bit adder block is RCA Systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position.the CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input and, then the final sum and carry are selected by the multiplexers (MUX). The carry-select adder generally consists of two ripple carry adders and a multiplexer. Adding two n-bit numbers with a carry-select adder is done with two adders (therefore two ripple carry adders) in order to perform the calculation twice, one time with the assumption of the carry being zero and the other assuming one. After the two results are calculated, the correct sum, as well as the correct carry, is then selected with the multiplexer once the correct carry is known. The number of bits in each carry select block can be uniform, or variable. In the uniform case, the optimal delay occurs for a block size of n variable, the block size should have a delay, from additional inputs A and B to the carry out, equal to that of the multiplexer chain leading into it, so that the carry out is calculated just in time. The delay is derived from uniform sizing, where the ideal number of full-adder elements per block is equal to the square root of the number of bits being added, since that will yield an equal number of MUX delays.two 4-bit ripple carry adders are multiplexed together, where the resulting carry and sum bits are selected by the carry-in. Since one ripple carry adder assumes a carry-in of 0, and the other assumes a carry-in of 1, selecting which adder had the correct assumption via the actual carry-in yields the desired result. A 16-bit carry-select adder with a uniform block size of 4 can be created with three of these blocks and a 4-bit ripple carry adder. Since carry-in is known at 340 International Journal for Modern Trends in Science and Technology

4 the beginning of computation, a carry select block is not needed for the first four bits. The delay of this adder will be four full adder delays, plus three MUX delays.a 16-bit carry-select adder with variable size can be similarly created. Here we show an adder with block sizes. This break-up is ideal when the full-adder delay is equal to the MUX delay, which is unlikely. The total delay is two full adder delays, and four MUX delays. Addition is the heart of computer arithmetic, and the arithmetic unit is often the work horse of a computational circuit. They are the necessary component of a data path, e.g. in microprocessors or a signal processor. There are many ways to design an added. The Ripple Carry Adder (RCA) provides the most compact design but takes longer computing time. If there is N-bit RCA, the delay is linearly proportional to N. Thus for large values of N the RCA gives highest delay of all adders. The Carry Look Ahead Adder (CLA) gives fast results but consumes large area. If there is N-bit adder, CLA is fast for N 4, but for large values of N its delay increases more than other adders. So for higher number of bits, CLA gives higher delay than other adders due to presence of large number of fan-in and a large number of logic gates. The Carry Select Adder (CSA) provides a compromise between small area but longer delay RCA and a large area with shorter delay CLA.In rapidly growing mobile industry, faster units are not the only concern but also smaller area and less power become major concerns for design of digital circuits. In mobile electronics, reducing area and power consumption are key factors in increasing portability and battery life. Even in servers and desktop computers power dissipation is an important design constraint. Design of area- and power-efficient high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. Among various adders, the CSA is intermediate regarding speed and area. III. MULTIPLEXER In electronics, a multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector. An electronic multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal. In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect to the output while a logic value of 1 would connect to the output. In larger multiplexers, the number of selector pins is equal to where is the number of inputs.a 2-to-1 multiplexer has a Boolean equation where and are the two inputs, is the selector input, and is the output 3.1 WHY WE REPLACED REGULAR CSLA WITH MODIFIED CSLA? Regular CSLA has 2 ripple carry adders (RCA) in each module for performing addition depending on carry. Using 2 RCAs in each module increases the number of transistors. Increase in number of transistors leads to increase in area and power consumption. 2 nd RCA in each module can be replaced by binary to excess one converter which performs the same operation with less number of transistors which leads to modified CSLA which is area efficient and low power consumption IV. DEVELOPED ADDER DESIGN The developed CSLA is based on the logic formulation given in (5a) (5g), and its structure is shown in Fig. 3(a). It consists of one HSG unit, one FSG unit, one CG unit, and one CS unit. The CG unit is composed of two CGs (CG0 and CG1) corresponding to input-carry 0 and 1. The HSG receives two n-bit operands (A and B) and generate half-sum word s0 and half-carry word c0 of width n bits each. Both CG0 and CG1 receive s0 and c0 from the HSG unit and generate two n-bit full-carry words c0 1 and c1 1 corresponding to input-carry 0 and 1, respectively.the logic diagram of the HSG unit is shown in Fig. 3(b). The circuits of CG0 and CG1 are optimized to take advantage of the fixed input-carry bits. The optimized designs of CG0 and CG1 are shown in Fig. 3(c) and (d), respectively.the CS unit selects one final carry word from the two 341 International Journal for Modern Trends in Science and Technology

5 carry words available at its input line using the control signal cin. It selects c0 1 when cin = 0; otherwise, it selects c1 1. The CS unit can be implemented using an n-bit 2-to-l MUX. However, we find from the truth table of the CS unit that carry words c0 1 and c1 1 follow a specific bit pattern.if c0 1 (i) = 1,then c1 1 (i) =1,irrespective of s0(i) and c0(i), for 0 i n 1. This feature is used for logic optimization of the CS unit. The optimized design of the CS unit is shown in Fig. 5(e), which is composed of n AND OR gates. The final carry word c is obtained from the CS unit.the MSB of c is sent to output as cout, and (n 1) LSBs are XORed with (n 1) MSBs of half-sum (s0) in the FSG [shown in Fig. 3(f)] to obtain (n 1) MSBs of final-sum(s). The LSB of s0 is XORed with cin to obtain the LSB of s.the proposed logic formulation for the CSLA is given as calculation. Instead, one can select the required carry word from the anticipated carry words {c0 and c1} to calculate the final-sum. The selected carry word is added with the half-sum (s0) to generate the final-sum (s).using this method, one can have three design advantages: 1) Calculation of s0 1 is avoided in the SCG unit; 2) the n-bit select unit is required instead of the (n + 1) bit; and 3) small output-carry delay. All these features result in an area delay and energy-efficient design for the CSLA The developed architecture has been simulated and synthesized on FPGA XC3S400K using XILINX ISE-12.4 tool.the performance of three proposed adders are evaluated and they are implemented using VHDL. V. SIMULATION & SYNTHESIS RESULTS FOR DEVELOPED 16BIT CSLA. The simulation result of our designed 16bit carry select adder is shown below Figure 4 Simulation result for developed 16 bit CSLA Figure 3.(a) Proposed CS adder design, where n is the input operand bit-width, and [ ] represents delay (in the unit of inverter delay), n = max(t, 3.5n + 2.7).(b) Gate-level design of the HSG. (c) Gate-level optimized design of (CG0) for input-carry = 0. (d) Gate-level optimized design of (CG1) for input-carry = 1 (e) Gate-level design of the CS unit. (f) Gate-level design of the final-sum generation (FSG) unit. From the above simulation result of proposed carry select adder 16 bit the operands a,b are inputs with cin whereas c10&c11 are carry outputs when cin =0 or cin=1.the final sum is s and final carry is c. As we are adding two 16 bits we obtain 32 bits as output with one carry bit. In the case of the BEC-based CSLA, c1 1 depends on s0 1, which otherwise has no dependence on s0 1 in the case of the conventional CSLA.The BEC method therefore increases data dependence in the CSLA. We have considered logic expressions of the conventional CSLA and made a further study on the data dependence to find an optimized logic expression for the CSLA.We find that a significant amount of logic resource is spent for calculating {s0 1, s1 1 }, and it is not an efficient approach to reject one sum-word after the Table 2 Device utilization summary for developed 16bit CSLA 342 International Journal for Modern Trends in Science and Technology

6 5.1 RTL SCHEMATIC Figure 5 RTL schematic for developed 16bit CSLA 5.2 COMPARISON CHARTS OF PERFORMANCE PARAMETERS OF EXISTING MODELS AND DEVELOPED MODEL The performance of FPGA is realized based on synthesis report the Device Utilization summary and Comparison of different adders are discussed in this chapter. By observing the results, the developed carry select adder is having high performance than the existing modified carry select adder. We can clearly observe the improvement in the area,power and delay product for developed carry select adder COMPARISION TABLE FOR EXISTING AND DEVELOPED 16 BIT ADDER S. N o Logic Available RCA BEC Utilizatio n Used Used Used PROPOSE D CS No of slices No of LUTS No of IOBS Maximum delay(ns) Table 3. Device utilization summary for (estimated values) for 16 bit DELAY COMPARISION CHART FOR EXISTING AND DEVELOPED 16 BIT ADDER Figure 6 Delay comparison chart for existing and developed 16bit adder VI. CONCLUSION Thus logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter BEC-based CSLA are reduced and analyzed to study the data dependence and to identify redundant logic operations. Here eliminated all the redundant logic operations present in the conventional CSLA, BEC- CSLA and proposed a new logic formulation for CSLA. In the developed scheme, depending on the initial carry the total operation decides the operation of two individual blocks which itself generates the two final sum s and carry individually. Here the main advantage is the output doesnot require any multiplexer. Only one block it-self works initially on input carry so totally half of the logic implementation is automatically reduced.an efficient CSLA design is obtained using optimized logic units. The developed CSLA design involves significantly less area and delay than the present BEC-based CSLA. The architecture has been verified on XILINX Spartan - 3E and respective synthesis result shows that the developed SQRT-CSLA involves nearly 35% less area delay product (ADP) and consumes 50% less energy than the developed CSLA, on average, for different bit-widths like 8, 16 and 32 bit widthsthan the BEC-based SQRT-CSLA. VII. FUTURE SCOPE Now a day s Carry Select Adder (CSLA) used in many data-processing processors to perform fast arithmetic functions.the speed of Proposed CSLA greater than Modified SQRT CSLA, but the area and power reduced compared to modified SQRT CSLA. So,proposed SQRT CSLA can be replaced by Modified SQRT CSLA,where the area and power major constraints than speed. In future by using more and more sophisticated fabrication techniques area can be minimized. REFERNCES [1] S.Manju and V. Sornagopal, An efficient SQRT architecture of carry select adder design by common Boolean logic, in Proc. VLSI ICEVENT, 2013,pp. 15 [2] M. Z. Rahman and L. Kleeman, A delay matched approach for the design of asynchronous sequential circuits, Dept. Comput. Syst.Technol., Univ. Malaya, Kuala Lumpur, Malaysia, Tech. Rep ,2013. [3] B. Ramkumar and H.M. Kittur, Low-power and area-efficient carry-select adder, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2,pp , Feb International Journal for Modern Trends in Science and Technology

7 [4] I.-C. Wey, C.-C. Ho, Y.-S. Lin, and C. C. Peng, An area-efficient carry select adder design by sharing the common Boolean logic term, in Proc.IMECS, 2012, pp. 1 4 [5] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs,2nd ed. New York, NY, USA: Oxford Univ. Press, [6] R. F. Tinder, Asynchronous Sequential Machine Design and Analysis:A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems. San Mateo, CA, USA:Morgan, [7] A. P. Chandrakasan, N. Verma, and D. C. Daly, Ultralow-power electronics for biomedical applications, Annu. Rev. Biomed. Eng., vol. 10, pp , Aug [8] P. Choudhury, S. Sahoo, and M. Chakraborty, Implementation of basic arithmetic operations using cellular automaton, in Proc. ICIT, 2008,pp [9] C. Cornelius, S. Koppe, and D. Timmermann, Dynamic circuit techniques in deep submicron technologies: Domino logic reconsidered, in Proc. IEEE ICICDT, Feb. 2006, pp.1 4. [10] Y. He, C. H. Chang, and J. Gu, An area-efficient 64-bit square root carryselect adder for low power application, in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 4, pp [11] D. Geer, Is it time for clockless chips? [Asynchronous processor chips], IEEE Comput., vol. 38, no. 3, pp ,Mar [12] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Reading, MA, USA: Addison-Wesley, [13] M. D. Riedel, Cyclic combinational circuits, Ph.D. dissertation,dept. Comput. Sci., [14] M. Anis, S. Member, M. Allam, and M. Elmasry, Impact of technology scaling on CMOS logic styles, IEEE Trans. CircuitsSyst., Analog Digital Signal Process., vol. 49, no. 8, pp ,Aug [15] Y. Kim and L.-S. Kim, 64-bit carry-select adder with reduced area, Electron. Lett., vol. 37, no. 10, pp , May [16] F.-C. Cheng, S. H. Unger, and M. Theobald, Self-timed carry look ahead adders, IEEE Trans. Comput., vol. 49, no. 7, pp ,Jul [17] K. K. Parhi, VLSI Digital Signal Processing. New York, NY, USA:Wiley,1998. [18] W. Liu, C. T. Gray, D. Fan, and W. J. Farlow, A 250-MHz wavepipelined adder in 2-μm CMOS, IEEE J. Solid-State Circuits, vol. 29,no. 9, pp , Sep [19] S. Nowick, Design of a low-latency asynchronous adder using speculative completion, IEE Proc. Comput. Digital Tech., vol. 143, no. 5,pp , Sep [20] O. J. Bedrij, Carry-select adder, IRE Trans. Electron. Comput.,vol. EC-11, no. 3, pp , Jun International Journal for Modern Trends in Science and Technology