Discontinuous Conduction Mode Analysis of Phase Modulated Series Resonant Converter

Transcription

1 Discontinuous Conduction Mode Analysis of Phase Modulated Series Resonant Converter Utsab Kundu, Parthasarathi Sensarma Department of Electrical Engineering IIT Kanpur, India Abstract This paper proposes an analytical approach to derive voltage gain for phase modulated (PM) dc-dc series resonant converter (SRC) operating in discontinuous conduction mode (DCM). Conventional fundamental harmonic approximation (FHA) technique is extended for non-ideal series resonant tank. The DCM analysis is presented in a normalized form defining appropriate base quantities. The converter is analyzed both in time and frequency domain to derive a non-linear algebraic function of diode rectifier extinction angle. The root of this function is numerically determined using MATLAB and used to predict the dc bus voltage. Experimental results are presented to validate the analysis. I. INTRODUCTION Phase modulated (PM) dc-dc series resonant converters (SRCs) are traditionally operated in continuous conduction mode (CCM) [1], typically above resonant frequency to achieve zero voltage switching (ZVS) of full-bridge (FB) switches. This approach compromises converter voltage gain significantly while ensuring ZVS in entire modulation range. On the other hand, discontinuous conduction mode (DCM) of SRC (DCMSRC) implies zero current switching (ZCS) of FB switches while retaining the ZCS property of rectifier diodes [2]. Load and modulation independent soft-switching, while operating at tank resonant frequency, makes DCMSRC superior compared to its CCM counterpart. But absence of an analytical formulation of the voltage gain complicates the DCMSRC converter design process, requiring repeated circuit simulations for design convergence. Conventional fundamental harmonic approximation (FHA) method [3] and extended describing function (EDF) technique [4] are not applicable for DCMSRC due to the discontinuous nature of series inductor current. Time domain analysis of DCM- SRC for above-resonance operation is reported in [5]. But this approach cannot be directly adopted to determine voltage conversion ratio (A v ) for steady state DCM operation while switching at resonant frequency. This paper presents DCM analysis of phase modulated SRC, switched at resonant frequency, using time and frequency domain representations. Structured derivation of A v is presented, which requires numerical solution of a single well-defined nonlinear algebraic equation. II. FHA ANALYSIS OF NON-IDEAL SRC The complete circuit diagram of series resonant boost dc-dc converter is shown in fig. 1a. The full-bridge (FB) switch network is switched using phase modulation approach [6]. It produces a high frequency square/quasi-square wave to excite the resonant tank. The tank comprises series resonating elements, L and C, and terminated at the primary of a step-up high-frequency transformer (HFT). Secondary of the HFT is connected to a diode bridge rectifier (DBR), followed by a filter capacitor, C f, to attenuate the switching harmonics. The following assumptions are considered for subsequent analysis. 1) Primary side MOSFETs and rectifier diodes are ideal. 2) Dead-time between the gating signals of FB MOSFETs are neglected. 3) The HFT does not contain any air-gap and thus offers very high magnetizing inductance. So, the parallel magnetizing branch is excluded from analysis of the tank network, shown in fig. 1b.

2 (a) Fig. 1. (a) Series resonant dc-dc converter, (b) Non-ideal tank network. (b) 4) The only non-ideality, r, comprises winding resistances of both inductor and transformer and the effective series resistance (ESR) of capacitor. 5) The leakage inductance of HFT is included in the tank inductance, L. For a given HFT turns ratio, 1 : N, voltage transfer characteristic of the tank network is normalized with respect to its natural frequency, ω 0, and expressed as V p (s) V t (s) = s 0 Q 0 s s 0 (Q 0 + Q r ) + 1, s 0 = s ω 0, C C Q 0 = R L, Q r = r L, R = 8R L π 2 N. (1) 2 To extract maximum gain, the switching frequency (f s ) is decided to be f s = ω 0 /2π = 1/(2π LC). (2) Using FHA analysis [3], the voltage gain expression for the entire power train is derived as < V dc > < V g > = < V t > < V p > < V s > < V dc > < V g > < V t > < V p > < V s >, = 2 2 π sin(α 2 ) R R + r N π 2 2, = N sin( α 2 ) R R + r, (3) where, <> denotes respective rms quantities and α is the modulation angle as shown in fig. 3. III. DCM ANALYSIS OF SRC All the parameters and state variables are referred to the primary side of HFT and normalized using the base quantities defined as follows. V B = V gmin, Z B = L/C, I B = V B /Z B, (4) where, V gmin denotes minimum input voltage. Per unit (p.u.) definitions of different parameters, state variables, input and output voltages are listed as follows. r pu = r Z B, R Lpu = R L N 2 Z B, i spu = i s I B, v Cpu = v C V B, V gpu = V g V B, V dcpu = V dc NV B, v ppu = v p /V B, i Rpu = (Ni R )/I B. (5) A. Time domain analysis Considering the half-wave symmetry of tank variables, the analysis is presented for a half cycle of DCM switching period. This half-cycle is further divided into three sub-intervals. Equivalent circuits of each sub-interval are shown in fig. 2. Fig. 3 illustrates ideal waveforms of state variables for steady-state DCM operation of SRC, where θ = ω 0 t and β denotes extinction angle of DBR. 1) Interval-I (0 θ α): This mode begins when the diagonal pair M 1 -M 4 of FB switch network is turned on. Due to discontinuous nature of the inductor current, i s, secondary side DBR also turns on at the beginning of this mode. Switching function, S, of DBR is shown in fig. 3. During this interval, tank capacitor voltage, v C, rises from its

3 (a) Interval-I (b) Interval-II (c) Interval-III Fig. 2. Equivalent circuits during three intervals of DCM. initial value V C0 and i s builds up from zero. This ensures ZCS turn-on of FB MOSFETs M 1 and M 4 and secondary diodes D 1 and D 4. This mode ends when i s reaches its peak, I s1, and v C rises to V C1. The normalized state equations for this interval are derived as (di spu /dθ) + r pu i spu + v Cpu = K, (6) (dv Cpu /dθ) = i spu, K = V gpu V dcpu. (7) The boundary conditions of Interval-I are normalized using respective base quantities and given by i spu (0) = 0, v Cpu (0) = V C0pu, (8) i spu (α) = I s1pu, v Cpu (α) = V C1pu, (9) The state equations (6) and (7) are solved using these mode boundaries as follows. I s1pu = A 1 e x (p + E) sin γ (10) V C1pu = A 1 e x (cos γ + 2E sin γ) + K (11) All parameters of (10) and (11) are listed in Appendix A. 2) Interval-II (α θ β): ZVS turn-on of M 3 and hard turn-off of M 4 define the beginning of this mode. The source V g remains disconnected thus forcing i s to fall. But v C further rises and reaches V C2 at the end of this interval. This mode ends when the DBR cease to conduct ensuring ZCS turn-off of diodes D 1 and D 4. (di spu /dθ 1 ) + r pu i spu + v Cpu = V dcpu, (12) (dv Cpu /dθ 1 ) = i spu, θ 1 = (θ α) (13) Noting that i s becomes zero at the end of this interval, the mode boundaries are presented as i spu (β) = 0, v Cpu (β) = V C2pu. (14) Fig. 3. Ideal waveforms of SRC operating in DCM. The state equations are solved using (9) and (14) as follows. 0 = e y [I s1pu cos δ F sin δ], (15) V C2pu = e y [A 2 cos δ + B 2 sin δ] V dcpu. (16) All parameters of (15) and (16) are presented in Appendix A. 3) Interval-III (β θ π): During this mode, the DBR is in off state and thus i s remains zero. The capacitor holds the charge and v C remains constant at V C2. ZCS turn-off of M 1 and ZCS turn-on of M 2 defines the end of this interval. Considering the

4 steady state of capacitor voltage, v C, the following expression is derived. V C2pu = V C0pu. (17) These simultaneous algebraic mode equations are simplified to derive an expression for V dcpu by eliminating intermediate variables as follows. Noting that e y 0, the expression for I s1pu is derived from (15) as I s1pu = A 2 J, J = 2p2 + (r 2 pu/2) 2p cot δ r pu. (18) Equating (10) and (18), the expression for V C1pu is simplified as V C1pu = M(K V C0pu ) V dcpu, M = [e x (p + E) sin γ]/j. (19) Rearranging (11) and (19), V C0pu = [1 (1/(M + U))]V gpu V dcpu, U = e x [cos γ + 2E sin γ]. (20) From (16) and (17), another expression for V C0pu is derived as V C0pu = [GV gpu (G + 1)V dcpu ]/(G 1), G = MDe y, D = cos δ + [(J/p) + (r pu /2p)] sin δ. (21) Equating (20) and (21), the converter voltage gain, A vt, is expressed as a function of α, R Lpu and β and given by A vt = V dcpu = 1 [ 1 + G 1 ] V gpu 2 M + U (22) B. Frequency domain analysis Frequency domain analysis of SRC is performed using multi-order decomposition technique [7]. Large-signal model of the converter is considered as a superposition of n-subsystems. Each of these operates at different steady-state frequencies, as shown in fig. 4a. Due to the non-linear nature of DBR, n-th order harmonic of i s generates the following components of rectified current, i R. i (n) spu S (m) = i (n m) Rpu + i (n+m) Rpu, (23) where, m is the harmonic order of switching function, S. It is obvious that n = m constructs the dc component of i R, I (0) R and n m results in higher order switching harmonics. Since the converter operates at resonant frequency, the higher order harmonics are adequately attenuated. With this simplified, yet realistic, assumption a reduced order model is realized using n = m = 1 and depicted in fig. 4b. The fundamental components of tank input voltage, v t and transformer primary voltage, v p is normalized using base voltage, V B and expressed as follows. tpu = 2V gpu [sin ϕ cos θ + (1 cos ϕ) sin θ], (24) π v (1) v (1) ppu = (2/π)[A p cos θ + B p sin θ], (25) A p = (V dcpu + V C0pu ) sin β, (26) B p = V dcpu (1 cos β) V C0pu (1 + cos β). (27) Assuming tuned operation of SRC, the p.u. fundamental component of i s is derived as i (1) spu = (v (1) tpu v (1) ppu)/r pu. (28) (a) Fig. 4. (a) Large-signal and (b) Reduced order model of SRC. (b)

5 The fundamental component of S is given by S (1) = (2/π)[sin β cos θ + (1 cos β) sin θ]. (29) Using (23), (28) and (29), I (0) Rpu is derived as I (0) Rpu = 2 r pu π 2 [V gpuλ 2V dcpu (1 cos β)], (30) λ = cos(α β) cos α cos β + 1. (31) Assuming the double frequency switching harmonic, i (2) Rpu is completely bypassed through C f, the normalized dc bus voltage, V dcpu is expressed as V dcpu = I (0) RpuR Lpu. (32) Rearranging (32), the voltage gain expression (A vf ) from frequency domain analysis is derived. A vf = V dcpu V gpu = 2λR Lpu π 2 r pu + 4R Lpu (1 cos β). (33) Using (22) and (33), a non-linear algebraic function of β is defined as follows. f(β) = A vt A vf. (34) For a given set of (R Lpu, α), the root of f(β) is numerically determined. Subsequently, A v is calculated from either (22) or (33). IV. RESULTS AND DISCUSSIONS An experimental prototype of series resonant dcdc boost converter is fabricated and shown in fig. 5a- 5b. It comprises the FB switch network along with the gate drivers, series resonant tank network, high frequency transformer, the diode bridge rectifier and output filter capacitor. Analog phase shift controller is used to switch the FB MOSFETs [6]. All the parameters of experimental hardware and operating conditions are listed in Table I. Considering these data, β is numerically determined using (34) in MATLAB. The dc bus voltage, V dc is calculated from (3) and (33) for CCM and DCM operations, respectively and tabulated in Table II. CCM operation of SRC is depicted in fig. 5c-5d, where continuous nature of secondary side current, i sec, is evident. Peak value of tank capacitor voltage, v C, is greater than the transformer primary voltage, TABLE I SYSTEM SPECIFICATIONS. L C r L m f s N C f V gmin V g α R L (CCM) R L (DCM) 3.84 µh 165 nf 100 mω 700 µh 200 khz 20 1 µf 10 V 20 V kω 6.4 kω (a) (b) (c) (d) analytical experimental V dc (V) analytical experimental β (deg.) (e) (f) R L (kω) (g) R 6 7 L (kω) Fig. 5. Experimental prototype: (a) Top view, (b) Bottom view. Output dc bus voltage and electrical variables of tank network: (c)-(d) CCM operation, (e)-(f) DCM operation. Analytical and experimental plots of (g) V dc and (h) β at different loads. Scale: v t (20 V/div), V dc (50 V/div), i sec - CCM (200 ma/div), DCM (100 ma/div), i s (2 A/div), v C (5 V/div), v p (5 V/div). X-axis: (Time - 1 µs/div). (h)

6 v p. This ensures the rectifier diodes remain in onstate for the entire switching cycle which confirms CCM operation. The spikes in v t indicates that the leading leg of FB network (M 1 -M 2 ) does not experience soft turn-on and thus increases voltage stress on switches. But DCM operation (figs. 5e & 5f) ensures ZCS turn-on of leading leg MOSFETs which reduces voltage stress. When the DBR turns-off, i sec does not become zero in practice due to the presence of body capacitance across rectifier diodes. The series LC branch resonates with diode capacitances and oscillations are experimentally observed not only in i s and i sec, but in v c also. Moreover, finite magnetizing inductance (L m ) of HFT acts as a resonating element during DCM operation. This causes slow transition at the edges of v p during off-state of DBR. Obviously, reflection of capacitor voltage in transformer primary does not appear, as shown in fig. 3. However, the rectifier extinction angle, β, is measured as shown in fig. 5f and presented in Table II. Variation of V dc and β with varying load conditions are shown in fig. 5g and 5h, respectively. The following error quantities are defined, e V dc = V dc (anl) V dc (exp) /V dc (anl),(35) e β = β(anl) β(exp) /β(anl), (36) where, (anl) and (exp) denotes analytical and experimental values, respectively. These errors are expressed in percentage and shown in fig. 6 at different loads. Close agreements of experimentally obtained V dc and β with analytical predictions indicate that TABLE II ANALYTICAL AND EXPERIMENTAL RESULTS. Results β V dc (DCM) V dc (CCM) Analytical V V Experimental V 106 V e Vdc e β R L (kω) Error (%) Fig. 6. Plots of e V dc and e β at different loads. the effects of finite L m and body capacitances are negligible. V. CONCLUSION Time and frequency domain analysis for phase modulated series resonant dc-dc converter operating in DCM is presented. Advantages of operating SRC in DCM is discussed. Limitations of conventional approaches are noted for DCM analysis. The analysis is presented in a normalized form considering ESR in resonant tank. Voltage gain expressions are derived both in time and frequency domain. The rectifier extinction angle is determined by numerically solving a non-linear algebraic equation, which is analytically derived. Analytical prediction for output dc bus voltage is experimentally validated. This normalized analytical approach provides a definite design guideline for phase modulated SRC operating in DCM. APPENDIX A PARAMETERS OF MODE EQUATIONS p = 1 (r 2 pu/4), A 1 = V C0pu K, E = r pu /4p, x = (r pu α)/2, γ = pα F = (pa 2 + (B 2 r pu /2)), A 2 = V C1pu + V dcpu, B 2 = (1/p)[I s1pu + (r pu A 2 /2)], y = r pu (α β)/2, δ = p(β α) REFERENCES [1] Kline, M.; Izyumin, I; Boser, B.; Sanders, S., Capacitive power transfer for contactless charging, in Proc. IEEE Applied Power Electronics Conf., Mar. 6-11, 2011, pp [2] Vandelac, J.-P.; Ziogas, P.D., A DC to DC PWM series resonant converter operated at resonant frequency, in IEEE Trans. Industrial Electron., vol. 35, no. 3, pp , Aug [3] Erickson R. W.; Maksimovic D., Fundamentals of Power Electronics, (2nd ed) Springer International Edition, [4] Ayachit, A.; Murthy-Bellur, D.; Kazimierczuk, M.K., Steadystate analysis of series resonant converter using extended describing function method, in Proc. IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2012, pp [5] Safaee, A.; Jain, P.; Bakhshai, A., Time-domain steady-state analysis of fixed-frequency series resonant converters with phaseshift modulation, in Proc. IEEE Transportation Electrification Conference and Expo (ITEC), June 2014, pp [6] Kundu, U.; Chakraborty, S.; Sensarma, P., Automatic Resonant Frequency Tracking in Parallel LLC Boost DC-DC Converter, IEEE Trans. Power Electron., vol. 30, no. 7, pp , Jul [7] Chaudhary, P.; Sensarma, P., Front-End Buck Rectifier With Reduced Filter Size and Single-Loop Control, in IEEE Trans. Industrial Electron., vol. 60, no. 10, pp , Oct