Flash Erasable, Reprogrammable CMOS PAL Device

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1 Features Low power ma max. commercial (1 ns) 13 ma max. commercial (5 ns) CMO Flash EPROM technology for electrical erasability and reprogrammability Variable product terms 2 x(8 through 16) product terms User-programmable macro Output polarity control ndividually selectable for registered or combinatorial operation Up to 22 input terms and 1 outputs DP, LCC, and PLCC available 5 ns commercial version 4 ns t CO 3 ns t Logic Block Diagram (PDP/CDP) V PALCE22V1 Flash Erasable, Reprogrammable CMO PAL Device 5 ns t PD 181-MHz state machine 1 ns military and industrial versions 7 ns t CO 6 ns t 1 ns t PD 11-MHz state machine 15-ns commercial, industrial, and military versions 25-ns commercial, industrial, and military versions High reliability Proven Flash EPROM technology 1% programming and functional testing Functional Description The Cypress PALCE22V1 is a CMO Flash Erasable second-generation programmable array logic device. t is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macro. CP/ PROGRAMMABLE AND ARRAY (132 X 44) Reset Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Preset /O /O 8 /O 7 /O 6 /O 5 /O 4 /O 3 /O 2 /O 1 /O V CC LCC PLCC Top View CE22V1 1 Top View Pin Configuration CP/ NC V CC /O /O 1 CP/ NC CC V /O /O 1 NC NC V /O /O /O2 /O3 /O4 N/C /O5 /O6 /O7 CE22V1 2 NC NC V /O /O /O2 /O3 /O4 N/C /O5 /O6 /O7 CE22V1 3 PAL is a registered trademark of Advanced Micro Devices. Cypress emiconductor Corporation 31 North First treet an Jose CA eptember 16

2 PALCE22V1 election Guide t PD ns t ns t CO ns CC ma Generic Part Number Com l Mil/nd Com l Mil/nd Com l Mil/nd Com l Mil/nd PALCE22V PALCE22V PALCE22V PALCE22V PALCE22V Functional Description (continued) The PALCE22V1 is executed in a 24-pin 3-mil molded DP, a 3-mil cerdp, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 1 outputs. The PALCE22V1 can be electrically erased and reprogrammed. The programmable macro provides the capability of defining the architecture of each output individually. Each of the 1 potential outputs may be specified as registered or combinatorial. Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further configurability is provided through array configurable output enable for each potential output. This feature allows the 1 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination /O controlled by the programmable array. PALCE22V1 features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PALCE 22V1 is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance. Additional features of the Cypress PALCE22V1 include a synchronous preset and an asynchronous reset product term. These product terms are common to all macros, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up. The PALCE22V1, featuring programmable macros and variable product terms, provides a device with the flexibility to implement logic functions in the 5- to 8-gate-array complexity. ince each of the 1 output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to 12 inputs and 1 outputs are possible. The 1 potential outputs are enabled using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macro. These macros are programmable to provide a combinatorial or registered inverting or non-inverting output. n a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is available for establishing the next result in applications such as control state machines. n a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the /O pin is made available to the array. The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic. Along with this increase in functional density, the Cypress PALCE22V1 provides lower-power operation through the use of CMO technology, and increased testability with Flash reprogrammability. Configuration Table Registered/Combinatorial C 1 C Configuration Registered/Active LOW 1 Registered/Active HGH 1 Combinatorial/Active LOW 1 1 Combinatorial/Active HGH 2

3 PALCE22V1 Macro AR D Q OUTPUT ELECT MUX CP Q 1 P NPUT/ FEEDBACK MUX 1 C 1 C MACROCELL CE22V1 4 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) torage Temperature C to +15 C Ambient Temperature with Power Applied C to +125 C upply Voltage to Ground Potential (Pin 24 to Pin 12)....5V to +7.V DC Voltage Applied to Outputs in High Z tate....5v to +7.V DC nput Voltage....5V to +7.V Output Current into Outputs (LOW)...16 ma DC Programming Voltage V Latch-Up Current... >2 ma tatic Discharge Voltage (per ML-TD-883, Method 315)... >21V Operating Range Ambient Range Temperature V CC Commercial C to +75 C 5V ±5% ndustrial 4 C to +85 C 5V ±1% Military [1] 55 C to +125 C 5V ±1% Note: 1. T A is the instant on case temperature. 3

4 PALCE22V1 ] Electrical Characteristics Over the Operating Range [2] Parameter Description Test Conditions Min. Max. Unit V OH Output HGH Voltage V CC = Min., OH = 3.2 ma Com l 2.4 V V N = V H or V L OH = 2 ma Mil/nd V OL Output LOW Voltage V CC = Min., OL = 16 ma Com l.5 V V N = V H or V L OL = 12 ma Mil/nd V H nput HGH Level Guaranteed nput Logical HGH Voltage for All nputs [3] 2. V [4] V L nput LOW Level Guaranteed nput Logical LOW Voltage for All nputs [3].5.8 V X nput Leakage Current V < V N < V CC, V CC = Max. 1 1 µa OZ Output Leakage Current V CC = Max., V < V OUT < V CC 4 4 µa C Output hort Circuit Current V CC = Max., V OUT =.5V [5,6] 3 13 ma CC1 tandby Power upply V CC = Max., 1, 15, 25 ns Com l ma Current V N = GND, 5, 7.5 ns 13 ma Outputs Open in Unprogrammed 15, 25 ns Mil/nd 12 ma Device 1 ns 12 ma [6] CC2 Operating Power upply V CC = Max., V L = 1, 15, 25 ns Com l 11 ma Current V, V H = 3V, 5, 7.5 ns Com l 14 ma Output Open, Device Programmed 15, 25 ns Mil/nd 13 ma as a 1-Bit 1 ns Mil/nd 13 ma Counter, f = 25 MHz Capacitance [6] Parameter Description Test Conditions Min. Max. Unit C N nput Capacitance V N = f = 1 MHz 1 pf C OUT Output Capacitance V OUT = f = 1 MHz 1 pf ] Endurance Characteristics [6] Parameter Description Test Conditions Min. Max. Unit N Minimum Reprogramming Cycles Normal Programming Conditions 1 Cycles Notes: 2. ee the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. V L (Min.) is equal to -3.V for pulse durations less than 2 ns. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V OUT =.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Tested initially and after any design or process changes that may affect these parameters. 4

5 PALCE22V1 AC Test Loads and Waveforms 5V R1238Ω (31Ω ML) 5V R1238Ω (31Ω ML) OUTPUT NCLUDNG JG AND COPE C L (a) R217Ω (236Ω ML) OUTPUT NCLUDNG JG AND COPE 5pF (b) R217 Ω (236Ω ML) OUTPUT C L (c) 75Ω (1.2KΩ ML) ALL NPUT PULE 3.V GND % 1% % 1% < 2 ns < 2 ns CE22V1 5 (d) Equivalent to: THÉ VENN EQUVALENT(Commercial) Equivalent to: THÉ VENN EQUVALENT(Military) Ω 136Ω OUTPUT 2.8V=V thc CE22V1 6 OUTPUT 2.13V=V thm CE22V1 7 Load peed C L Package 5, 7.5, 1, 15, 25 ns 5 pf PDP, CDP, PLCC, LCC Parameter V X Output Waveform Measurement Level t ER (- ) 1.5V V OH.5V VX t ER (+) 2.6V V OL.5V V X t EA (+) V V X 1.5V V OH t EA (- ) V thc VX.5V V OL (e) Test Waveforms 5

6 PALCE22V1 ] Commercial witching Characteristics PALCE22V1 [2,7] 22V1-5 22V1-7 22V1-1 22V V1-25 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit t PD nput to Output Propagation Delay [8] ns t EA nput to Output Enable Delay [] ns t ER nput to Output Disable Delay [1] ns t CO Clock to Output Delay [8] ns t 1 nput or Feedback et-up Time ns t 2 ynchronous Preset et-up ns Time t H nput Hold Time ns t P External Clock Period (t CO + t ) ns t WH Clock Width HGH [6] ns t WL Clock Width LOW [6] ns f MAX1 External Maximum MHz Frequency (1/(t CO + t )) [11] f MAX2 Data Path Maximum Frequency MHz (1/(t WH + t WL )) [6, 12] f MAX3 nternal Feedback Maximum MHz Frequency (1/(t CF + t )) [6,13] t CF Register Clock to ns Feedback nput [6,14] t AW Asynchronous Reset Width ns t AR Asynchronous Reset ns Recovery Time t AP Asynchronous Reset to ns Registered Output Delay t PR ynchronous Preset ns Recovery Time t PR Power-Up Reset Time [6,15] µs Notes: 7. Part (a) of AC Test Loads and Waveforms is used for all parameters except t ER and t EA(+). Part (b) of AC Test Loads and Waveforms is used for t ER. Part (c) of AC Test Loads and Waveforms is used for t EA(+). 8. Min. times are tested initially and after any design or process changes that may affect these parameters.. The test load of part (a) of AC Test Loads and Waveforms is used for measuring t EA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring t EA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 1. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to the point at which a previous HGH level has fallen to.5 volts below V OH min. or a previous LOW level has risen to.5 volts above V OL max. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 14. This parameter is calculated from the clock period at f MAX internal (1/f MAX3 ) as measured (see Note above) minus t. 15. The registers in the PALCE22V1 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the rise in V CC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied 6

7 PALCE22V1 Military and ndustrial witching Characteristics PALCE22V1 [2,7] 22V1-1 22V V1-25 Parameter Description Min. Max. Min. Max. Min. Max. Unit t PD nput to Output Propagation Delay [8] ns t EA nput to Output Enable Delay [] ns t ER nput to Output Disable Delay [1] ns t CO Clock to Output Delay [8] ns t 1 nput or Feedback et-up Time ns t 2 ynchronous Preset et-up ns Time t H nput Hold Time ns t P External Clock Period (t CO + t ) ns t WH Clock Width HGH [6] ns t WL Clock Width LOW [6] ns f MAX1 External Maximum Frequency MHz (1/(t CO + t )) 11] f MAX2 Data Path Maximum Frequency MHz (1/(t WH + t WL )) [6,12 ] f MAX3 nternal Feedback Maximum MHz Frequency (1/(t CF + t )) [6,13] t CF Register Clock to ns Feedback nput [6,14] t AW Asynchronous Reset Width ns t AR Asynchronous Reset ns Recovery Time t AP Asynchronous Reset to ns Registered Output Delay t PR ynchronous Preset ns Recovery Time t PR Power-Up Reset Time [6,15] µs 7

8 PALCE22V1 witching Waveforms NPUT /O, REGTERED FEEDBACK YNCHRONOU PREET t t t t WH WL H CP t PR t P t AW t AR AYNCHRONOU REET REGTERED OUTPUT COMBNATORAL OUTPUT t CO t PD t AP t [1] ER [1] t ER [] t EA t [] EA CE22V1 8 Power-Up Reset Waveform [15] POWER UPPLY VOLTAGE 1% % t PR V CC REGTERED ACTVE LOW OUTPUT t CLOCK t PR MAX = 1 µs t WL CE22V1 8

9 PALCE22V1 Functional Logic Diagram for PALCE22V1 1 AR P CE22V1 1 13

10 PALCE22V1 Ordering nformation CC t PD t t CO Package Operating (ma) (ns) (ns) (ns) Ordering Code Name Package Type Range PALCE22V1-5PC P13 24-Lead (3 ML) Molded DP Commercial PALCE22V1-5JC J64 28-Lead Plastic Leaded Chip Carrier PALCE22V1-7JC J64 28-Lead Plastic Leaded Chip Carrier Commercial PALCE22V1-7PC P13 24-Lead (3-Mil) Molded DP PALCE22V1-1JC J64 28-Lead Plastic Leaded Chip Carrier Commercial PALCE22V1-1PC P13 24-Lead (3-Mil) Molded DP PALCE22V1-1J J64 28-Lead Plastic Leaded Chip Carrier ndustrial PALCE22V1-1P P13 24-Lead (3-Mil) Molded DP PALCE22V1-1DMB D14 24-Lead (3-Mil) CerDP Military PALCE22V1-1KMB K73 24-Lead Rectangular Cerpack PALCE22V1-1LMB L64 28-quare Leadless Chip Carrier PALCE22V1-15JC J64 28-Lead Plastic Leaded Chip Carrier Commercial PALCE22V1-15PC P13 24-Lead (3-Mil) Molded DP PALCE22V1-15J J64 28-Lead Plastic Leaded Chip Carrier ndustrial PALCE22V1-15P P13 24-Lead (3-Mil) Molded DP PALCE22V1-15DMB D14 24-Lead (3-Mil) CerDP Military PALCE22V1-15KMB K73 24-Lead Rectangular Cerpack PALCE22V1-15LMB L64 28-quare Leadless Chip Carrier PALCE22V1-25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial PALCE22V1-25PC P13 24-Lead (3-Mil) Molded DP PALCE22V1-25J J64 28-Lead Plastic Leaded Chip Carrier ndustrial PALCE22V1-25P P13 24-Lead (3-Mil) Molded DP PALCE22V1-25DMB D14 24-Lead (3-Mil) CerDP Military PALCE22V1-25KMB K73 24-Lead Rectangular Cerpack PALCE22V1-25LMB L64 28-quare Leadless Chip Carrier MLTARY PECFCATON Group A ubgroup Testing DC Characteristics Parameter ubgroups V OH 1, 2, 3 V OL 1, 2, 3 V H 1, 2, 3 V L 1, 2, 3 X 1, 2, 3 OZ 1, 2, 3 CC 1, 2, 3 witching Characteristics Parameter ubgroups t PD, 1, 11 t CO, 1, 11 t, 1, 11 t H, 1, 11 Document #: B 1

11 PALCE22V1 Package Diagrams 24 Lead (3 Mil) CerDP D14 ML-TD-1835 D- Config.A 28 Lead Plastic Leaded Chip Carrier J64 24 Lead Rectangular Cerpack K73 ML-TD-1835 F- 6 Config.A 28 quare Leadless Chip Carrier L64 ML-TD-1835 C-4 11

12 PALCE22V1 Package Diagrams (continued) 24 Lead (3 Mil) Molded DP P13/P13A Cypress emiconductor Corporation, 16. The information contained herein is subject to change without notice. Cypress emiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress emiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress emiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress emiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress emiconductor against all charges.

Flash-erasable Reprogrammable CMOS PAL Device

Flash-erasable Reprogrammable CMOS PAL Device PALCE22V1 is a replacement device for PALC22V1, PALC22V1B, and PALC22V1D. UE ULTRA37 TM FOR ALL NEW DEGN PALCE22V1 Features Low power 9 ma max. commercial (1 ns) 13 ma max. commercial (5 ns) CMO Flash