TA1303AFN TENTATIVE TA1303AFN MIXER / OSCILLATOR BUILT-IN FREQUENCY SYNTHESIZER FOR VHF, CATV AND UHF BAND.

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1 TENTATIVE TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC TA1303AFN MIXER / OSCILLATOR BUILT-IN FREQUENCY SYNTHESIZER FOR VHF, CATV AND UHF BAND. The TA1303AFN is a single chip which integrates a PLL and a MIX OSC for VHF, CATV and UHF band. The control data conforms to 3-wire bus and I 2 C bus formats. Bus-SW can be used to easily switch for easy tuner system set-up. Flat, compact package: SSOP30 (0.65 mm pitch) FEATURES MIX OSC block VHF CATV bands: Mixer and Oscillator UHF bands: Mixer and Oscillator Built-in IF amplifier Single IF output terminal Weight: 0.17g (Typ.) PLL block Standard bi-directional I 2 C bus format control 3-wire bus format control 18-bit and 19-bit automatical discrimination circuit (when 3-wire bus selected) Tuning amplifier 4-bit bandswitch drive transistor 5-levels A / D convertor (when I 2 C bus selected) Frequency step: khz, 50 khz and 62.5 khz (at 4 MHz X tal used) 4 programmable chip addresses (when I 2 C bus selected) Power on reset circuit 1 / 4 prescaler Note: These devices are easy to be damaged by high static voltage or electric fields. In regard to this, please handle with care. To input summary items. 1

2 BLOCK DIAGRAM 2

3 TERMINAL FUNCTION PIN No. PIN NAME FUNCTION INTERFACE 3-wire bus : clock data input 1 CL / SCL I 2 C bus : serial clock data input Please refer the description (Table. 1) on page wire bus :data input 2 DA / SDA I 2 C bus :serial data input /output Please refer the description (Table. 1) on page wire bus : enable data input 3 EN / ADR I 2 C : address select input Please refer the description (Table. 1) on page V CC3 This is power supply pin for Band circuits. This can use, from 5 V to 9 V Band1~Band4 Output can be controlled by setting the band switch data. U / V band can be switched by setting the band switch data. Please refer the description (Table. 5) on page 21. 3

4 PIN No. PIN NAME FUNCTION INTERFACE 8 9 MIX Output The output terminal of MIXER. For tuning, connect a tank circuit between pins 8 and V CC1 This is power supply pin for analog circuit. A changeover switch of control data. 11 BUS-SW 3-wine bus and standard I 2 C bus are switches by the voltage applied on this pin. Please refer the description (Table. 1, 2) on page 13 and GND1 This is the ground pin for analog circuit. 13 VHF Input VHF-RF input UHF Input UHF-RF input. It is possible to input either balanced or unbalanced circuit VHF Oscillator VHF oscillator pins. In case of production abnormal oscillation, connect a resistor between pin 18 and the external capacitor. 17 GND2 This is the ground pin for analog circuit. 4

5 PIN No. PIN NAME FUNCTION INTERFACE UHF Oscillator UHF oscillator pins. They are colpitts oscillator. 23 GND2 This is the ground pin for digital circuit. 24 IF Output Output terminal of IF signal which output impedance, 75 Ω 25 V CC2 This is power supply pin for digital circuit. 26 X tal Crystal oscillator input. At this block, the reference signal is generated. 27 Charge Pump Output Tuning voltage output terminal. This LSI has a built-in tuning amplifier. 28 NF 5

6 PIN No. PIN NAME FUNCTION INTERFACE At 3 wire bus mode : this functions as lock detector. If the PLL has locked, the output becomes low. 29 ADC / LOCK At I 2 C bus mode : this functions as terminal of AD convertor. This converts the input voltages into proper digital data. Please refer the description (Table. 6) on page 21. MAXIMUM RATINGS (Ta = 25 C) MIX OSC Block PLL Block Power Dissipation CHARACTERISTIC SYMBOL RATING UNIT V CC1 6 V f IN 120 dbµv V CC2 6 V V CC3 12 V VBT 38 V PD 780 [IC only] (Note) Operating Temperature T opr 20 ~85 C Storage Temperature T stg 55 ~150 C mw Note: When using the device at above Ta = 25C, decrease the power dissipation by 6.3 mw for each increase of 1 C. RECOMMENDED OPERATING CONDITION PIN No. SYMBOL MIN TYP. MAX UNIT 10 MIX OSC block V CC V 25 PLL block V CC V 30 V CC3 V CC2 9.9 V 6

7 ELECTRICAL CHARACTERISTICS PC CHARACTERISTICS (Unless otherwise specified, V CC1 = 5 V, V CC2 = 5 V, V CC3 = 9 V, Ta = 25C ) CHARACTERISTIC Power Supply and Current 1 SYMBOL TEST CIR- CUIT BAND TEST CONDITION MIN TYP. MAX UNIT I CC1-1 VHF I CC1-2 UHF Power Supply and Current 2 I CC Power Supply and Current 3 I CC3-1 I CC3-2 1 Band switch : 1 Band ON IBD = 30 ma (LOAD) Band switch : 2 Band ON IBD = 40 ma (TOTAL LOAD) ma 7

8 ELECTRICAL CHARACTERISTICS MIX OSC block (Unless otherwise specified, V CC1 = 5 V, V CC2 = 5 V, V CC3 = 9 V, Ta = 25C ) CHARACTERISTIC SYMBOL TEST CIR- CUIT BAND TEST CONDITION (*) MIN TYP. MAX UNIT Conversion Gain Noise Figure IF Out Power Level Conversion Gain Shift Frequency Shift (The PLL is not operating) Switching On Drift (The PLL is not operating) 1% Cross Modulation 3rd Inter Modulation 6-ch Beat Prescaler Beat (*) IF : MHz (Note 1) (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) (Note 7) (Note 8) (Note 9) (Note 10) VHF f RF = MHz CG 3 VHF f RF = MHz db UHF f RF = MHz UHF f RF = MHz VHF f RF = MHz NF 3 VHF f RF = MHz db UHF f RF = MHz UHF f RF = MHz VHF f RF = MHz IFp 3 VHF f RF = MHz dbmw UHF frf = MHz UHF f RF = MHz VHF f RF = MHz ±0.5 CGs 3 VHF f RF = MHz ±0.5 db UHF f RF = MHz ±0.5 UHF f RF = MHz ±0.5 VHF f osc = 101 MHz ±100 fb 3 VHF f osc = 413 MHz ±150 khz UHF f osc = 419 MHz ±150 UHF f osc = 847 MHz ±150 VHF f osc = 101 MHz ±100 fs 3 VHF f osc = 413 MHz ±200 khz UHF f osc = 419 MHz ±150 UHF f osc = 847 MHz ±200 VHF f D = MHz CM 3 VHF f D = MHz dbµv UHF f D = MHz UHF f D = MHz VHF f D = MHz IM3 3 VHF f D = MHz DB UHF f D = MHz UHF f D = MHz B6 3 VHF f p = MHz f s = MHz DB f osc = 167 MHz (A-ch), 173 MHz(B-ch), Bpre 3 VHF 179 MHz(C-ch), dbµv 185 MHz (D-ch) 8

9 PLL block (Unless otherwise specified, V CC1 = 5 V, V CC2 = 5 V, V CC3 = 9 V, Ta = 25C ) CHARACTERISTIC SYMBOL TEST CIR- CUIT TEST CONDITION MIN TYP. MAX UNIT Bandswitch Drive Current IBD 1 Maximum drive current / 1 port 30 ma Bandswitch Drive Maximum LOAD IBD MAX 1 Maximum total drive current 50 ma Bandswitch Drive Voltage Drop Tuning Amplifier Output Voltage (Close Loop) Tuning Amplifier Maximum Current VBD Sat 1 IBD = 30 ma V Vt Out V BT = 33 V, RL = 33 [kω] V IVt V BT = 33 V 3 ma X tal Negative Resistance XtR kω X tal Operating Range OSC f in MHz X tal External Input evel OSC in mv p-p Lock Output Low Voltage VLKL 1 (Lock mode, 3-wire bus mode) 0.4 V Lock Output High Voltage VLKH 1 Logic Input Low Voltage Logic Input High Voltage Logic Input Current (Low) IBsL 1 Logic Input Current (High) IBsH 1 (Unlock mode, 3-wire bus mode) 4.6 V VBsL 1 Pins 1 to V VBsH 1 Pins 1 to 3 3 V CC Pin Pin Pin 1, Pin Pin Bus-SW Low Input Voltage VBIL V Bus-SW High Input Vlotage VBIH V CC2 Bus-SW Low Current (Low) IBIL µa Bus-SW Low Current (High) IBIH µa Charge Pump Output Current Ichg 1 CP= [0] ±30 ±60 ±90 CP= [1] ±140 ±280 ±420 ACK Output Voltage V ACK 1 I SINK = 3 ma (l 2 C-bus mode) 0.4 V V µa µa 9

10 CHARACTERISTIC SYMBOL TEST CIR- CUIT TEST CONDITION MIN TYP. MAX UNIT Set-up Time T s 2 Enable Hold Time T sl 2 Next Enable Stop Time T NE (3-wire bus mode) 6 Next Clock Stop Time T NC Refer to data timing chart 6 Clock Width T c 2 Enable Set-up Time T L 10 Data Hold Time T H 2 SCL Clock Frequency f SCL khz Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition t BUF 4.7 t HD;STA 4.0 Low Period of the SCL Clock t LOW 4.7 High Period of the SCL Clock t HIGH 4.0 Set-up Time for a Repeated START Condition (I 2 C bus mode) t SU;STA Refer to data timing chart 4.7 Data Hold Time t HD;DAT 0 Data Set-up Time t SU;DAT 250 Rise Time of both SDA and SCL Signals Fall Time of both SDA and SCL Signals Set-up Time for STOP Condition t R t F t SU;STO µs µs ns 4.0 µs 10

11 Fig.1 3-wire bus data timing chart (Falling edge timing) Fig.2 I 2 C bus data timing chart (Rising edge timing) REFERENCE DATA (V CC1 = 5 V, V CC2 = 5 V, V CC3 = 9 V, Ta = 25C ) CHARACTERISTIC SYMBOL TEST CIR- CUIT BAND TEST CONDITION MIN TYP. MAX UNIT Lock Up Time Lupt 3 Reference Leak Suppression Level fref S / I 3 VHF f osc = 101 MHz f osc = 173 MHz 40 VHF f osc = 179 MHz f osc = 413 MHz 60 UHF fosc = 419 MHz f osc = 847 MHz 30 VHF f RF = MHz ( 30 dbmw input) (CP = [1], fref = khz) 65 VHF f RF = MHz ( 30 dbmw input) (CP = [1], fref = khz) 60 UHF f RF = MHz ( 30 dbmw input) (CP = [1], fref = khz) 48 UHF f RF = MHz ( 30 dbmw input) (CP = [1], fref = khz) 53 ms db Local Oscillator Leak Level (To IF Output) [Worst Case] LOIF 3 VHF f osc = 101 MHz~f osc = 173 MHz 36 VHF f osc = 179 MHz~f osc = 413 MHz 36 UHF f osc = 419 MHz~f osc = 847 MHz 28 dbmw 11

12 TEST CONDITIONS Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Conversion Gain f RF input level = 30 dbmw Noise Figure Noise Figure meter used. IF Out Power Level Measure IF output level when it is maximum level. Conversion Gain Shift The Conversion gain shift is defined as a change in conversion gain when supply voltage varies from V CC = 5 to 4.5 V or from V CC = 5 to 5.5 V. Frequency Shift (The PLL is not operating) The frequency shift is defined as a change in oscillator frequency when supply voltage varies from V CC = 5 to 4.5 V or from V CC = 5 to 5.5 V. Switching On Drift (The PLL is not operating) Measure frequency change from 2 seconds after switching on to 3 minutes. 1% Cross Modulation fd = fp (fdrf input level = 30 dbmw) fud = fp + 12 MHz 100 khz, 30%AM Input two signals, and increase the fud RF input level. Measure the fud RF input level when the suppression level reaches 56.5 db. 3rd Inter Modulation fd = fp (fd RF input level = 30 dbmw) fud = fp + 1 MHz (fud RF input level = 30 dbmw) Input two signals, measure the suppression level. 6-ch Beat fp = MHz (fp RF input level = 30 dbmw) fs = MHz (fs RF input level = 30 dbmw) Input two signals, measure the suppression level IF output signal between below signals. fudif1 = (fp + fs) fosc = ( ) 129 = 42 MHz fudif2 = (2 fs) fosc = ( ) 129 = 46.5 MHz Prescaler Beat 1 / 4 fosc (A-ch) = 1 / = MHz 1 / 4 fosc (B-ch) = 1 / = MHz 1 / 4 fosc (C-ch) = 1 / = MHz 1 / 4 fosc (D-ch) = 1 / = MHz As for each channel, measure the level to IF output. 12

13 PLL BLOCK Operation description TA1303AFN can be controlled with either by 3-wire bus or standard I 2 C bus. The 3-wire bus mode is eqvipped with an 18-bit / 19-bit automatic selection circuit. Frequency steps can be switched, depending on the voltage applied to the BUS-SW pin. The I 2 C bus conforms to the standard I 2 C bus format. The bus supports two-way bus communications control, consisting of WRITE mode where data are received and READ mode where data are transmitted. In READ mode, the voltage applied on the A / D converter input pin can be transmitted and output with 5-level resolution. (This function is only valid when the I 2 C bus is selected. When the 3-wire bus is selected, the A / D converter input pin functions as the Lock output pin.) Addresses can be set using the hardware bits. 4 programmable addresses are supported. 3-wire bus and standard I 2 C bus are switched by the voltage applied on the BUS-SW pin. The power-on reset circuit is built in this product, and the detection voltage is designed about 1.4 V. If it raises to voltage of operation after making it stop for a while near the voltage of a power-on reset circuit of operation at the time of starting of a power supply, a power-on reset circuit may not operate normally. Function chart Table. 1 PIN NAME 3-WIRE BUS I 2 C BUS BUS-SW [OPEN] or [V CC ] [GND] CL / SCL CLOCK INPUT SCL INPUT DA / SDA DATA INPUT SDA IN / OUTPUT EN / ADR ENABLE INPUT ADDRESS Lock ADC Lock ADC 3-Wire bus communications control The 3-wire bus uses normal 18-bit and 19-bit data (band switch information and programmable divider information) and 27-bit test data (charge-pump current setting, tuning amplifier on / off, reference frequency divider ratio setting, and testing item functions) are available. The program frequency is sequentially calculated together with normal data and test data. fosc = fr 4 N fosc : Program frequency fr : Phase comparator reference frequency N : Divider ratio 13

14 (1) Normal data Depending on the voltage (OPEN, VCC) applied on the BUS-SW pin and the transfer DATA bit length, the X tal divider ratio setting, phase comparator reference frequency, and step frequency of the normal data are as shown in the table below. Normal data function table Table. 2 BUS-SW INPUT TRANSFER DATA X TAL RATIO REFERENCE FREQUENCY STEP FREQUENCY [V CC ] 18-bit Cannot be set [V CC ] 19-bit 1 / khz 50 khz [OPEN] 18-bit 1 / khz 62.5 khz [OPEN] 19-bit 1 / khz khz Note 1: The step frequency at 4 MHz (X tal used) Note 2: During OPEN, automatically set with transmitted bit length (18 19 possible) Fig.3 Normal data format (18-bit transmission) Fig.4 Normal data format (19-bit transmission) 14

15 a) 18-bit DATA TRANSMISSION : During a high level of the enable signal, the data is clocked into the register on the falling edge of the clock. Data are latched under the condition that the number of clocks while the enable signal is high is 18bits (the number of clock rising edges is 18). Data are latched on the falling edge of the enable signal. At 18-bit data transfer, N14 of the program divider is always automatically set to [0]; the phase comparator reference frequency divider ratio is set to 1 / 256. Please refer the description (Fig1. 3-wire bus data timing chart) on page 11. b) 19-bit DATA TRANSMISSION : During a high level of the enable signal, the data is clocked into register on the falling edge on the clock. Data are latched under the condition that the number of clocks while the enable signal is high is 19bits (the number of clock rising edges is 19). Data are latched on the falling edge of the enable signal. At 19-bit data transfer, depending on the BUS-SW, the phase comparator reference frequency divider ratio is set to either 1 / 320 or 1 / 512. Please refer the description (Fig1. 3-wire bus data timing chart) on page

16 (2) TEST MODE In the test mode, the settings can be changed and the function can be checked. Change from the normal mode to the test mode with a 27-bit or more of clocks and data transmission during a high level of the enable signal. The data are latched at the 27th falling edge of the clock signal, validating the previous 27-bit data. The latch timing is the same as normal data. The 4-bit bandswitch data and the programmable divider data are latched at the 20th bit rising edge of the clock signal, and the data is updated. The test data are latched at the 27th bit falling edge of the clock signal, and the data is updated. When the mode is changed from test to normal, RSa changes depending on the data bit length (18 or 19 bits, automatic discrim ination). The data set in RSb in test mode are retained (see the table below). REFERENCE FREQUENCY DIVIDER RATIO SETTING TEST MODE 1 / / / 512 DATA TRANSMISSION LENGTH SET REFERENCE FREQUENCY DIVIDER RATIO 18-bit 1 / bit 1 / bit 1 / bit 1 / bit 1 / bit 1 / 512 *: The data timing is the same as normal data. Fig.5 Test data format 16

17 TEST DATA SPECIFICATIONS B4 ~1 : Band drive data [0] : OFF [1] : ON When band drive data is [1] either Band 1 or Band 2, VHF mode. When band drive data is [0] both Band 1 and Band 2, UHF mode. N14 ~N0 : Programmable counter data CP : Charge-pump output current [0] : ±60 µa (Typ.) [1] : ±280 µa (Typ.) T2, T1, T0 : Test bits T2, T1, T0 : Test mode setting CHARACTERISTIC T 2 T 1 T 0 REMARKS Normal Operation OFF 0 1 Charge pump is OFF (Check output : NF) Charge-Pump Sink Only charge pump Sink current is ON (Check output : NF) Source Only charge pump Source current is ON (Check output : NF) Reference Signal Output Reference signal output : Lock 1 / 2 Counter Divider Output / 2 counter output : Lock Phase Comparator Test Comparative signal input : DA Reference signal input : CL (Check output : NF) : Don t Care Note: When testing the counter divider output, programmable counter data input is necessary. Rsa, Rsb : Reference frequency divider ratio select bit. RSa, RSb : X tal reference frequency divider ratio select bits. DIVIDER RATIO RSa RSb 1 / / / : Don t Care Note: When the mode is changed from test to normal, RSa changes depending on the data bit length (18 or 19 bits, automatic discrimination). The data set in RSb in test mode are retained. OS : Tuning amplifier control bit [0] : Tuning amp ON (Normal operation) [1] : Tuning amp OFF (High impedance) : Don t Care 17

18 I 2 C Bus communications control The TA1303AFN conforms to standard I 2 C bus format. The I 2 C bus mode enables two-way bus communications with the WRITE mode, which receives data, and READ mode, which status data. WRITE and READ modes are set using the last bit (R / W bit) of the address byte. If the last address bit is set to [0], WRITE mode is set ; if set to [1], READ mode is set. Addresses can be set using the hardware bits. 4 programmable addresses can be programmed. With this setting, multiple frequency synthesizers can be used in the same I 2 C bus line. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR : Pin 3). An address is selected according to the set bits. When the correct address byte is received, during acknowledgment, serial data (SDA) line is Low. If WRITE mode is set at this time, when the data byte is programmed, the serial data (SDA) line is Low during the next acknowledgment. Please refer the description (Fig2. I 2 C bus data timing chart) on page 11. (1) WRITE mode (setting command) When WRITE mode is segment, byte 1 segment the address data ; bytes 2 and 3 segment the frequency data ; byte 4 segment the divider ratio setting and function setting data ; and byte 5 segment the output port data. Data are latched and transferred at the end of, byte 3, byte 4, and byte 5. Bytes 2 and 3 are latched and transferred is done with a two byte set (byte 2 + byte 3). Once a correct address is received and acknowledged, the data type is determined according to[0]or[1]set in the first bit of the next byte. That is, if the first bit is [0], the data are frequency data ; if [1], function setting or output port data. Until the I 2 C bus STOP CONDITION is detected, the additional data can be input without transmitting the address again. (EX : Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid. Byte 1 can set the hardware bit with address data. The hardware bit is set with voltage applied to the address setting pin (ADR : Pin 3). 18

19 Bytes 2 and 3 are stored in the 15-bit shift register with counter data for the frequency setting, and control the 15-bit programmable counter ratio. The Lock frequency can be calculated in the following formula : fosc = fr 4 N fosc : Program frequency fr : Phase comparator reference frequency (Step frequency) N : Counter total ratio fr is calculated using the crystal oscillator frequency and the reference frequency divider ratio set in byte 4 (control byte). (fr = X tal oscillator frequency / reference frequency divider ratio) The reference frequency divider ratio can be set to, 1 / 256, 1 / 512, and 1 / 320. When using a 4MHz crystal oscillator, fr = khz, khz, and 12.5 khz. The step frequency are 62.5 khz, khz, and 50 khz. Byte 4 is a control byte used to set functions. Bit 2 (CP) controls the output current of the charge-pump circuit. When bit 2 is set to [0], the output current is set to ±60 µa ; when set to [1], ±280 µa. Bit 3 (T2), bit 4 (T1) and bit 5 (T0) are used to set the test mode. They are used to set the charge-pump test, phase comparator reference signal output, and counter divider 1 / 2 output. Please refer the description (Table. 3) on page 21. Bit 6 (Rsa) and bit 7 (Rsb) are used to set the X tal reference frequency divider ratios. Please refer the description (Table. 4) on page 21. Bit 8 (OS) is used to set the charge-pump drive amplifier output setting. When bit 8 is set to [0], the output is ON (Normal use) ; when set to [1]the output is OFF (High impedance). Byte 5 is used to set and control the output port (Bands 1~4). Select [0]for OFF, and [1]for ON. Please refer the description (Table. 5) on page 21. When band switch data is [1]either Band 1 or Band 2, VHF mode. When band switch data is [0]both Band 1 and Band 2, UHF mode. Two output ports can be operation turned on, but be sure to keep the total output current under 50 ma. (2) READ mode (status request) When READ mode is set, power-on reset operation status, phase comparator lock detector output status, and 5-level A / D converter pin input voltage status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply of VCC2 stops, bit 1 is set to [1]. The conditions for reset to [0] voltage supplied to VCC2 is 3 V or higher, transmission is requested in READ mode, and the status is output. (When VCC2 is turned on, bit 1 is also set to [1]) Bit 2 (FL) indicates the phase comparator lock status. When locked, [1] is output ; when unlocked, [0] is output. Bits 6, 7, and 8 (A2, A1, A0) indicate the 5-level A / D converter status. The voltage applied to the A / D converter input pin (pin 29) is output through a 5-level resolution. Please refer the description (Table. 6) on page 21. (EX : The AFT output voltage data can be given to the master device.) 19

20 DATA FORMAT a) WRITE MODE BYTE MSB LSB 1 Address Byte MA1 MA0 R / W=0 ACK 2 Divider Byte 1) 0 N14 N13 N12 N11 N10 N9 N8 ACK 3 Divider Byte 2) N7 N6 N5 N4 N3 N2 N1 N0 ACK(L) 4 Control Byte 1 CP T2 T1 T0 RSa RSb OS ACK(L) 5 Band SW Byte B4 B3 B2 B1 ACK(L) : DON T Care ACK : Acknowledged (L) : Latch and transfer timing b) READ MODE BYTE MSB LSB 1 Address Byte MA1 MA0 R / W=1 ACK 2 Status Byte POR FL A2 A1 A0 : DON T Care ACK : Acknowledged DATE SPECIFICATIONS MA1, MA0 : Programmable hardware address bits ADDRESS PIN APPLIED VOLTAGE MA1 MA0 0 ~0.1 V CC2 0 0 OPEN or 0.2 V CC2 ~ 0.3 V CC V CC2 ~ 0.6 V CC V CC2 ~ V CC2 1 1 N14 ~ N0 CP : Programmable counter data : Charge-pump output current setting [0] : ±60 µa (Typ.) [1] : ±280 µa (Typ.) 20

21 Table. 3 T2, T1, T0 : Test mode setting CHARACTERISTIC T 2 T 1 T 0 REMARKS Normal Operation Charge-Pump OFF 0 1 Charge-pump is OFF (Check output : NF) Sink Only charge-pump Sink current is ON (Check output : NF) Source Only charge-pump Source current is ON (Check output : NF) Reference Signal Output Reference signal output : ADC 1 / 2 Counter Divider Output / 2 counter divider output : ADC Phase Comparator Test Comparative signal input : SDA Reference signal input : SCL (Check output : NF) : DON T Care Note: Table. 4 When testing the counter divider output, programmable counter data input is necessary. RSa, RSb : X tal reference frequency divider ratio select bits. RSa RSb DIVIDER RATIO / / / 320 OS Table. 5 : DON T Care : Tuning amplifier control setting. [0] : Tuning amplifier ON (Normal operation) [1] : Tuning amplifier OFF (High impedance) B4 ~ B1 : BAND switch data [0] : OFF When band drive data is [1] either Band1 or Band2, VHF mode. [1] : ON When band drive data is [0] both Band1 and Band2, UHF mode. POR : Power-on reset flag [0] : Normal operation [1] : Reset operation FL : Lock detect flag [0] : Unlocked [1] : Locked A2, A1, A0 : 5-level A / D converter status. Table. 6 ADC PIN APPLIED VOLTAGE A 2 A 1 A V CC2 ~ V CC V CC2 ~ 0.60 V CC V CC2 ~ 0.45 V CC V CC2 ~ 0.30 V CC ~ 0.15 V CC *: Accuracy is ± 0.03 V CC2 21

22 I 2 C BUS CONTROL SUMMARY The bus control format for TA1303AFN conforms to the Philips I 2 C bus control format. (1) Start / stop conditions (2) Bit transfer (3) Acknowledge (4) Slave addresses A 6 A 5 A 4 A 3 A 2 A 1 A 0 R / W * * 0 Purchase of TOSHIBA I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specification as defined by Philips 22

23 TEST CIRCUIT 1 TEST CIRCUIT 2 X tal external input measurement 23

24 TEST CIRCUIT 3 LINE DIAMETER TURN DIAMETER NUMBER OF TURNS L1 0.3 mm 2.0 mm 7.5 T L2 0.3 mm 2.0 mm 2.5 T L3 0.3 mm 2.5 mm 2.5 T Band1/Band2=VHF-L or VHF-H Band3/Band4=UHF-L or FMT L4 : 0.9 µh ± 5% 24

25 [REFERENCE DATA] X tal External Input Level If it uses not only TEST CIRCUIT 2 but Fig.6, please refers to Graph 1. Fig.6 X tal External Input Reference Application 25

26 PACKAGE DIMENSIONS Weight: 0.17 g (Typ.) 26

27 RESTRICTIONS ON PRODUCT USE EBA TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Handbook etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( Unintended Usage ). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer s own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. 27