D6.3: Evaluation of the 2nd generation 2x2 PLATON optical interconnect router
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1 ICT - Information and Communication Technologies Merging Plasmonics and Silicon Photonics Technology towards Tb/s routing in optical interconnects Collaborative Project Grant Agreement Number D6.3: Evaluation of the 2nd generation 2x2 PLATON optical interconnect router Revision: Final Due Date of Deliverable: 30/06/2013 Actual Submission Date: 06/10/2013 Start date of project: January 1 st 2010 Duration: 42 months Organization name of lead contractor for this deliverable: ICCS/NTUA Authors: Dimitris Kalavrouziotis (ICCS/NTUA), Giannis Giannoulis (ICCS/NTUA), Dimitrios Apostolopoulos (ICCS/NTUA), Konstantinos Vyrsokinos (CERTH), Nikos Pleros (CERTH) November 18, 2013 FP The PLATON Consortium Page 1 of 27
2 Project Information PROJECT Project name: Project acronym: Project start date: Project duration: Contract number: Project coordinator: Instrument: Activity: Merging Plasmonic and Silicon Photonics Technology towards Tb/s routing in optical interconnects PLATON 01/01/ months Nikos Pleros CERTH STREP THEME CHALLENGE 3: Components, Systems, Engineering DOCUMENT Document title: Document type: Deliverable number: Contractual date of delivery: Calendar date of delivery: Editor: Authors: Workpackage number: Workpackage title: Evaluation of the 2nd generation 2x2 PLATON optical interconnect router Report D6.3 30/06/ /10/2013 Dimitris Kalavrouziotis Dimitris Apostolopoulos, Giannis Giannoulis, Konstantinos Vyrsokinos, Nikos Pleros WP6 Evaluation of the 4x4 PLATON optical interconnect router Lead partner: Dissemination level: Date created: ICCS/NTUA PU 26/09/2013 Updated: Version: Total number of Pages: Document status: Final 27 final November 18, 2013 FP The PLATON Consortium Page 2 of 27
3 TABLE OF CONTENTS 1 EXECUTIVE SUMMARY INTRODUCTION PURPOSE OF THIS DOCUMENT DOCUMENT STRUCTURE AUDIENCE OVERVIEW OF PLATON 2X2 ROUTER CONCEPT EXPERIMENTAL EVALUATION OF PLA20 2X2 ROUTER OPTICAL CHARACTERIZATION BEFORE PLASMONIC DEPOSITION... 8 Cutback Section Characterization SOI Multiplexer Static Characterization OPTICAL CHARACTERIZATION AFTER PLASMONIC DEPOSITION CHARACTERIZATION OF THE PACKAGED ROUTER... ERROR! BOOKMARK NOT DEFINED. 5 EXPERIMENTAL EVALUATION OF THE PLA22 A MZI STATIC OPTICAL CHARACTERIZATION Chip PLA22 WC Chip PLA22 WC Chip PLA22 WC STATIC THERMO OPTIC CHARACTERIZATION Chip PLA 22 WC Chip PLA 22 WC Chip PLA 22 WC CONCLUSIONS November 18, 2013 FP The PLATON Consortium Page 3 of 27
4 1 Executive Summary This document provides details about the experimental evaluation of the PLA20 and the PLA22 chips that incorporate a complete 2x2 router and a hybrid Si-DLSPP A-MZI, respectively. The decision about reallocating the resources originally planned for the development of the 4x4 router was received after the experimental evaluation of the PLA19 chips (first fabrication run of 2x2 router) that revealed very high losses of more than 60dB between the input and output port. The identification of the cause that induced the high losses (see D6.1 for more details) led the consortium to proceed to another fabrication run of the 2x2 router with the optimized process, called PLA20. The option of applying this process for the first time at the 4x4 router was considered too risky, especially without any feedback fromany successful 2x2 router. A series of PLA20 2x2 routers was fabricated by AMO and UB with three of them being sent to IZM for packaging. Additionally to the 2x2 routers, three chips incorporating only one Si-DLSPP A-MZI were fabricated in order to serve as the backup plan in case no complete 2x2 router would operate successfully. This back-up plan involved the external interconnection via fibers of the SOI-MUX devices employed in the PLA20 2x2 router chips and the PLA22 A-MZZI chips, so as to demonstrate Siplasmonic routing functionality even if not all the elements are encompassed on the same chip. November 18, 2013 FP The PLATON Consortium Page 4 of 27
5 2 Introduction 2.1 Purpose of this document The objective of this deliverable is to report on the performance of the unpackaged PLA20 and PLA22 chips, which include the complete re-designed 2x2 router and the hybrid Cyclomer-loaded SPP A-MZI switch, respectively. 2.2 Document structure The present deliverable is split into two major chapters: - Optical performance evaluation of the PLA20 2x2 routers - Optical performance evaluation and static thermo-optic characterization of the PLA22 A-MZI 2.3 Audience This document is public. November 18, 2013 FP The PLATON Consortium Page 5 of 27
6 3 Overview of PLATON 2x2 router concept Figure 3-1: PLATON s 2x2 router block diagram Figure 3-1 shows the block diagram of the PLATON 2x2. Routing platform operates with optical data line-rates of 40Gb/s and reside on a Silicon-on-Insulator Motherboard that hosts all the heterogeneous technologies, namely SOI-based components, Dielectric Loaded Surface Plasmon Polariton (DLSPP) switches, Photodiodes and Integrated Circuit Microcontrollers. The 2x2 router offers an aggregate switching throughput of 560 Gb/s. Briefly the role of each router sub-unit is as follows: 1. 7x1 SOI MUX (Multiplexer): This subsystem is used to multiplex the 7 incoming 40Gb/s data traffic carrying wavelengths into a common, single optical traffic stream that is considered to follow the same route throughout the network. Two 7x1 SOI multiplexers will be employed in the 2x2 PLATON. The SOI MUX will rely on silicon-based photonic integration technologies. 2. PD O/E Conversion Stage: Photodiodes integrated on the SOI motherboard will form the O/E conversion stage of the routing platform. PDs will be used for converting the optical header information into respective electrical header pulses to be subsequently processed by the IC Header Processing and Control Circuit. One PD will be employed for every header wavelength, which in turn implies that in the case of the 2x2 router a total number of 2 PDs will be used. 3. IC Header Processing and Control Circuit: This subsystem is used for processing the incoming header information and generating the proper electrical control signals to drive the DLSPP switching matrix. For the 2x2 router, the IC circuit will have two input ports for receiving the respective electrical header pulse streams and will provide two electrical output signals for controlling the state of the 2x2 switching matrix. 4. DLSPP switching matrix: The DLSPP switching matrix routes the incoming traffic streams towards the different outputs depending on the header information. PLATON s switching matrix will comprise Dielectric Loaded Surface Plasmon Polariton (DLSPP)- based thermo-optic switching elements. A 2x2 switching matrix will be used for the 2x2 routing platform. A schematic representation of these building blocks and their positioning on the SOI motherboard is provided in Figure 3-2. November 18, 2013 FP The PLATON Consortium Page 6 of 27
7 Figure 3-2: PLATON s SOI motherboard and its various building blocks November 18, 2013 FP The PLATON Consortium Page 7 of 27
8 D6.3 Evaluation of the 4x4 PLATON optical interconnect router 4 Experimental Evaluation of PLA20 2x2 router 4.1 Optical Characterization before plasmonic deposition Figure 1 (a) presents the mask layout of the PLA20 chip prior the deposition of the plasmonic waveguides. The structure of the chip is identical to PLA19 that was extensively described in D6.1, except from the thickness of the Spin-on-Glass (SOG) that is placed between the photonic/plasmonic waveguides and the metallization layer. In the PLA20 chip the SOG layer thickness has been increased to 850nm so as to minimize the metal induced losses. Figure 1: (a) Mask layout of the PLA 20 chip before the plasmonic deposition, (b) impression of the real PLA 20 chip, (c) SOI cavity and (d) SOI multiplexer (front-end of the chip) As it can be seen in the figure of the chip the optical I/O connectivity is realized by an array of grating couplers whereas the electrical control or bias signals can be applied through the contact/bonding pads that are connected to the electrical circuitry of the PLA20 chip. The chip is also equipped with a cutback section including 8 waveguides of various lengths that will be utilized for extracting the propagation and coupling losses, evaluating, this way, the quality of the overall fabrication process. Figure 1 (b) shows an impression of the fabricated chip during the characterization process in NTUA s premises while inset (c) depicts the SOI chip cavities that will host the gold layer and the plasmonic waveguides. November 18, 2013 FP The PLATON Consortium Page 8 of 27
9 - Silicon-on-Insulator Multiplexers The front end of the chip is an optical multiplexing circuitry comprising cascaded 2nd order SOI waveguide ring resonators (WRRs) that enable the multiplexing of 100 GHz spaced 40 Gb/s channels into a common waveguide. The generic 8:1 SOI MUX design employs two different radii clusters (R1 and R2), with each cluster having four 2nd order thermo-optically tunable ring structures of the same radius (Figure 2). This configuration meets AMO's fabrication limit to single lines (50nm in resist) and can perform successfully for a thermo-optically induced wavelength tuning of less than 3 nm (see D2.2). Besides, it can fulfill PLATON s signal specifications, namely the 100 GHz channel (resonance) spacing and the 0.32 nm (40 GHz) 3-dB bandwidth of each resonant peak. Figure 2: Schematic of the 8:1 SOI multiplexer It should be noted that the initially targeted 4x4 PLATON router would require four different spectral bands within the nm wavelength window and this specification could be achieved by choosing different combinations for the ring radii and the straight waveguides. To this end, the consortium exploited results from the already tested SOI MUX structures so as to generate the following table describing four different MUX designs that satisfy the aforementioned condition. The PLA20 2x2 router chip however needs only two SOI multiplexers as it has two multi-wavelength inputs. Therefore, the current 2x2 PLA20 chip relies only on the third and fourth MUX designs. Table 1: SOI multiplexer designs November 18, 2013 FP The PLATON Consortium Page 9 of 27
10 The thermo-optic tuning of the ring resonators was enabled by applying thin resistive layers (Ti heaters) above each ring that are conductively connected to the electrical circuitry of the chip and can be heated by supplying electrical current. Cutback Section Characterization Before the evaluation of the PLA20 chip silicon functionality, the cutback section, shown in Figure 3 (a), was tested and characterized. As it was already mentioned, the section comprises 8 different silicon waveguides with lengths varying from 8500 μm to μm, equipped with grating couplers. The input and output of the waveguides are placed on opposite sides. Therefore the regular probe station configuration was used, employing two individual cleaved fibers tilted at 10 degrees. The input of the probe station was connected to a tunable laser (through a polarization controller, ensuring TM polarization) while the output power was monitored on an optical power meter. Figure 3 (b) shows the calculated Fiber-to-fiber (F-t-F) losses plotted against the waveguide length. Linear fitting reveals that both the propagation and coupling losses are quite low, 1.45 db/cm and 4.2 db /coupler respectively, while the coefficient of determination is very close to 1. These observations indicate the advanced fabrication quality of the PLA20 silicon chip. Figure 3: (a) Mask layout of the cutback section, (b) Linear fitting of the cutback measurements November 18, 2013 FP The PLATON Consortium Page 10 of 27
11 SOI Multiplexer Static Characterization Before the characterization of the PLA 20 chip, it was agreed by the consortium, not to apply electrical current on the chip so as to preserve the quality of the contact pads, facilitating the wirebonding process during the packaging of the 2x2 router chip. To this end, the evaluation of the SOI multiplexer was performed only statically, without investigating the thermo-optic functionality of the dual ring modules. Note that the adequate thermo-optic behavior of these structures has been verified and reported in D3.2. As described in the previous paragraphs, the input and output optical connections of the 2x2 router are realized through grating couplers that are placed in a 1D array arrangement. To this end, the in and out light coupling is based on the use of a V-groove assembly comprising 16 fibers placed in 250um spaced v-grooves (Figure 4 (a)) that corresponds to the pitch of the grating coupler array. The end facet of the V-groove assembly was polished at 10 degrees (top-to-bottom) so as to comply with the optimum operation angle of the grating couplers. The chip was lacking alignment grating couplers, therefore the alignment of the fiber array relied on the use of the optical path connecting the common (bus) waveguide of the SOI MUX and the 10% tap waveguide as shown in Error! Reference source not found. (b). More specifically, the ASE produced by a high power EDFA was launched into the common (bus) and the output power and spectrum was monitored at the 10% tap waveguide (monitor). Following the successful alignment, a tunable CW laser was employed so as to scan and reconstruct the spectral response of the device along the 1500 to 1580 nm spectral window. The same procedure was applied for both the upper and the lower multiplexer (MUX3 and MUX4 designs). Figure 4: (a) Photo of the characterization process and (b) SOI multiplexer and input/output optical ports Figure 5 (a) shows the normalized spectral response of the bus waveguide of MUX 3. The response is the result of the multiplication of the cascaded through ports of the dual ring resonators filtered by the spectral response of the I/O grating coupler. The transfer function of the coupler can be seen on the envelope of the overall response while the notches represent the filtering effect of the dual rings. At the left side of the graph the FSR is approximately 7nm that corresponds to 12μm ring radius. For wavelengths longer than 1535 nm, however, two notches appear and the calculation of the FSR becomes trickier. This is due to the small radius difference between the rings resonators of the first (12 μm radius) and the second (11.7 μm) cluster that leads to two slightly different overlapping FSRs. November 18, 2013 FP The PLATON Consortium Page 11 of 27
12 D6.3 Evaluation of the 4x4 PLATON optical interconnect router Figure 5: Response of the bus waveguides of SOI MUX 3 and 4 Figure 5 (b) depicts the normalized spectral response of the bus waveguide of MUX 4. The FSR at the center of the graph is approximately 9.2 nm that corresponds to 9 μm ring radius. For longer or shorter wavelengths, though, two notches appear. This is again justified by the overlap of two slightly different FSRs stemming from the difference between the ring radius of the first (9 μm) and the second (9.2 μm) clusters. It should be noted that in both cases the fiber-to-fiber losses were found to be approximately 25dB including the 10dB induced by the splitting ratio of the 90/10 monitor coupler. Figure 6 shows two indicative and normalized results regarding the spectral response of the drop port. The left graph was obtained when ASE was launched into waveguide 4 whereas the right graph was obtained when ASE was into the waveguide 8. In both cases the shape of the transfer function was quite steep while the extinction ratio was more than 25 db revealing the advanced filtering/multiplexing quality of the dual ring modules. As mentioned earlier, waveguides 1-4 employ 12 μm radius ring resonators whereas waveguides 5-8 employ 11.7 μm radius. Therefore, the FSRs measured for the two graphs are 7 nm and 7.2 nm respectively. Figure 6: Spectral response of the waveguide 4 and 8 November 18, 2013 FP The PLATON Consortium Page 12 of 27
13 4.2 Optical Characterization after plasmonic deposition Figure 7 (a) shows the mask layout 2x2 PLA20 platon router chip after the plasmonic deposition. The plasmonic waveguides were deposited in the respective SOI cavities as was described in the previous paragraph. The structured gold layer inside the cavity, the plasmonic waveguide as well as the gold contact pads are shown in inset (b), while inset (c) depicts again the already described front-end of the 2x2 router chip. Figure 7: (a) Mask layout of the PLA 20 chip after the plasmonic deposition, (b) Gold layer and plasmonic waveguide deposited in the SOI cavity and (c) SOI multiplexer The main targets of this characterization are: - To identify any detrimental effect of the plasmonic deposition processing on the quality of the silicon waveguides and circuitry - To measure and evaluate the fabrication quality of the plasmonic part, in terms of propagation losses and effective coupling to the silicon waveguides. The first target could be achieved by evaluating the performance of the cutback section and the SOI multiplexers after the plasmonic processing and compare the results to the ones that were presented in the previous paragraph. To this end, the cutback waveguides were again characterized and the measured fiber-to-fiber are plotted against waveguide length in the following graph (Figure 8). November 18, 2013 FP The PLATON Consortium Page 13 of 27
14 Figure 8: Linear fitting of the cutback section Linear fitting reveals that the calculated propagation losses are 3.4 db/cm and the coupling losses are approximately 3.7 db/coupler. Comparing to the previously obtained results, it seems that the propagation losses have been increased after the plasmonic processing while the coupling losses have been decreased. This, however, is quite unlike to be true, since it is impossible to achieve improvement of the silicon grating coupler quality during the plasmonic processing. The answer to this issue is given by the coefficient of determination that is quite lower compared to the previous measurements, meaning that the f-t-f losses plotted against waveguide length, do not fully exhibit linear behavior, hindering the correct extraction of the propagation and coupling losses. This leads to the conclusion that the plasmonic processing affected the quality of the silicon waveguides in an inconsistent manner, probably depending on the location of each waveguide on the chip. In any case, though, the influence on the waveguide performance is minor, resulting to only marginal deterioration of the chip s optical functionality. Figure 9 shows the normalized spectral responses of the MUX3 and MUX4 bus waveguides. The graphs are quite similar to the spectral responses presented in Figure 6, exhibiting the same envelope as well as identical FSR values. Only minor differences are noticed mainly related to the Figure 9: Spectral response of the bus waveguide of (a) MUX 3 and (b) MUX 4 November 18, 2013 FP The PLATON Consortium Page 14 of 27
15 tuning capabilities and step accuracy (it directly affects the correct sampling and representation of the notches) of the tunable laser that was employed during the characterization. This leads seamlessly to the conclusion that the overall optical functionality of the SOI multiplexers was not affected during the processing for the deposition of the plasmonic waveguides. Having verified the adequate operation of the silicon waveguides and circuitry after the plasmonic processing, the next step of the characterization was the static evaluation of the plasmonic section. To this end, the output of a tunable CW laser was launched in the BUS waveguide of MUX 3 and MUX 4 and the output power at the BAR and CROSS output ports was measured. According to the previously obtained results the output of the plasmonic MZI should include the transfer functions shown in Figure 9, decreased by the amount of plasmonic propagation and coupling losses. However, the power levels measured at the two outputs of the MZI when light was launched into MUX 3 were negligible, whereas the F-t-F losses when MUX 4 was used were more than 58 db. Furthermore, the spectrum that was obtained, in the latter case, by tuning the CW laser along the 1500 to 1580 nm spectral window is shown in Figure 10. The power variation shown in the graph is quite high (more than 15 db), hindering the depiction of the SOI multiplexer transfer function. The unexpectedly high plasmonic losses combined with the aforesaid power variation, indicate the detrimentally poor performance of the plasmonic section. The reason for that could possibly lay on the unsuccessful coupling between the silicon and the Dielectric Loaded Surface Plasmon Polariton. It should be noted, though, that the plasmonic deposition on a silicon chip equipped with electrical wiring and metallization layers is a very demanding process that could readily lead to misalignment issues between the silicon and the plasmonic waveguides. Figure 10: Spectral response of the BAR and CROSS state of the plasmonic switch (bus waveguide of MUX 4 used as optical input) November 18, 2013 FP The PLATON Consortium Page 15 of 27
16 5 Experimental Evaluation of the PLA22 A-MZI 5.1 Static Optical Characterization The following figure depicts the mask layout of the PLA 22 chip design. The design follows the same guidelines as the PLA 20, with the only differences being the lack of the SOI MUX structures (as shown in Figure 11 (b)) and the addition of two silicon alignment waveguides (for V-groove assemblies). The main purpose of this chip design is to test the functionality of the hybrid cyclomerloaded (Figure 11 (c)) plasmonic A-MZI without the SOI multiplexing modules, following a step wise approach that would allow to identify and address the fabrication issues related to PLA 20 and PLA 19. Figure 11: (a) Mask layout of the PLA 22 chip, (b) lack of the optical part of the SOI MUX and (c) Gold layer and DLSPP waveguide integrated in the SOI cavity The following three chips of the PLA 22 family were sent and statically characterized in NTUA premises, both in terms of losses and thermo-optic functionality: PLA 22 W C212 PLA 22 W C312 PLA 22 W C213 The characterization includes the evaluation of the coupling and propagation losses, as well as the measurement of the spectral responses for the silicon and the plasmonic part. The results obtained for each chip are presented in the following paragraphs. November 18, 2013 FP The PLATON Consortium Page 16 of 27
17 Chip PLA22 - WC212 Figure 12 shows the spectral response of the silicon alignment waveguide (shown in Figure 11). It can be seen that the response exhibits 3dB ripples, probably due to the spectral behavior of the grating couplers, while the fiber-to-fiber losses (db) were found to be 15.5 db at nm. Figure 12: Spectral response of the silicon alignment waveguide During the loss characterization of the plasmonic MZI, a tunable CW laser was first launched into the upper and then into the lower input (the inputs are shown in Figure 11). The BAR and the CROSS outputs, for each input, where measured, whereas the laser was swept along the 1500 to 1580 nm spectral window so as to detect the spectral behaviors of the evaluated optical paths. The input optical power was 0 dbm. Figure 13: Spectral response of (a) the BAR state and (b) the CROSS state for light launched in the upper input and spectral response of (a) the BAR state and (b) the CROSS state for the light launched in the lower input November 18, 2013 FP The PLATON Consortium Page 17 of 27
18 Table 2: F-t-F losses (db) for all the input/output combinations Figure 13 presents the obtained spectral behaviors for all the respective combinations while Table 2 summarizes the minimum measured fiber-to-fiber losses for the upper and the lower input. The results indicate that the MZI was naturally biased close to the BAR state since the output power of that state is, in both cases, more than 6 db higher than the CROSS. Chip PLA22 WC312 Figure 14 depicts the spectral response of the silicon alignment waveguide for chip WC312. The fiber-to-fiber losses (db) were found to be 14.9 db at nm showing marginally improved performance compared to chip WC212, while the response exhibits again the 3dB ripples due to the spectral behavior of the grating couplers. For the characterization of the plasmonic MZI the tunable CW laser was employed. Power was launched into the upper and lower input port, whereas the respective BAR and the CROSS output ports, for each input, were measured. The tunable laser was swept along the 1500 to 1580 nm spectral window so as to detect the spectral behaviors of the evaluated optical paths. The input optical power was 0 dbm. Figure 14: Spectral response of the silicon alignment waveguide November 18, 2013 FP The PLATON Consortium Page 18 of 27
19 Figure 15: Spectral response of (a) the BAR state and (b) the CROSS state for light launched in the upper input and spectral response of (a) the BAR state and (b) the CROSS state for the light launched in the lower input Figure 15 presents the obtained spectral behaviors for all the respective combinations while Table 3 summarizes the minimum measured fiber-to-fiber losses for the upper and the lower input. It can be seen that the CROSS port of the upper input, exhibits a rather poor performance, hindering the identification of the natural biasing point of the switch. Therefore, the thermo-optic characterization is required so as to obtain a better indication on this issue. Table 3: F-t-F losses (db) for all the input/output combinations November 18, 2013 FP The PLATON Consortium Page 19 of 27
20 Chip PLA22 WC213 Figure 16 shows the spectral response of the silicon alignment waveguide for chip WC213. The 3dB ripples on the response are evident also in this graph, whereas the fiber-to-fiber losses (db) were found to be 15.1 db at nm, laying in the same range with the two other PLA 22 chips. Figure 16: Spectral response of the silicon alignment waveguide The BAR and CROSS port spectral responses for both the upper and the lower input ports were measured also for chip WC213 by sweeping the tunable CW laser along the 1500 to 1580 nm spectral window. The power launched into the chip was again 0 dbm and the obtained results are shown in the following figure. Figure 17: Spectral response of (a) the BAR state and (b) the CROSS state for light launched in the upper input and spectral response of (a) the BAR state and (b) the CROSS state for the light launched in the lower input November 18, 2013 FP The PLATON Consortium Page 20 of 27
21 Table 4 presents the minimum fiber-to-fiber losses that were measured for all the respective input-output combinations. It is clear that thermo-optic characterization is required also in this case, as the summarized results do not provide enough information on the biasing state of the switch. Table 4: F-t-F losses (db) for all the input/output combinations November 18, 2013 FP The PLATON Consortium Page 21 of 27
22 5.2 Static Thermo-optic Characterization The following figure (Figure 18) depicts the measurement configuration that was employed during the static thermo-optic characterization of the PLA 22 chips. Insets (b) and (c) show the way that the electrical tips were placed on the contact pads that are connected to the underlaying gold layer of the upper and the lower DLSPP waveguide. Figure 18: (a) Mask layout of the PLA 22 chip, electrical contact tips on (b) the upper DLSPP and (c) the lower DLSPP waveguide Each contact tip pair was connected to an external dc current source and the injected current was varied from 0 to 30 ma. The optical input was connected to the tunable CW laser while the output was measured in a power meter. The emission wavelength for each characterization was chosen according to the graphs of the static optical characterization that were presented in the previous paragraph so as to minimize the transmission losses. The thermo-optic responses as well as the stability of the thermo-optic tuning of the DLSPP waveguides that were obtained during the evaluation of each chip, are presented in the following paragraphs. November 18, 2013 FP The PLATON Consortium Page 22 of 27
23 Chip PLA 22 WC212 Firstly, current up to 30 ma was injected into the upper DLSPP waveguide while the BAR and CROSS output for each optical input were measured. Then, the lower DLSPP waveguide was thermooptically tuned and the same results were again obtained. Figure 19: Thermo-optic response of the upper DLSPP waveguide for light launched in (a) the lower and (b) the upper waveguide, and thermo-optic response of the lower DLSPP waveguide for light launched in (c) the lower and (d) the upper waveguide Figure 19 illustrates the thermo-optic response graphs that were reconstructed after the measurements together with the extinction ratios (per port) that were exhibited by the switch. It is clear that the TO behavior of the switch is approximately the same for the BAR and the CROSS state, regardless the optical input, when the current is injected in the upper or the lower DLSPP waveguide. The stability of the thermo-optic tuning over time was measured by injecting 20 ma current in the lower DLSPP waveguide and monitoring the CROSS output with light launched in the lower input for 10 minutes. The results, shown in Figure 20, indicate that the maximum variation of the output power was less than 1.8 db. November 18, 2013 FP The PLATON Consortium Page 23 of 27
24 Figure 20: Stability over time measurement for the current injected in the lower DLSPP and light launched in the lower input Chip PLA 22 WC312 The procedure, described for chip 212, was followed also here, with current up to 30 ma being injected into the upper DLSPP and, afterwards, the lower DLSPP waveguide and the BAR/CROSS outputs for each optical input being measured. Figure 21: Thermo-optic response of the upper DLSPP waveguide for light launched in (a) the lower and (b) the upper waveguide, and thermo-optic response of the lower DLSPP waveguide for light launched in (c) the lower and (d) the upper waveguide November 18, 2013 FP The PLATON Consortium Page 24 of 27
25 Figure 21 depicts the thermo-optic response graphs that were obtained while the, per-port, extinction ratios, exhibited by the switch, are shown as insets in the diagrams. The TO behavior of the switch is approximately the same for the BAR and the CROSS state, regardless the optical input, when the current is injected in the upper DLSPP. However, the responses are somewhat different when the current is injected into the lower DLSPP possibly due to permanent shifting of the biasing point during the measurements. The thermo-optic stability over time was evaluated by injecting 20 ma current for 10 minutes in the lower DLSPP waveguide and monitoring the CROSS output. The CW laser was launched in the lower input. The results, shown in Figure 20, indicate that the maximum variation of the output power was less than 0.33 db. Figure 22: Stability over time measurement for the current injected in the lower DLSPP and light launched in the lower input November 18, 2013 FP The PLATON Consortium Page 25 of 27
26 Chip PLA 22 WC213 In the case of WC213 chip, current was injected only into the lower DLSPP waveguide as conductive contact between tips and the pads of the upper DLSPP was not achieved. The BAR and CROSS output for the upper and the lower input, respectively, were measured. Figure 23: Thermo-optic response of the lower DLSPP waveguide for light launched in (a) the lower and (b) the upper waveguide Figure 23 presents the thermo-optic response graphs that were obtained after the measurements, including the extinction ratios (per port) exhibited by the switch. It can be seen that the TO behavior of the switch is approximately the same for the BAR and the CROSS state, regardless the optical input, as expected. The stability of the thermo-optic phase accumulation over time was measured by injecting 20mA current in the lower DLSPP waveguide, light into the lower input and monitoring the CROSS output for 10 minutes. The results, shown in the following figure, indicate that the maximum variation of the output power was approximately 5.5 db. This value is profoundly higher compared to the previous two samples of the PLA 22 chip family. Figure 24: Stability over time measurement for the current injected in the lower DLSPP and light launched in the lower input November 18, 2013 FP The PLATON Consortium Page 26 of 27
27 6 Conclusions This deliverable is reporting on the experimental evaluation of the PLA20 and PLA22 chips. PLA 20 (complete 2x2 router chip) revealed successful optical performance for the SOI-MUX devices but very high losses when it comes to the operation of the plasmonic switch in cascade of the SOI-MUX elements. The A-MZI switch encompassed in the PLA22 chip showed a great potential for yielding successful switching functionality with record low power consumption. The testing if the completely packaged PLA20 chip where also the electrical performance of the SOI-MUX devices can be tested is taking place as this report is being written, with the next step being the interconnection via external fibers of the SOI-MUX modules with the PLA22 chip in order to demonstrate Si-plasmonic routing even without having all modules located on the same chip. November 18, 2013 FP The PLATON Consortium Page 27 of 27
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