KV4x Family Product Brief Supports 150 MHz devices with 64 KB to 256 KB Flash

Transcription

1 Freescale Semiconductor Document Number:KV4XPB Product Brief Rev 2, 02/2015 KV4x Family Product Brief Supports 150 MHz devices with 64 KB to 256 KB Flash 1 Introduction The Kinetis KV4x family of microcontrollers is a highperformance solution offering exceptional precision, sensing and control for some of the most demanding applications in motor and power control. Built upon the ARM Cortex -M4 core running at 150 MHz with DSP and floating point unit. It features advanced high-speed and high accuracy peripherals such as high resolution pulse-width modulation (PWM) with 312 picosecond resolution, dual 12-bit analog-to-digital converters (ADCs) sampling at 4.1 Mega Samples Per Second (MSPS), a total of 30 PWM channels for support of multimotor systems and dual FlexCAN modules. The KV4x is supported by a comprehensive enablement suite from Freescale and third-party resources including reference designs, software libraries and motor configuration tools. Contents 1 Introduction Block diagram Features Part identification Block diagram The following figure shows a superset block diagram of the device. Other devices within the family have a subset of the features Freescale Semiconductor, Inc. Preliminary

2 Features MCG ARM Cortex M4 JTAG/SWD 32 khz RC 8MHz RC 32-b it C P U 150 MHz SPFPU 16 -ch DMA PLL MHz MCM Osc Low range: 32 khz High range: 4-20 MHz Crossbar switch (AXBS-Lite) FMC GPIO Up to RCM SIM PMC 128 Peripheral bridge P-Flash Up to 256KB eflexpwm 8ch + 4ch 12 bit ADC (4.1 MSPS) 12 bit ADC (4.1 MSPS) FlexTimer 8ch + 8ch +2ch 2 x PDB XBARA nano-edge 1x 12 bit DAC 4 x HSCMP with 6bit DAC ENC EWM WDOG 4 - ch PIT XBARB SRAM Up to 32KB FlexSCI FlexSCI LPTMR SPI I2C SMBUS FlexCAN x2 CRC IRQ AOI Figure 1. Block diagram 3 Features 3.1 Common features Core/System Modules Table 1. Common features Security Modules Core ARM Cortex-M4 CRC 1 CPU Frequency 150 MHz Software Watchdog (WDOG) Yes DMA 16 ch External Watchdog Monitor Yes Nested vectored interrupt controller (NVIC) 32 bit Communication interfaces Floating Point Unit Single Precision SPI 2 each with four word FIFO Memory I 2 C 1 with SMBUS support Flash memory Up to 256 KB UART 2 SRAM Up to 32 KB FlexCAN 2 supporting 2.0A/B Timer Modules Clocks PDB 2 PDBs with 15 inputs Table continues on the next page... 2 Preliminary Freescale Semiconductor, Inc.

3 Table 1. Common features (continued) Features External crystal oscillator or resonator Internal clock references Frequency-locked loop (FLL) /PLL Analog modules Low range, low power or fullswing: khz High range, low power or full-swing: 4-20 MHz 32 khz IRC 1 khz LPO Range: MHz FlexTimer (FTM) PIT General-purpose input/output (GPIO) Human Machine Interface 3 FTMs: 2 8-channels with motor control features and 1 2-channel FTM with quadrature decoding 1 4-ch PIT 3 V I/O 12 bit DAC 1 Maximum number of I/Os 74 in 100-pin package Analog Comparators with 6- bit DAC 12-bit analog-to-digital converter ( ADC) 4 Hardware characteristics 2x12-bit cyclic analog-todigital converters (ADC) with 4.1 MSPS sample rate Package Voltage range 48 in 64-pin package 38 in 48-pin package 100-LQFP ( 14 x 14 mm) 64-LQFP (10 x 10 mm) 48-LQFP (7 x 7 mm) 1.71 V to 3.6 V Temperature range (TA) -40 C to 105 C 3.2 Orderable part numbers and features Part Number Core Freq (MHz) NOTE The 48-pin LQFP package for this product is not yet available. However, it is included in a Package Your Way program for Kinetis MCUs. Visit freescale.com/kpyw for more details. Flash Mem (KB) RAM (KB) MKV 4.1 MSPS ADC 1.9 MSPS eflex PWM 1 Nano Edge Flex Timer bit DAC CMP with 6-bit DAC SCI SPI I2C Flex CAN 46F Yes F Yes F Yes F Yes F F F F F Yes Table continues on the next page... Pin Count Freescale Semiconductor, Inc. Preliminary 3

4 Module-by-module feature list Part Number Core Freq (MHz) Flash Mem (KB) RAM (KB) MKV 4.1 MSPS ADC 1.9 MSPS eflex PWM 1 Nano Edge Flex Timer bit DAC CMP with 6-bit DAC SCI SPI I2C Flex CAN 44F Yes F Yes F Yes F Yes F F F F F F F F F F F F F F Pin Count = 12 eflexpwm channels are available 8 = 8 eflexpwm channels are available = FTM0 8 channels, FTM3 8 channels and FTM1 2channels are available 8+2 = FTM0 8 channels are available, FTM1 2channels are available 3. Package Your Way 3.3 Module-by-module feature list Core modules ARM Cortex M4 Core (150 MHz) with SPFPU ARM core based on ARMv7 architecture & Thumb -2 ISA Harvard bus architecture Up to 150 MHz core frequency from 1.71 V to 3.6 V Integrated Digital Signal Processor (DSP) Single Point Floating Point unit (SPFPU) compliant to IEEE 754 Standard for Floating point arithmetic Integrated bus matrix Configurable Nested Vectored Interrupt Controller (NVIC) Support up to 32 interrupt request sources 3-stage pipeline micro architecture with branch speculation Serial wire debug (SWD) reduces the number of pins required for debugging 4 Preliminary Freescale Semiconductor, Inc.

5 Core modules Nested Vectored Interrupt Controller (NVIC) Close coupling with Cortex-M4 core's Harvard architecture enables low latency interrupt handling Up to 64 interrupt sources Includes a single non-maskable interrupt 16 levels of priority, with each interrupt source dynamically configurable Supports nesting of interrupts when higher priority interrupts are activated Relocatable vector table Low-Leakage Wakeup Unit (LLWU) Support for up to 32 external input pins and up to 8 internal modules with individual enable bits for device interrupt from low leakage modes. Input sources may be from external pins or from internal peripherals capable of running in various low power stop modes. External pin wake-up inputs, each of which is programmable as falling-edge, rising-edge, or any change. Wake-up inputs that are activated after the device enters a low-leakage power mode. Optional digital filters provided to qualify an external pin detect. Note that when the LPO clock is disabled, the filters are disabled and bypassed DMA Controller Up to sixteen fully programmable channels with 32-byte transfer control descriptors Data movement via dual-address transfers for 8-, 16-, 32-, 128-bit data values Programmable source, destination addresses, transfer size, support for enhanced address modes Support for major and minor nested counters with one request and one interrupt per channel Support for channel-to-channel linking and scatter/gather for continuous transfers with fixed priority and round-robin channel arbitration DMA Channel Multiplexer (DMA MUX) 16 independently selectable DMA channel routers 4 periodic trigger sources available Each channel router can be assigned to 1 of 63 possible peripheral DMA sources System Clocks Frequency-locked loop (FLL) 2-48MHz Digitally-controlled oscillator (DCO) Option to program DCO frequency for a 32,768 Hz external reference clock source Internal or external reference clock can be used to control the FLL 0.2% resolution using 32 khz internal reference clock 2% deviation over voltage and temperature using internal 32 khz internal reference clock, 1% deviation with limited temperature range (0 C to 70 C) Phase-locked loop (PLL) Voltage-controlled oscillator (VCO) External reference clock is used to control the PLL Modulo VCO frequency divider Phase/Frequency detector Integrated loop filter Freescale Semiconductor, Inc. Preliminary 5

6 Memory Internal reference clock generator Can be used as a clock source for other on-chip peripherals External clock from the Crystal Oscillator (XOSC) Can be selected as the clock source for the MCU External clock monitor with reset request capability Reference divider for FLL is provided Watchdog Timer (WDOG) Independent, configurable clock source input Write-once control bits with unlock sequence Programmable timeout period Fast mechanism to test watchdog clock tree and resets MCU. Windowed refresh option Unique and robust refresh mechanism Cumulative count of watchdog resets between power-on resets Configurable interrupt on timeout External Watchdog Monitor (EWM) Monitors external circuit as well as the software flow Programmable timeout period Interrupt capability prior to timeout Independent output (EWM_OUT_b) that places external circuit (but not CPU and peripheral) in a safe mode when EWM timeout occurs Utilizes 1 khz LPO clock source that is independent of CPU clock Continues to operate in Wait mode and Stop mode Debug Controller Serial Wire JTAG Debug Port (SWJ-DP) combines external interface that provides a standard JTAG interface for debug access external interface that provides a serial-wire bidirectional debug interface Debug Watchpoint and Trace (DWT) with the following functionality: four comparators configurable as a hardware watchpoint, an ETM trigger, a PC sampler event trigger, or a data address sampler event trigger several counters or a data match event trigger for performance profiling configurable to emit PC samples at defined intervals or to emit interrupt event information Instrumentation Trace Macrocell (ITM) with the following functionality: Software trace - writes directly to ITM stimulus registers can cause packets to be emitted Hardware trace - packets generated by DWT are emitted by ITM Time stamping - emitted relative to packets Test Port Interface Unit (TPIU) acts as a bridge between ITM and an off-chip Trace Port Analyzer Flash Patch and Breakpoints (FPB) implements hardware breakpoints and patches code and data from code space to system space Memory On-Chip Memory Up to 256 KB program flash memory 6 Preliminary Freescale Semiconductor, Inc.

7 Human-machine interface Up to 32 KB SRAM Security circuitry to prevent unauthorized access to RAM and flash contents Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16/32-bit shift register User Configurable 16/32 bit CRC Programmable Generator Polynomial Error detection for all single, double, odd, and most multi-bit errors Programmable initial seed value High-speed CRC calculation Optional feature to transpose input data and CRC result via transpose register, required on applications where bytes are in lsb format Human-machine interface General Purpose Input/Output (GPIO) Progammable glitch filter and interrupt with selectable polarity on all input pins Hysteresis and configurable pull up/down device on all input pins Analog bit Cyclic Analog-to-Digital Converter (ADC) Two independent 12-bit cyclic analog-to-digital converters (ADCs) Each ADC has 8 channel internal mux Each ADC has ability to scan and store up to 8 conversion results Built-in x1, x2, x4 programmable gain pre-amplifier Maximum ADC clock frequency up to 25 MHz, 240nS conversion time Support of analog inputs for single-ended and differential conversions Sequential, parallel, and independent scan mode First 8 samples have offset, limit and zero-crossing calculation supported ADC conversions can be synchronized by any module connected to internal crossbar module, such as PWM, timer modules, GPIO, and comparators Support for multi-triggering mode with a programmable number of conversions on each trigger Additional external muxs added to create an option of up to 38 possible ADC input channels in 100-pin devices High-Speed Analog Comparator (CMP) Up to four selectable comparator inputs; each input can be compared with any input by any polarity sequence Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output Comparator output may be sampled, windowed(ideal for zero cross detection) or digitally filtered Fixed ACMP hysteresis from 3 mv to 20 mv Up to eight selectable comparator inputs; each input can be compared with any input by any polarity sequence Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output Remains operational in low power mode Internal 6-bit DAC programmable reference on fourth input Freescale Semiconductor, Inc. Preliminary 7

8 Timers Typically 5 mv of input offset Less than 40 μa power consumption in enable mode and less than 1 na in disable mode (excluding programmable reference generator) bit Digital-to-Analog Converter 12-bit resolution Powerdown mode Automatic mode allows the DAC to automatically generate pre-programmed output waveforms, including square, triangle, and sawtooth waveforms (for applications like slope compensation) Programmable period, update rate, and range Output can be routed to an internal comparator, ADC, or optionally to an off-chip destination Timers Enhanced Flex Pulse Width Modulator (eflexpwm) This chip has one eflexpwm module. Up to 12 output channels in each module, 3 outputs from each of four sub-modules. 16 bits of resolution for center, edge aligned, and asymmetrical PWMs PWMA with NanoEdge high resolution Fractional delay for enhanced resolution of the PWM period and edge placement Arbitrary PWM edge placement PWM phase shifting NanoEdge implementation: 312 ps PWM frequency and duty-cycle resolution Each complementary pair can operate with its own PWM frequency base and deadtime values 4 time base in each PWM module Independent top and bottom deadtime insertion PWM outputs can operate as complementary pairs or independent channels Independent control of both edges of each PWM output Enhanced input capture and output compare functionality on each input Channels not used for PWM generation can be used for buffered output compare functions Channels not used for PWM generation can be used for input capture functions Enhanced dual edge capture functionality Synchronization to external hardware or other PWM supported Double buffered PWM registers Integral reload rates from 1 to 16 Half-cycle reload capability Multiple output trigger events can be generated per PWM cycle via hardware Support for double switching PWM outputs Up to eight fault inputs can be assigned to control multiple PWM outputs Programmable filters for fault inputs Independently programmable PWM output polarity Individual software control of each PWM output All outputs can be programmed to change simultaneously via a FORCE_OUT event PWMX pin can optionally output a third PWM signal from each submodule Option to supply the source for each complementary PWM signal pair from any of the following: external digital pin internal timer channel external ADC input, taking into account values set in ADC high and low limit registers 8 Preliminary Freescale Semiconductor, Inc.

9 Timers FlexTimers (FTM) 2x8-ch + 1x2-ch FlexTimers Selectable FTM source clock Programmable prescaler 16-bit counter supporting free-running or initial/final value, and counting is up or up-down Input capture, output compare, and edge-aligned and center-aligned PWM modes Input capture and output compare modes Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels with independent outputs Deadtime insertion is available for each complementary pair Generation of hardware triggers Software control of PWM outputs Up to 4 fault inputs for global fault control Configurable channel polarity Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event DMA support for FTM events Global time base mode shares single time base across multiple FTM instances Programmable Interrupt Timers (PITs) Up to 4 general purpose interrupt timers Up to 4 interrupt timers for triggering ADC conversions 32-bit counter resolution Clocked by system clock frequency DMA support Low Power Timer Operation as timer or pulse counter Selectable clock for prescaler/glitch filter 1 khz internal LPO External low power crystal oscillator Internal reference clock (not available in low leakage power modes) Configurable glitch filter or prescaler Interrupt generated on timer compare Hardware trigger generated on timer compare Quadrature Encoder/Decoder (ENC) Includes logic to decode quadrature signals Configurable digital filter for inputs 32-bit position counter capable of modulo counting 16-bit position difference register Maximum count frequency equals the peripheral clock rate Position counter can be initialized by software or external events Preloadable 16-bit revolution counter Inputs can be connected to a general purpose timer to aid low speed velocity measurements Quadrature decoder filter can be bypassed A watchdog timer to detect a non-rotating shaft condition Freescale Semiconductor, Inc. Preliminary 9

10 Communication interfaces Compare function to indicate when shaft has reached a defined position Optional interrupt when both PHASEA and PHASEB inputs change in the same cycle Communication interfaces Serial Peripheral Interface (SPI) Master and slave mode Full-duplex, three-wire synchronous transfers Programmable transmit bit rate Double-buffered transmit and receive data registers Serial clock phase and polarity options Slave select output Mode fault error flag with CPU interrupt capability Control of SPI operation during wait mode Selectable MSB-first or LSB-first shifting Programmable 8-bit or 16-bit data transmission length Receive data buffer hardware match feature 64-bit FIFO mode for high speed transfers of large amounts of data Support for both transmit and receive by DMA UART Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format 13-bit baud rate selection with fractional divide of 32 Programmable 8-bit or 9-bit data format Separately enabled transmitter and receiver Programmable transmitter output polarity Programmable receive input polarity 13-bit break character option 11-bit break character detection option Parameterizable buffer support for one dataword for each transmit and receive Independent FIFO structure for transmit and receive Two receiver wakeup methods: Idle line wakeup Address mark wakeup Address match feature in receiver to reduce address mark wakeup ISR overhead Hardware flow control support for request to send (RTS) and clear to send (CTS) signals Interrupt or DMA driven operation Receiver framing error detection Hardware parity generation and checking 1/16 bit-time noise detection Flex Controller Area Network (FlexCAN) module Clock source from PLL or XOSC/CLKIN Implementation of CAN protocol Version 2.0 A/B Standard and extended data frames Data length of 0 to 8 bytes Programmable bit rate up to 1 Mbps 10 Preliminary Freescale Semiconductor, Inc.

11 Part identification Support for remote frames Sixteen Message Buffers: each Message Buffer can be configured as receive or transmit, and supports standard and extended messages Individual Rx Mask Registers per Message Buffer Internal timer for time-stamping of received and transmitted messages Listen-only mode capability Programmable loopback mode, supporting self-test operation Programmable transmission priority scheme: lowest ID, lowest buffer number, or highest priority Global network time, synchronized by a specific message Low power modes, with programmable wakeup on bus activity Inter-Integrated Circuit (I 2 C) Compatible with I 2 C bus standard and SMBus version 2 features Up to 100 kbps with maximum bus loading, 400kbps supported with limited bus loading Multi-master operation Software programmable for one of 64 different serial clock frequencies Programmable slave address and glitch input filter Interrupt driven byte-by-byte data transfer Arbitration lost interrupt with automatic mode switching from master to slave Calling address identification interrupt Bus busy detection broadcast and 10-bit address extension Address matching causes wake-up when processor is in low power mode DMA support 4 Part identification 4.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 4.2 Format Part numbers for this device have the following format: Q KV## A FFF T PP CC N 4.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status M = Fully qualified, general market flow P = Prequalification KV## Kinetis family KV40 Table continues on the next page... Freescale Semiconductor, Inc. Preliminary 11

12 Part identification Field Description Values KV41 KV43 KV44 KV45 KV46 A Key attribute F = Cortex-M4 w/ DSP and FPU FFF Program flash memory size 64 = 64 KB 128 = 128 KB 256 = 256 KB T Temperature range ( C) V = 40 to 105 PP Package identifier LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) LL = 100 LQFP (14 mm x 14 mm) CCC Maximum CPU frequency (MHz) 15 = 150 MHz N Packaging type R = Tape and reel (Blank) = Trays 12 Preliminary Freescale Semiconductor, Inc.

13 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. Freescale, the Freescale logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved 2014 Freescale Semiconductor, Inc. Document Number KV4XPB Revision 2, 02/2015 Preliminary