Go over Quizzes 2 and 4. Introduction to pipelining Maybe hazards

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1 Pipelining 1

2 Tody Go over Quizzes 2 nd 4. Inroduion o pipelining Mybe hzrds 2

3 Pipelining Cyle 1 10n (10ns) Cyle 2 20n (10ns) Cyle 3 30n (10ns) Wh s he leny for one uni of work? Wh s he hroughpu?

4 Pipelining 1.Brek up he logi wih lhes ino pipeline sges 2.Eh sge n on differen d 3.hes hold he inpus o heir sge 4.Every lok yle d rnsfers from one pipe sge o he nex (10ns) (2ns) (2ns) (2ns) (2ns) (2ns)

5 yle 1 2ns yle 2 4ns yle 3 6ns yle 4 8ns yle 5 10ns yle 6 12ns Wh s he leny for one uni of work? Wh s he hroughpu?

6 Criil ph review Criil ph is he longes possible dely beween wo regisers in design. The riil ph ses he yle ime, sine he yle ime mus be long enough for signl o rverse he riil ph. enghening or shorening non-riil phs does no hnge performne Idelly, ll phs re bou he sme lengh 6

7 Pipelining nd Hopefully, riil ph redued by 1/3 7

8 imiions of Pipelining You nno pipeline forever Some logi nno be pipelined rbirrily -- Memories Some logi is inonvenien o pipeline. How do you inser regiser in he middle of n muliplier? Regisers hve os They os re -- hoose nrrow poins in he logi They os energy -- lhes don do ny useful work They os ime Exr logi dely Se-up nd hold imes. Pipelining my no ffe he riil ph s you expe 8

9 Pipelining Overhed Dely (D) -- How long does he logi ke (i.e., he useful pr) Se up ime (ST) -- How long before he lok edge do he inpus o regiser need be redy? Regiser dely (RD) -- Dely hrough he inernls of he regiser. 9

10 Pipelining Overhed Clok Seup ime Regiser in????? New D Regiser ou Old d New d Regiser dely 10

11 Pipelining Overhed Dely (D) -- How long does he logi ke (i.e., he useful pr) Se up ime (ST) -- How long before he lok edge do he inpus o regiser need be redy? Regiser dely (RD) -- Dely hrough he inernls of he regiser. BseCT -- yle ime before pipelining BseCT = D + ST + RD. PipeCT -- yle ime fer pipelining N imes PipeCT = ST + RD + D/N Tol ime = N*ST + N*RD + D 11

12 Pipelining Diffiulies Fs Slow Slow Fs Fs Slow Slow Fs You n lwys pipeline how you would like The riil ph only wen down fs logi 12

13 How o pipeline proessor Brek eh insruion ino piees -- remember he bsi lgorihm for exeuion Feh Deode Colle rgumens Exeue Wrie bk resuls Compue nex PC The lssi 5-sge MIPS pipeline Feh -- red he insruion Deode -- deode nd red from he regiser file Exeue -- Perform rihmei ops nd ddress lulions -- ess d memory. Wrie bk-- Sore resuls in he regiser file. 13

14 Pipelining proessor Feh Deode Mem Wrie EX bk Feh Deode Mem Wrie EX bk 14

15 Imp of Pipelining Brek he proessor ino P pipe sges Wh hppens o leny? = Ins * CPI * CyleTime The yle ime =? CPI =? 15

16 Imp of Pipelining Brek he proessor ino P pipe sges Wh hppens o leny? = Ins * CPI * CyleTime The yle ime = CT/P CPI = 1 CPI is n verge: Cyles/insruions When # of insruions is lrge, CPI = 1 If jus one insruion, CPI = P 16

17 Pipelined Dph PC 4 Insru(on r 1 Regiser r 2 File Wrie r Wrie D D 1 D 2 Shi< le< 2 AU Wrie D D D Sign 16 Exend 32

18 Pipelined Dph PC 4 Insru(on IFeh/De r 1 Regiser r 2 File Wrie r Wrie D D 1 D 2 De/Exe Shi< le< 2 AU Exe/Mem Wrie D D D Mem/WB Sign 16 Exend 32

19 Pipelined Dph 4 Insru(on r 1 Regiser r 2 File Wrie r Wrie D D 1 D 2 Shi< le< 2 AU Wrie D D D dd lw Sub Sub. Sign 16 Exend 32

20 Pipelined Dph 4 Insru(on r 1 Regiser r 2 File Wrie r Wrie D D 1 D 2 Shi< le< 2 AU Wrie D D D dd lw Sub Sub. Sign 16 Exend 32

21 Pipelined Dph 4 Insru(on r 1 Regiser r 2 File Wrie r Wrie D D 1 D 2 Shi< le< 2 AU Wrie D D D dd lw Sub Sub. Sign 16 Exend 32

22 Pipelined Dph 4 Insru(on r 1 Regiser r 2 File Wrie r Wrie D D 1 D 2 Shi< le< 2 AU Wrie D D D dd lw Sub Sub. Sign 16 Exend 32

23 Pipelined Dph 4 Insru(on r 1 Regiser r 2 File Wrie r Wrie D D 1 D 2 Shi< le< 2 AU Wrie D D D dd lw Subi Sub. Sign 16 Exend 32

24 Simple Pipelining Conrol Conrol Feh Deode Mem Wrie EX bk Conrol Conrol Conrol Conrol Feh Deode Mem Wrie EX bk Compue ll he onrol bis in deode, hen pss hem from sge o sge. I won sy his simple... 24

25 Pipelining is Triky If ll he d flows in one direion, pipelining is relively esy. No so, for proessors. Deode nd wrie bk boh ess he regiser file. Brnh insruions ffe he nex PC Insruions need vlues ompued by previous insruions 25

26 No jus riky, Hzrdous! Hzrds re siuions where pipelining does no work s elegnly s we would like Cused by bkwrd flowing signls Or by lk of vilble hrdwre Three kinds D hzrds -- n inpu is no vilble on he yle i is needed Conrol hzrds -- he nex insruion is no known Sruurl hzrds -- we hve run ou of hrdwre resoure Deeing, voiding, nd reovering from hese hzrds is wh mkes proessor design hrd. Th, nd he Xilinx ools ;-) 26

27 A Sruurl Hzrd Boh he deode nd wrie bk sge hve o ess he regiser file. There is only one regisers file. A sruurl hzrd!! Soluion: Wrie erly, red le Wries our he lok edge nd omplee long before he end of he yle This leve enough ime for he oupus o sele for he reds. Hzrd voided! Feh Deode Mem Wrie EX bk 27

Outline Single Cycle Processor Design Multi cycle Processor. Pipelined Processor Design. Overall clock period. Analyzing performance 3/18/2015

Outline Single Cycle Processor Design Multi cycle Processor. Pipelined Processor Design. Overall clock period. Analyzing performance 3/18/2015 3/8/5 Pipelined Processor Design. Sahu CSE, T Guwahai Please be updaed wih hp://ainga.iig.erne.in/~asahu/c/ Ouline Single Cycle Processor Design Muli cycle Processor Merging M and, emoving dder and dder