High-p T (Hi-pT) Board for ATLAS TGC Trigger

Transcription

1 Muon Endcap Trigger Electronics Document presented for FDR held on March 1, 2004 CF I. Introduction High-p T (Hi-pT) Board for ATLAS TGC Trigger ATLAS TGC Electronics group *revised on 16th March 2004 The main component of a High-p T (Hi-pT) board is Hi-pT ASIC [1]. Total four Hi-pT ASICs are mounted for all three types of the board. These three types are called endcap-wire, endcap-strip and forward. Each of them accepts output signals from PS boards, which handle wire and/or strip signals of the endcap or the forward region of TGC. Every type of the Hi-pT board accepts LVDS serialised signals with Unshielded Twisted Pair (UTP) category 5 cables, and deserialized the signals, makes Hi-pT coincidence from both doublet signals (r or φ and r or φ) and triplet ones (r or φ), and finally sends the trigger results to a Sector Logic (SL) module via optical fibre cables in serialised G-link protocol. A Hi-pT board must be installed in a VME 9U crate with the depth of 19cm in which is installed at the outer rim of the big-wheel of the triplet (M1). Electronics components on the board must be, therefore, satisfied with the conditions set by the ATLAS RHA (Radiation Hardness Assurance) working group, and cleared the standard tests also set by the group. The component used on the board (listed below) have been cleared such the tests [2]. II. Hi-pT ASIC The active component of the board is Hi-pT ASIC. Input and output configuration of the board is almost identical to one of the ASIC. Understanding of this ASIC is indispensable to understand the board configuration. In this section we briefly review the inside of the ASIC. The detailed description of the ASIC will be found in [1]. Fig.1 shows the block diagram of the ASIC. The structure is identical for both wire and strip signals. Signals from the triplet (only position information of r or φ) are coming downward from top in the figure while the doublet signals (r or φ and r or φ) are coming from left side. The position information from both inputs are made coincidence in the matrix block to identify high p T muons (p T > 20 GeV/c). Maximum two highest p T muons can be selected in 2-out-of- 6 select block, and the position data of these candidates are outputted together with the corresponding displacement information, which is kept untouched in ASIC. Since there is only one 2-out-of-6 select block, ASIC outputs also these two highest p T data. Even if there are no candidate tracks found in ASIC, both the position and displacement data of two highest p T tracks are outputted through ASIC if more than two tracks are alreadyfound in SLB ASICs connected [3]. Input data configuration of Hi-pT ASIC is given in Table 1. The ASIC can accept maximum six low-p T tracks from doublet SLB ASICs and 12 tracks from triplet SLB ASICs. These numbers are common for both the wire and strip signals.

2 Table 1:Hi-pT ASIC input configuration Triplet Doublet Wire Strip Wire & Strip Max. Hits/SLB ASICs Max. no. of SLB ASICs Maximum number of hits Figure 1: Block diagram of Hi-pT ASIC

3 III. Types of Boards There are three types of Hi-pT board, 1. for endcap-wire, 2.for endcap-strip, and 3. for forward. All boards mount four Hi-pT ASICs. The difference of the types are only number of inputs and outputs of four Hi-pT ASICs. In Tables 2 to 4, the number of SLB ASICs connected to the input for both the triplet and doublet and number of candidate tracks to be selected for every Hi-pT ASICs mounted in each board are summarised. The selection rule applied to each Hi-pT ASIC is also listed in these tables. The selection rule consists two numbers, one is to specify maximum number of low-p T candidates to be inputted, and the another one is the maximum number of high p T candidates to be selected. The selection rules (input and output scheme) are determined by the board connection diagram for a trigger sector shown in Fig.2. The rules are closely connected to the readout segmentation scheme of the wire signals. In Fig. 3, we show the signal segmentation diagram. In order to provide consistent trigger information from the triplet and the doublet, we must process signals in the tower geometry structure. We have had, thus, to set specific segmentation for the wire signal processing as shown in Fig. 3. We have segmented the wire readout sections into seven for the triplet and 10 for the doublet in the endcap region while we have divided into four for both the triplet and doublet. The segmentations can be seen in the different color boxes in the figure. The 10 segments in the endcap doublets are processed with 10 SLB ASICs denoted as EWD0 to EWD9 in Fig. 2. The seven segemnts in the triplet are served by SLB EWT0 to EWT6. Normally one SLB ASIC covers one segement and gives at maximum two muon candidate tracks. The three Hi-pT ASICs except top one are applied unifromly the selection rule of 6 2 because maximum number of tracks passed through in the three segments covered by these Hi-pT ASICs will be six. The inputs of the first Hi-pT ASIC Figure 2: Module Connection diagram

4 Figure 3: TGC trigger signal segmentation scheme of wire (colored boxes) and strip (white boxes) channels. mounted on type end-cap comes from the SLB ASICs (SB) of EWD0 and EWT0 as shown in Fig.3. The served region of these SLB ASICs corresponds to the top (blue colored) boxes of both the triplet (M1) and the doublet (M2 and M3). Thus the selection rule of 2 1 will be appropriate for this Hi-pT ASIC. The number of tracks passed in the segment, however, will be expected as very low. This is a reason why the selection rule 1 1 is applied to this Hi-pT ASIC. The Strip segmentations are also indicated in the white boxes in Fig. 3. Numbers of segments in End-cap region are five (doublet) and four (triplet). The five segments are processed with five SLB ASICs of ESD0 to ESD4 while four segments are covered with two SLB ASICs of EST0 and EST1 (Note that two identical matrices are installed in an SLB ASIC for the triplet strip channel signal processing). One Hi-pT ASIC which covers three SLB ASICs is applied to 6 2, and the other ASIC which covers two SLB ASICs is applied to 4 2 rule. The same explanation is also refered to for the selection rules for the type forward. The design examples of these three types are sketched in Fig. 4 to Fig. 6. Table 2:Endcap-wire: inputted for doublet and triplet, selection rule Hi-pT ASIC Doublet Triplet Selection rule

5 Table 3:Endcap-strip: inputted for doublet and triplet, selection rule Hi-pT ASIC Doublet Triplet Selection rule Table 4:Forward: inputted for doublet and triplet, selection rule Hi-pT ASIC Doublet Triplet Selection rule not used

6 Figure 4: Endcap-wire Figure 5: Endcap-strip

7 Figure 6: Forward

8 IV. Parts to be mounted on board The components and electronics parts to be mounted on every type of Hi-pT board are listed in Table 5. V. Development History Table 5:Electronics parts list Parts Model Endcap wire Endcap strip Forward RJ45 Connector LVDS Desirialiser SN65LVDS1224A Hi-pT ASIC Hitachi GA G-Link HDMP-1032A Transmitter Agilent E/O Converter V23818-K305-L57 Infineon Clock Driver QS IDT CPLD Actel SX-A JTAG ASP SN74LVT Bus Driver SN74LVTH Open Drain Buffer SN74LVC Diode MA Bus Driver SN74LVT LVDS receiver SN65LVDS OR SN74LVC Comparator TC74AC The first prototype of a forward board has been constructed in Summer The Hi-pT ASIC mounted on the board was Version 3 1 (submitted in January 2001 and delivered in February 2001). This IC was almost identical to the production version one (version 4). The board fitted to the VME 9U crate with the depth of 19cm. This board size was the same as the final one. Instead of the Anti-fuse FPGA, a conventional Xilinx FPGA (XC95288) was used to control the VME signals. The LVDS receiver used on this board was one of National Semiconductor product (DS92LV1224) while the one used on the production version board will be one from Texas Instruments (SN65LVDS1224). The pin assignment of the Texas Instruments LVDS receiver is compatible with one of National Semiconductor. The reason why we change it to Texas Instruments is to consider total ionisation dose (TID) data, which we have made measurement in the radiation hardness test [2]. Texas Instruments one is preferrable. This prototype version has been used extensively for all the slice tests from 2001 to 2003 [4] and the beam test at CERN SPS H8 in In such long time, the board has worked. The picture of the board is shown in Fig This version is also called as HITACHI GA version 1. The ASIC was the first one to be fabricated in HITACHI Gate Array technology.

9 Figure 7: First prototype of the Hi-pT board: type forward The several registers has been implemented in order to control the readout of LVDS deserialiser (three registers) and of G-link (one), and nine registers for Hi-pT ASICs. The registers are accessed with A24D16 mode in VME operation. The register list is shown in Table 6. Although the board has been designed with type forward, the registers set on the board includes ones used for all other types (endcap-wire and endcap-strip). Although the registers implemented are still for the prototype, the same register set must be implemented in the production type board. Table 6:Register Table for Hi-pT board Address Register Name Read/Write Initial Value Bit size Endcap-wire 0x00 LOCK_EWT R 0x3FFF 14 0x02 LOCK_EWD_Upper R 0xFF 8 0x04 LOCK_EWD_Lower R 0xFFF 12 0x06 LOCK_EWG R 0 4 0x08 CS_EW R/W 0 8 0x0A VD_H0_EWD W 0 3 0x0C VD_H0_EWT W 0 6 0x0E VD_H1_EWD W 0 9 0x10 VD_H1_EWT W x12 VD_H2_EWD W 0 9 0x14 VD_H2_EWT W x16 VD_H3_EWD W 0 9 0x18 VD_H3_EWT W 0 9 Endcap-Strip 0x20 LOCK_EST R 0xFFFF 16 0x22 LOCK_ESD_SmallA R 0x3FF 10 0x24 LOCK_ESD_LargeA R 0x3FF 10 0x26 LOCK_ESG R 0xF 4 0x28 CS_ES R/W 0 8 0x2A VD_H0_ESD W 0 9

10 The contents (bit allocation and meaning) of the individual registers should be referred to ref. 5. VI. References Table 6:Register Table for Hi-pT board Address Register Name Read/Write Initial Value Bit size 0x2C VD_H0_EST W 0 6 0x2E VD_H1_ESD W 0 6 0x30 VD_H1_EST W 0 3 0x32 VD_H2_ESD W 0 9 0x34 VD_H2_EST W 0 6 0x36 VD_H3_ESD W 0 6 0x38 VD_H3_EST W 0 3 Forward 0x20 LOCK_FT R 0x2FF 10 0x22 LOCK_FWD R 0xFF 8 0x24 LOCK_FSD R 0x3 2 0x26 LOCK_FG R 0 3 0x28 CS_F R/W 0 8 0x2A VD_H0_FWD W 0 9 0x2C VD_H0_FWT W 0 9 0x2E VD_H1_FWD W 0 3 0x30 VD_H1_FWT W 0 9 0x32 VD_H2_FSD W 0 3 0x34 VD_H2_FST W 0 3 0x36 VD_H3_FSD W 0 3 0x38 VD_H3_FST W 0 3 [1] Hi-pT Trigger ASIC for ATLAS TGC, August, 2002, document submitted to ATLAS TGC Hi-pT ASIC PRR held in September, 2002 [2] TGC Radiation Test Report for TGC electronics FDR held in March, 2004, [3] SLB ASIC Technical Document, document submitted to ATLAS TGC electronics FDR held in March, 2004 [4] Slice Tests of Level 1 Muon End-cap Trigger System, document submitted to ATLAS TGC electronics FDR held in March, 2004 [5] Yoshio Nakamura, Hi-pT Board Design Manual (in Japanese), June 2001