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1 Is Now Part of To learn more about ON Semiconductor, please visit our website at ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

2 AN-4187 Board Assembly Guidelines for Fairchild PQFN 88 Dual Cool Packages Summary Power Quad Flat No-Lead (PQFN) packages are widely used for low voltage applications. Because of its small configuration and low profile, it is a good space-saving alternative to the typical leaded packages. Fairchild has developed a PQFN package footprint, the PQFN 8 x 8 Dual Cool package. The new package size will have an advantage over the industrial standard SMD component, the D2PAK package, because of its size. And with the exposed metal slug on the top of the package, this will allow an added benefit for heat dissipation with the application of air flow or heatsink. This application note on the Power88 Dual Cool package will guide customers on how to use the package in the board manufacturing line. Board Attributes and Design Guide Land Pattern Design Below is the recommended land pattern design for the PQFN package. Figure 1. Figure 2. PQFN 8 x 8 Dual Cool Package, Top View PQFN 8 x 8 Dual Cool Package, Bottom View Figure 3. Recommended Land Pattern for Power88 (Dimensions are in Millimeters) The source and gate pads are larger than the package lead to allow toe filleting of the solder. This is also wider than the leads, providing enough allowance for variation in board fabrication and component placement during assembly. This can typically vary up to 0.10 mm combined. The land pad for the exposed thermal pads of the package is equal to the size of this exposed pad. This big connection between the board and the component will allow the strong surface tension of the molten solder to pull the component and align itself with the land pad. With this, even highly offset component placement will let the component to self-align with the board pads. Rev /27/16

3 Figure 4. Solder Fillet at Toe of the Component Lead In power applications where a large amount of heat is generated during the application, wide Cu artwork on the board allows more area for heat to be dissipated. In the thermal characterization done on this package, the increase in Cu registration on the board connected to the drain pad results significantly lower thermal resistance. With this, it is recommended that the drain pad on the board be routed and connected to a large Cu area on the board for heat dissipation. The board pads can either be solder mask defined (SMD) or non-solder mask defined (NSMD). The difference is illustrated below. In the soldering evaluation conducted on the PQFN 8x8 Dual Cool package, it is noted that solder beading around the drain pad is more prevalent in SMD pads than NSMD pads. It is believed that the gap between the solder mask and the Cu pad in the NSMD pad provides a space for the solder particles to settle when this is pushed out by the out gassing of flux during preheating, and then wicks the land pad back during reflow. With this, it is recommended that the NSMD pad be used on the drain pad of the PQFN 8x8, and Cu be routed out from the four fused drain leads for electrical and thermal connection. Board Surface Finish The pad surface finishes that are commonly used on boards are NiAu (electroless nickel immersion gold), OSP (organic solderability preservative) and HASL (hot air surface leveling). Another popular finish is the immersion Ag (silver). NiAu is preferable in some applications and finepitch packages because of its excellent surface solderability and flatness. OSP has a very low cost and excellent flatness. The thickness should depend on the resistance of the underlying Cu pad from tarnishing and retention of the solderability of the surface. HASL is the most readily available surface finish. It has a superior barrel fill and solderability characteristics. Immersion (Ag) is a lead-free alternative and has an excellent flatness, however, special handling may be required. There is no preference for the PQFN 8x8 Dual Cool package on the suitable surface finish; however, reliability tests have been performed on this package used OSP and NiAu surface finishes, wherein in both finishes, the package passed the qualification requirements. Figure 5. Difference between an NSMD and SMD Land Pad In NSMD, the copper pad is etched out to define the land pattern. The overall pattern registration is dependent on the copper artwork. The SMD pad, on the other hand, is defined by a photo-imageable solder mask process. Because of the smaller area covered by the NSMD pads, this allows more area for routing traces around the component. In SMD pads, the Cu artwork is much larger than the pads, and this is defined by the solder mask, allowing easy routing of Cu traces and connecting the large Cu for thermal dissipation. Rev /27/16 2

4 Board Assembly Considerations by Solder Paste Printing and Reflow Process Solder Paste Solder pastes normally used in board assembly have particles sizes of either Type 3 or Type 4, and their flux materials are classified as ROL0 (rosin based, low activity and halide-free) or the no-clean solder paste (typically a ROL0 or ROM0). Typical metal loading of the paste ranges from 88 to 90% solder alloy in the paste; this is approximately 50% solder paste by volume. The most common solder alloys for board assembly are the eutectic Snob solder (63Sn37Pb) and the SAC305 (95.5Sn3.0Ag0.5Cu) for the BP-free assembly. Fairchild recommends that solder pastes with a no-clean flux should be used in the board assembly of the PQFN packages. Because of the low standoff heights of the solder joints; there will be difficulty in cleaning the trapped flux residues under the package. Stencil Aperture and Thickness The recommended stencil aperture design for the PQFN 8 x 8 Dual Cool package is shown below. Figure 6. Stencil Aperture Design for Solder Paste Printing (Dimensions provided are in millimeters) Figure 7. Sample Photo of Printed Solder Paste The aperture for the leads and exposed die pad are relatively smaller than the board pads. The aperture size for the exposed die-attach pad or drain connection of the package is approximately 40 to 60% of the corresponding board land pad size, while the apertures for the pins 1 to 4 is approximatley 80% of the corresponding board land pad. The apertures on the leads are smaller than the pads. The apertures for the leads are made smaller to balance the thickness of the resulting solder joint from the exposed die pad, while still providing sufficient volume to form toe fillets. The recommended stencil thickness is mm (5 mils). The relatively small solder paste print coverage for the exposed pad of the PQFN package is based on the study conducted on several pastes from different vendors and different solder paste print coverage for the exposed pad. The result was that each of these pastes reacts differently to reflow. One paste was found to outgas much more than the other pastes. Large print coverage for this kind of solder paste on the board pad can create several defects in the assembly. While a relatively small paste volume results in insufficient solder coverage and voids. (a) (b) Figure 8. Common defects observed due to excessive solder on the exposed pad board connection. (a) Solder beading at the periphery of the package, (b) X-ray image of squeeze ball Rev /27/16 3

5 Figure 9. Board Mounted PQFN 8 x 8 Dual Cool Package An investigation on the cause of these defects revealed that the out gassing of the flux during reflow either pushes the pastes or the molten solder outwards from the pad. As a result, the solder that goes outside the pad create solder beads either in the periphery or under the package. At times, this excess solder may add or pull out some solder from the adjacent leads, creating an imbalance in the solder volume between leads leading to a tilted package or solder bridging. In the above recommended aperture, the aspect and area ratios were calculated and these are found to be above the typical minimum acceptable value for a laser cut stencil. The formulae for area and aspect ratios are below: Aspect Ratio = Area Ratio = The generally accepted aspect ratio and area ration for the laser cut stencil are >1.5 and >0.66, respectively. Tapering or trapezoidal opening of stencil holes are recommended, because this improves the solder paste released during paste printing. Electro-polishing a laser cut stencil is also recommended to have a better solder paste release. Using electroformed stencils is also recommended because of its excellent release performance. The drawback for the electroformed stencil is its cost; this is significantly more expensive than a laser cut stencil. Component Placement Width of Aperture Thickness of Stencil Foil Area of Pad Area of Aperture Wall Depending on the placement accuracy of the pick-and-place machine, the PQFN packages can tolerate up to a certain amount of placement offset to have an acceptable solder joint. Simulations done revealed that the PQFN package can allow placement offset up to 50% of its land pad width. This is about 0.50 mm offset. In this situation, the package can re-align itself with the board land pad during solder reflow. Placement height or pressure should be taken into consideration during component placement on the board. Compressing the printed paste between the component and the board, results in the paste being spread out on the land pad area. This is especially true on the exposed area where large paste volume is deposited. The compressed paste narrows down the paths for solder paste to outgas during reflow, which can lead to defects like beading. It is recommended that the placement height is controlled. Some component mounters have the capability to control the height or the amount of mounting force during component placement. The height to use should be sufficient to allow enough adhesion of the component to the paste, not to allow it to fall off during transport to the reflow oven. Reflow Process and Component Moisture Sensitivity The temperature profile to use during reflow of the PQFN package should be based on the recommended temperature profile of the solder paste vendor. However, care must be taken not to expose the package to temperatures higher than 260 C. This package is tested and qualified to perform reliably up to 3 reflow passes at the maximum reflow peak temperature of 260 C according to the IPC / JEDEC J-STD Thermocouple locations should be taken into consideration when creating the reflow profile for the board. Due to variation in the component sizes, number of components on every area of the board, and board design, there will be variation in the thermal masses on the board. This results to wide temperature gradient across the board. It is important, that thermocouples should be placed on areas wherein the temperature sensitive components are placed and on areas where high thermal masses exists. This guarantees that the components on these areas are exposed to the right reflow temperatures. Fairchild s Application Note, AN-7528, provides guidelines on the different reflow methodologies for surface mount devices. Critical conditions that could affect the components on the board and the appropriate temperature profile for each reflow technology are presented. The PQFN package is tested to meet moisture sensitivity level 1 at 260 C peak reflow temperature per IPC/JEDEC J-STD-020, thus, baking of this component prior to the assembly process is not necessary. Rev /27/16 4

6 Figure 10. Typical Reflow Temperature Profile Board Assembly Considerations by Wave Soldering Wave Soldering Process The basic process flow for wave soldering is illustrated below. Adhesive is applied on the board before component placement. The adhesive should be sufficiently tacky to hold the component during transport to the curing station. The adhesive is then cured by subjecting the assembly to an elevated temperature environment (depending on the curing requirement of the adhesive). The board is flipped upside down so that the mounted component is at the bottom side of the board as it goes through the wave soldering system. Flux is applied to the board, preheated to activate the flux and goes through to two solder waves with temperature set according to the soldering temperature of the alloy being used. Figure 11. Wave Soldering Process Flow Board Land Pad Design In wave soldering a PQFN, the land pad coverage should be extended and be made larger than the nominal package land pad being used in SMT reflow assembly. This is to allow the liquid solder from the wave to have a path to flow through, from the tip of the land pad and into the terminals at the bottom of the component. The recommended design for the PQFN 8x8 Dual Cool package has a longer lead land pad. Below is the recommended land pad design for wave soldering the PQFN 8 x 8 Dual Cool package. Figure 12. Land pattern Design for PQFN 8 x 8 Dual Cool Package Wave Soldering (Dimensions are in millimeters) Rev /27/16 5

7 Component orientation with respect to the direction of the wave soldering conveyor is critical to get a good soldering result. This is illustrated in Figure 13; the lead land pad layout is aligned with the movement of the conveyor. This component orientation with respect to conveyor movement will prevent formation of solder bridging, solder skipping or shadowing. Conveyor direction during wave soldering Printed adhesives Land pad pattern PQFN 8x8 Dual Cool Package Figure 13. Overlaid PQFN 8 x 8 Dual Cool Package on the Board Land Pad and the dispensed Adhesive Adhesive In wave soldering PQFNs, the adhesive must be chosen appropriately to ensure that this will hold the component through the whole wave soldering process flow. It must be tacky enough after print that the component won t move or fall off during transport from component placement to cure. It must have good adhesion strength after cure to prevent it from falling off during the wave soldering process, from flux spray, preheating up to wave soldering. The wet adhesive must also maintain its consistency in continuous printing or dispensing process. Adhesive print for PQFN 8 x 8 Dual Cool package is shown above. Printing the adhesive instead of dispensing is recommended to achieve better planarity and consistency in volume. The amount of printed adhesive should be applied sufficiently. Too little adhesive may not be able to hold the component well during placement and wave soldering. On the other hand, too much adhesive may spread up to the land pads during placement; this can cause solder non-wetting to the component leads and board pads. Adhesive must be cured according to the curing conditions recommended by the supplier. It must be assured that the adhesive is fully cured before wave soldering. The recommended stencil thickness for adhesive printing is 6mils. Solder Flux Flux selection is important in wave soldering. For PQFN and other components with recessed areas for soldering, solder flux with low solid content is preferred; because of its low viscosity, it can easily wicks up solderable pads under the component, flowing under the narrow space in between the component and the board by capillary action, and facilitating solder wetting during wave soldering. This flux can either be applied by spray or foaming. No-clean type solder flux is recommended. With the absence of standoff of the PQFN package and narrow spaces in between the component and the board, it is difficult to remove the trap solder residues in these areas in board cleaning, thus flux materials with low corrosive contents is preferred. Wave Solder Profile A standard wave soldering machine usually consists of the fluxing zone, preheating zone, soldering zone and cooling zone. Preheat temperatures and the preheating time should be set according to the flux specification. Too high temperature and too long preheat time may break down the flux activation systems which causes shorts/icicles. While long preheating results to oxidation of the board pad, thus preventing proper soldering and results to voids. On the other hand, too low preheat temperatures may cause skips or unwanted residues left on the PCB. Dual wave soldering is becoming common in the industry. A typical dual wave soldering profile is shown in the illustration below. The 1st wave which has turbulent wave crest ensures wetting of all the land pads allowing the molten solder to find its way to all joints on the PCB. The 2nd wave which has a laminar solder flow drains out the excess solder from the board after the 1st wave. This removes the excess solder and levels up the solder joint of every lead. The solder bath temperature must be 20 to 30 C higher than the liquidus temperature of the solder alloy for effective soldering, however, this must be lower than the maximum soldering temperature specified for this package (260 C). The wave soldering profile (preheat ramp rate, speed, peak temperature) would depend on the wave soldering equipment and the materials used. The devices used in the wave soldering study of the PQFN 8 x 8 Dual Cool are the FDMT800150DC and FDMT800152DC. The FDMT800150DC has a silicon die size of 6 x 4.42 mm, the current biggest qualified die on the PQFN 8 x 8 Dual Cool. Figure 14. Typical Dual Wave Solder Profile Rev /27/16 6

8 Inspection of Board Mounted PQFN 8x8 Dual Cool Package Inspection of the mounted component should be done with the use of 10-20x magnification scope and transmission or laminograph x-ray. A well-reflowed solder joint shows evidence of wetting and adherence wherein the solder merges to the soldered surface forming a contact angle of 90. The solder joints should normally have a smooth appearance. On certain occasions, a matte, dull or grainy solder joints may appear. This can be due to the solder alloy used, the component termination or board pad surface finish, or the soldering process used. IPC-A-610 provides the inspection methodology and acceptance criteria for this package. For the wave soldering process, the assembly is prone to solder bridging, skips, icicles and other solder joint defects. It is proper to set controls in inspecting the solder joints especially that the leads and drain are not exposed for this type of package. Controls can be done visually and through x-ray inspection. The images below show the top view of the PQFN 8 x 8 Dual Cool package that has gone through wave soldering. The solder coverage at the drain and flat pin areas of the mounted unit can t be inspected visually since it s not exposed. The appropriate method for this is through x-ray imaging to check the solder coverage between the land pad and the bottom terminations of the component. Figure 15. Wave Soldered Power88 Destructive inspection such as cross-sectioning may be performed for sample monitoring during the development stage. With this, soldering coverage can be verified. Because of the exposed solderable clip on the top of the PQFN 8 x 8 Dual Cool package, a solder mound is formed on the top of the package during wave soldering. The height of the mound can add up about 0.8 mm to the PQFN 8 x 8 Dual Cool package total thickness. This can be an issue if heat dissipating components or heatsinks need to be attached on top of the PQFN 8 x 8 Dual Cool package. One solution to this is to use soft and thick thermal interface materials, such as gap filler sheet or gap filler gel, which easily conforms to the shape of the component. Gap filler sheet with thickness over 1 mm is commonly available in the market. Solder Mound PQFN 8x8 Dual Cool Solder Joint PCB Figure 16. Cross-Section of the Wave Soldered PQFN 8 x 8 Dual Cool Package Rev /27/16 7

9 Rthja, C/W AN-4187 Heat Sink Application One unique advantage of the PQFN packages is its low Rthjc because of the directly bonded silicon die on the exposed drain pad of the package. This allows heat to dissipate efficiently from the die to the printed circuit board. Exposing the clip on top of the PQFN 8 x 8 Dual Cool package gives additional benefits by allowing the heatsink to be attached on to it and further improve the thermal performance. The design of the PQFN 8 x 8 Dual Cool package allows top and bottom cooling, giving better thermal performance than other SMT packages for power applications. On the thermal characterization of PQFN 8 x 8 Dual Cool package, there is significant improvement in the thermal resistance from junction to ambient if the Cu registration on the printed circuit board is increased from a minimum pad to a 1 in 2 Cu connected to the solder-mask-defined land pad. Depending on the size of the heatsink to use on top of the package and presence of air flow, the thermal resistance can still be further improved. Thermal Resistance, FDMT800150DC (PQFN 8x8 Dualcool) No Small Large No Small Large No Small Large No Small Large Still Air Still Air Still Air Still Air Still Air Still Air 200 FPM 200 FPM 200 FPM 200 FPM 200 FPM 200 FPM Minimum Board Pad Minimum Board Pad Minimum Board Pad 1 sq inch Board 1 sq inch Board 1 sq inch Board Minimum Board Pad Minimum Board Pad Minimum Board Pad 1 sq inch Board 1 sq inch Board 1 sq inch Board (a) (b) (c) (d) (e) Figure 17. Thermal characterization on PQFN 8 x 8 Dual Cool package,(a) Result summary of thermal characterization, (b) Board with 1 in 2 Cu trace connected to the drain, (c) Board with minimum Cu pads, (d) Large Al heatsink 45.2x41.4x12.7 mm, Aavid thermalloy Part # 10-L4LB-11, and (e) Small Al heatsink 20.9x10.4x12.7 mm. Rev /27/16 8

10 Assembly with Heat Sinks There are various types of heatsinks available in the market. The design, form, and mechanism for thermal dissipation vary depending on the application and on the amount of heat that needs to be dissipated. The method of attachment also vary, as these can either be by solder anchoring, push pin, thermal tape, screwing, or application of glue or adhesive. Thermal interface materials are being used to improve the contact between the component and the heatsink. Given the rough surfaces of the component and the heatsink, there will be air gaps in the interface that will limit heat dissipation. The use of thermally conductive interface material fills this gap, thus, improving heat transfer from the package to the heat dissipating component. Thermal interface materials or TIM comes in a lot of forms depending on the method of application; these can be electrically conductive or isolative. Typical TIMs include the following: Thermal Grease Insulating Pad Phase-change Materials Thermal Tape Gap Filler Sheet or Gel Thermally Conductive Glue or Adhesives For a heatsink attachment using thermally conductive adhesive or glue, the basic process flow is illustrated below. Figure 18. Basic Assembly Flow with using Glue or Adhesive The pattern of the dispensed glue could be a single large dot or by an X-mark done by writing. The heatsink can be manually placed on top of the component. This can also be run in automated assembly using a pick-and-place mounter like the Yamaha YC8 mounter. Specialized pick up nozzle is required and designed according to the form of the heatsink. Depending on the tackiness of the adhesive being used, pressure may be required during heatsink placement. This will hold the heatsink in place during transport for the mounter to the curing station. Application of Pressure on the Component In certain heatsink applications, pressure may be applied on the component. Such applications where tightening a screw, a push pin, or a solder anchor is used to secure the heatsink, a compression load is placed on the component. The PQFN 8 x 8 Dual Cool package has been tested and simulated to withstand high amount of compression load. In the test conducted, the package can withstand up to 1500 N of load without causing any electrical or mechanical failure. Figure 19. Typical Dispensed Pattern of Thermally Conductive Adhesive on the Component Figure 20. Pick-and-Place Nozzle from Yamaha Motors Co., Ltd. and Placement Rev /27/16 9

11 General Rework Guideline PQFN Packages The recommended board rework methodology for this package is as follows. Step Tools / Equipment Guideline / Procedure Baking Component Removal Land Preparation Component installation Inspection Oven Rework Station Heat gun Solder Wick, Soldering Iron, Continuous Vacuum, Desoldering System, Desoldering Tip Mini Stencil, Solder Paste Dispenser, Low Magnification Microscope, Pick and Place Machine, Reflow Oven X-ray Machine, Low Magnification Microscope Baking of the board assembly may be necessary depending on the moisture sensitivity of the board and the other surrounding components. The purpose is to eliminate absorbed moisture on these parts, and prevent the damaging effects when subjected to sudden ramp of temperature during removal of the component. Secure the board on the rework station. Preheat the whole board to minimize warpage of the board when high temperature is applied on the component to be removed. Apply heat into the component using a heat gun, once the solder joint has melted; remove the component immediately using a vacuum nozzle. It is important to take note that applying too much heat on the board can also affect the surrounding components, thus it is important to do this process quickly. It is also important not to expose the PQFN package to too much heat so as not to damage the component. This will help us understand failure mechanism should this component be returned to us for analysis. After the component is removed, remove excess solder left on the lands using a continuous vacuum desoldering system and soldering tip. Soldering iron and solder wicking material can also be used to do this. After preparing the lands, install a new component into the board. The old component should not be used. Installation of the new component follow these steps: Solder paste printing/dispensing screen print solder paste on the lands. Use a mini stencil to do this. The stencil should have the same aperture size and thickness with the one used in the whole board assembly. A solder paste dispensing system can also be used to put paste on the lands. Inspection perform inspection to check if sufficient paste is printed on the board. Component placement place the component onto the board either manually or the work station. Reflow reflow the board using the standard reflow profile established for the whole board assembly. Inspect the component after reflow using an X-ray machine to check solder joint anomalies like solder bridging, beading and voids. Rev /27/16 10

12 References [1] FSC-QAR-0024, Guideline on the Methodology of Board Level Characterization [2] IPC2221, IPC standard, Generic Standard on Printed Board Design [3] Board-Level Evaluation of Power Qual Flat No-Lead (PQFN) Packages, Fairchild Semiconductor Power Seminar white paper [4] ANSI/J-STD-004, IPC and EIA Joint Standard, Requirements for Soldering Fluxes [5] IPC7525, IPC Standard, Stencil Design Guidelines [6] IPC/EIA J-STD-001, and EIA Joint Standard, Requirements for Soldered Electrical and Electronic Assemblies [7] IPC-A-610, IPC standard, Acceptability of Electronic Assemblies [8] IPC-7093, Design and Assembly Process Implementation for Bottom Termination Components [9] IPC7351, IPC standard, Generic Requirements for Surface Mount Design and Land Pattern Standard [10] AN-7528, Fairchild Application Notes, Guidelines for Soldering Surface Mount Components to PC Boards [11] IPC/JEDEC J-STD-020, IPC and JEDEC Joint Standard, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [12] FSC-QAR-0006, Fairchild Semiconductor General Reliability Requirements [13] IPC9701, IPC standard, Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments [14] JESD22-B111, JEDEC standard, Board Level Drop Test Method of Components for Handheld Electronic Devices [15] JESD22-B113, JEDEC standard, Board Level Cyclic Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Devices [16] JESD22-B103, JEDEC Standard, Vibration, Variable Frequency [17] IPC/JEDEC J-STD-033, IPC and JEDEC Joint Standard, Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices [18] FDMT800150DC Fairchild Datasheet DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Rev /27/16 11

13 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor E. 32nd Pkwy, Aurora, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com Semiconductor Components Industries, LLC N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative