CODE GENERATION FOR EMBEDDED PROCESSORS

Transcription

1 CODE GENERATION FOR EMBEDDED PROCESSORS

2 CODE GENERATION FOR EMBEDDED PROCESSORS EDITED BY Peter MARWEDEL University of Dortmund Dortmund, Germany Gert GOOSSENS IMEC SPRINGER SCIENCE+BUSINESS MEDIA, LLC

3 Library of Congress Cataloging-in-Publication Data A CLP. Catalogue record for this book is available from the Library of Congress. ISBN ISBN (ebook) DOI / Copyright 2002 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 2002 Softcover reprint of the hardcover 1st edition 2002 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC. Printed on acid-free paper. This printing is a digital duplication of the original edition.

4 CONTENTS CONTRIBUTORS PREFACE 7 11 Part I REQUIREMENTS 13 1 CODE GENERATION FOR EMBEDDED PROCESSORS: AN INTRODUCTION Peter Manoedel 1 New, flexible target technologies 2 Design scenarios for embedded processors 3 Requirements for design tools 4 Related work 5 Target models for retargetable compilation 6 Summary 2 RETARGETABLE CODE GENERATION: KEY ISSUES FOR SUCCESSFUL INTRODUCTION Paul Vanoostende, Etienne Vanzieleghem, Emmanuel Rousseau, Christian Massy and Fhln~ois Gerard 1 Introduction 2 DSP-core architecture 3 Selection of the bigb-ievellanguage 4 Tool support 5 Conclusions

5 2 CODE GENERATION FOR EMBEDDED PROCESSORS 3 CHALLENGES IN CODE GENERATION FOR EMBEDDED PROCESSORS Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Liao, Sharad Malik, Ashok Sudarsanam, Steve Tjiang and Albert ",ang ~ 1 Introduction ~ 2 Retargetable code generation 50 3 Optimization techniques 52 4 Compiler organization and experimental infrastructure 61 5 Summary 64 Part II RETARGET ABLE CODE GENERATION SYSTEMS 65 4 FLEXW ARE: A FLEXIBLE FIRMWARE DEVELOPMENTE~ONMENTFOR EMBEDDED SYSTEMS Pierre G. Paulin, Clifford Liem, 7revor C. May and Shailesh Sutanuala 67 1 Introduction 67 2 INSULIN : instruction set simulation 69 3 CODESYN : retargetable code generation 75 4 Conclusion 84 5 CHESS: RETARGET ABLE CODE GENERATION FOR EMBEDDED DSP PROCESSORS Dirk Lanneer, Johan Van Praet, Augusli Kifti, Koen Schools, Werner Geurts, Filip Thoen and Gert Goossens 85 1 Introduction 85 2 Outline of the CHESS environment 87 3 Processor modelling using the instruction-set graph 91 4 A bundling technique for code selection 93 5 A data routing technique for register allocation 95 6 Global scheduling 97 7 Results 98 8 Conclusions 100

6 Contents 3 6 AN ILP-BASED APPROACH TO CODE GENERATION Tom Wilson, Gary Grewal, Shawn Henshall and Dilip Banerji Introduction Background A linear programming view of code generation Overview of the code generation system Final remarks RETARGETABLE CODE GENERATION FOR PARALLEL, PIPELINED PROCESSOR STRUCTURES Wolfgang Schenk Introduction Compiler phases Related work External machine representation Internal machine representation The code generation algorithm Conclusion 135 Part III MACHINE DESCRIPTION MODELS AND FORMAL METHODS BEYOND TOOL-SPECIFIC MACHINE DESCRIPTIONS Andreas Fauth Introduction Related work The formalism NML Applications based on NML Conclusion 152

7 4 CODE GENERATION FOR EMBEDDED PROCESSORS 9 ON TRANSFORMING CODE GENERATION TO A PARSING PROBLEM Farhad M avaddat Introduction Problem statement and approach Methodology User Experience Conclusions LOCAL MICROCODE GENERATION IN SYSTEM DESIGN Michel Langevin, Eduard Cerny, lorg Wilberg and H einrich-theodor Vierhaus Introduction An approach to codesign The problem of local microcode generation An approach for local microcode generation Conclusions CODE GENERATION BASED ON TRELLIS DIAGRAMS Bernhard Wess Introduction Target machine description by trellis diagrams Code generation by means of trellis trees Data flow graph compiler Summary and conclusions A UNIFIED CODE GENERATION APPROACH USING MUTATION SCHEDULING Steven Novack, Alex Nicolau and Nikil Dutt Introduction Related work illustration of MS Implementation and results 211

8 Contents 5 Part IV SPECIAL APPLICATIONS AND FUTURE DIRECTIONS RETARGETABLE COMPILATION OF SELF-TEST PROGRAMS USING CONSTRAINT LOGIC PROGRAMMING Ulrich Bieker Introduction Related work RESTART: REtargetable Self-Test program generation - an overview Input specification : hardware and software Retargetable code generation : techniques Results Conclusions CODE GENERATION FOR TRANSPORT TRIGGERED ARCHITECTURES Henk Corporaal and Jan Hoogerbrugge Introduction Transport triggered architectures Code generation Compiling the MCCD algorithm Improvements Conclusions SOFTWARE SYNTHESIS FOR REAL-TIME INFORMATION PROCESSING SYSTEMS Marco Comero, Filip Thoen, Gert Goossens and Franco Curatelli Introduction Existing approaches in software design System specification and synthesis script Program threads Representation model Execution model 274

9 6 CODE GENERATION FOR EMBEDDED PROCESSORS 7 Conclusions REFERENCES INDEX

10 CONTRIBUTORS Guido Araujo Princeton University Princeton, New Jersey, U.S.A. Dilip Banerji University of Guelph Guelph, Ontario, Canada Ulrich Bieker University of Dortmund Dortmund, Germany Eduard Cerny Universite de Montreal Montreal, Quebec, Canada Marco Cornero SG8-Thomson Microelectronics Crones, France Henk Corporaal Delft University of Technology Delft, The Netherlands Franco Curatelli University of Genova Genova, Italy Srioivas Devadas MIT Cambridge, Massachusetts, U.S.A. Nikil Dutt University of California Irvine, California, U.S.A. Andreas Fauth Technische Universitiit Berlin Berlin, Germany Fran~ois Gerard Alcatel Mobile Communications Colombes, France Werner Geurts IMEC Gert Goossens IMEC Gary Grewal. University of Guelph Guelph, Ontario, Canada Shawn Hensball University of Guelph Guelph, Ontario, Canada Jan Hoogerbrugge Delft University of Technology Delft, The Netherlands Kurt Keutzer Synopsys Inc. Mountain View, California, U.S.A. Augusli Kifli IMEC

11 8 CODE GENERATION FOR EMBEDDED PROCESSORS Michel Langevin GMD St. Augustin, Germany Dirk Lanneer IMEC Stan Liao MIT Cambridge, Massachusetts, U.S.A. Clifford Liem INPG Grenoble, France Sharad Malik Princeton University Princeton, New Jersey, U.S.A. Peter Marwedel University of Dortmund Dortmund, Germany Christian M888Y Alcatel Mobile Communications Colombes, France Farhad Mavaddat University of Waterloo Waterloo, Ontario, Canada Trevor C. May Bell-Northern Research Ltd Ottawa, Ontario, Canada Alex Nicolau University of California Irvine, California, U.S.A. Steven Novack University of California Irvine, California, U.S.A. Pierre G. Paulin SGS-Thomson Microelectronics Crolles, France Emmanuel Rousseau Alcatel Mobile Communications Colombes, France Wolfgang Schenk University of Dortmund Dortmund, Germany Koen Schoofs IMEC Ashok Sudarsanam Princeton University Princeton, New Jersey, U.S.A. Shailesh Sutarwala Bell-Northern Research Ltd Ottawa, Ontario, Canada Filip Thoen IMEC Steve Tjiang Synopsys Inc. Mountain View, California, U.S.A. Paul Vanoostende Alcate1-Bell Antwerp, Belgium Johan Van Praet IMEC Etienne Vanzieleghem Alcatel-Bell Antwerp, Belgium

12 Contributors 9 Heinrich-Theodor Vierhaus GMD St. Augustin, Germany Albert Wang Synopsys Inc. Mountain View, California, U.S.A. Bernhard Wess Technische Universitiit Wien Vienna, Austria Jorg Wilberg GMD St. Augustin, Germany Tom Wilson University of Guelph Guelph, Ontario, Canada

13 PREFACE Modern electronics is driven by the explosive growth of digital communications and multi-media technology. A basic challenge is to design first-time-right complex digital systems, that meet stringent constraints on performance and power dissipation. In order to combine this growing system complexity with an increasingly short time-to-market, new system design technologies are emerging based on the paradigm of embedded programmable processors. This concept introduces modularity, flexibility and re-use in the electronic system design process. However, its success will critically depend on the availability of efficient and reliable CAD tools to design, programme and verify the functionality of embedded processors. Recently, new research efforts emerged on the edge between software compilation and hardware synthesis, to develop high-quality code generation tools for embedded processors. This book provides a survey of these new developments, as presented at the First International Workshop on Code Generation for Embedded Processors. This workshop was organised at Schlofi Dagstuhl, Germany, from August 31 to September 2,1994, by the members of the Chips project (Esprit-9138). Chips is a basic research action sponsored by the European Commission, with partners : University of Dortmund, IMEC, and University of Genova. 11

14 12 The material contained in this book has been selected from the contributions presented at the workshop. Based on a thorough review and editing process, a comprehense overview of the state-of-the-art was obtained. Although not limited to these targets, the main emphasis is on code generation for modem DSP processors. Important themes covered by the book include : the scope of general purpose versus application-specific processors, machine code quality for embedded applications, retarget ability of the code generation process, machine description formalisms, and code generation methodologies. The editors would like to thank all those who helped preparing the book, in particular the members of the code generation groups at IMEC and the University of Dortmund. Peter Marwedel Gert Goossens Dortmund/Leuven