Micromachined DC contact capacitive switch on low-resistivity silicon substrate

Transcription

1 Sensors and Actuators A 127 (2006) Micromachined DC contact capacitive switch on low-resistivity silicon substrate A.B. Yu a, A.Q. Liu a,, Q.X. Zhang b, A. Alphones a, H.M. Hosseini a a School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore , Singapore b Institute of Microelectronics, 11 Science Park Road, Science Park II, Singapore , Singapore Received 9 March 2005; received in revised form 16 October 2005; accepted 7 November 2005 Available online 15 December 2005 Abstract A DC contact capacitive shunt switch on low-resistivity Si substrate is designed and demonstrated. There are two main differences between this design and the conventional capacitive shunt switch. First, the dielectric layer is fabricated on the ground planes of the coplanar waveguide (CPW) transmission line. The contact between the metal bridge and the center conductor becomes DC contact when the metal bridge is driven down. As a result, the down-state capacitance degradation problem can be solved and the down-state capacitance as high as 30 pf can be achieved. Second, the switch is fabricated on a low-resistivity silicon substrate. This is the first time where a RF MEMS switch can be fabricated on a low-resistivity silicon substrate without any wafer transfer technology; thus, it can greatly simplify the fabrication process and reduce cost. Measurement results show that the insertion loss is lower than 0.4 db until 26.5 GHz and the isolation is 15 db at 1 GHz, 26 db at 10 GHz and 27 db at 26.5 GHz. The down-state resistance and the inductance are 1.3 and 2 ph, respectively Elsevier B.V. All rights reserved. Keywords: DC contact switch; Capacitive shunt switch; CPW transmission line; RF MEMS 1. Introduction An important figure of merit qualifying the RF performance of a capacitive switch is the down/up capacitance ratio R.However, for most of the capacitive shunt switch reported to date, it is difficult to obtain capacitance ratio larger than 150 because of the down-state capacitance degradation problem, which means that the obtained down-state capacitance is much smaller than the designed value. As a result, conventional capacitive shunt switches are more suitable when frequency is higher than X- band (8 12 GHz) because it is difficult to obtain larger than 15 db isolation at lower frequency range [1]. To obtain high isolation in or lower than X-band, one method is to use inductively tuned capacitive switches by properly choosing the LC resonant frequency; however, the bandwidth of this design is narrow because of the large down-state inductance in the circuit [2]. Another method is to use dielectric material with high dielectric constant, such as strontium titanate oxide Corresponding author. Tel.: ; fax: address: eaqliu@ntu.edu.sg (A.Q. Liu). (STO) with a relative dielectric constant ranging between 30 and 120 [3]. Large capacitance ratio of 600 is obtained, and higher than 30 db isolation can be achieved at 2 GHz. However, the STO material is not a commonly used material in MEMS fabrication process, and the down-state capacitance is greatly degraded as the designed capacitance ratio is larger than The down-state capacitance degradation problem is caused by the non-planar metal bridge, roughness of the contact area and the etching hole in the metal bridge etc. [4]. To avoid this problem, a switched-capacitor approach can be used [5,6], in which a metal insulator metal (MIM) capacitor is defined between the bridge and the coplanar waveguide (CPW) center conductor. This results in a capacitance ratio that is independent of the roughness of the bottom electrode. However, in this design, the MIM capacitor is defined on the CPW center conductor, therefore, its capacitance value is limited by the width of the CPW center conductor. Another problem in most recently reported capacitance shunt switches is that in order to reduce substrate loss, these switches need to be fabricated on low loss substrates, as done on highresistivity silicon substrates, glass or quartz substrates, or to use wafer transfer technique [7]. Either method has its respective /$ see front matter 2005 Elsevier B.V. All rights reserved. doi: /j.sna

2 A.B. Yu et al. / Sensors and Actuators A 127 (2006) shortcoming(s). For instance, the silicon, glass or quartz substrates are more expensive compared to the low resistivity silicon substrate, whereas use of the wafer transfer technique will complicate the fabrication process. The objective of this paper is to develop a DC contact capacitive shunt switch without down-state capacitance degradation problem, and to use low resistivity silicon as substrate without any wafer transfer process. First, the design of the capacitive switch with the dielectric layer patterned on the ground planes of the CPW is presented. It is shown that by shifting the dielectric layer onto the ground planes of the CPW transmission line, the down-state capacitance degradation problem can be avoided and high capacitance ratio can be obtained. It is also shown that by properly selecting the dimensions of the CPW transmission line, it is feasible for this switch to be fabricated on a low-resistivity silicon wafer. Second, the fabrication process of this switch is proposed, a SiO 2 layer with thickness of 18 m is deposited on the silicon substrate as isolation layer. Finally, the measurement results are presented and discussed. 2. Switch design and modeling 2.1. Design of DOG switch Fig. 1 shows a schematic diagram of the newly designed switch. In this design, the dielectric layer is fabricated on the Fig. 2. Equivalent circuit of DOG switch. CPW ground planes instead of the CPW center conductor. The metal bridge, the dielectric layers and the CPW ground planes consist of two MIM capacitors in shunt connection. Because of the nature of its construction, this newly designed switch is referred as dielectric-on-ground (DOG) switch while the conventional capacitive switch is referred as dielectric-on-center conductor (DOC) switch in this paper. Fig. 2 shows the equivalent circuit of the switch. In the upstate position, the switch capacitance Cu DOG is dominated by the parallel-plate capacitance C pp between the metal bridge and the CPW center conductor, that is: C DOG u = C pp = ε 0A 1 g + t d /ε r = ε 0 A 1 g where A 1 is the overlap area between the metal bridge and the CPW center conductor and A 1 = ww with w is the width of the metal bridge and W is the width of the CPW center conductor. While in the down-state, the DC-contact between the metal bridge and the CPW center conductor results in an R s L model in series with MIM capacitors. Therefore, the down-state capacitance of the switch Cd DOG is dominated by the capacitance of the MIM capacitor C MIM, that is: (1) Cd DOG = C MIM = ε 0ε r A 2 (2) t d where A 2 is the total area of the MIM capacitor and A 2 = 2wW d with W d is the width of the MIM capacitor. Therefore, the capacitance ratio of this DOG switch can be expressed as: Fig. 1. Schematic diagram of the DOG capacitive switch: (a) 3D view; (b) top view; (c) cross section view. r = CDOG d Cu DOG = ε rg A 2 A 2 = r 0 (3) t d A 1 A 1 where r 0 = ε rg t d is the capacitance ratio for the DOC switch. From Eq. (3), for the DOG switch, high capacitance ratio can be obtained by increasing A 2 /A 1, which gives a new degree of freedom to optimize the switch design, and no down-state capacitance degradation problem would occur. This is one of the advantages from this DOG switch. It is interesting to note that since the MIM capacitor is defined on the ground planes of the CPW transmission line, the width of the CPW slots can be reduced to 20 m or narrower while the characteristic impedance Z 0 of the CPW transmission line can still be maintained as 50 by properly selecting the width of the

3 26 A.B. Yu et al. / Sensors and Actuators A 127 (2006) center conductor. The narrow slots and the center conductor do not have any problem in obtaining large down-state capacitance since the MIM capacitor is fabricated on the ground planes; instead, it becomes possible for this switch to be fabricated on a low-resistivity silicon substrate. This is another advantage from this DOG switch Design of CPW transmission line To reduce the attenuation of transmission line on the lowresistivity silicon substrate, a thick SiO 2 layer can be deposited on it as isolation layer. When the thickness of the SiO 2 layer is larger than the width of the CPW slot, the attenuation of the CPW transmission line fabricated on the low-resistivity silicon substrate is comparable to that of the CPW transmission line fabricated on the high resistivity silicon substrate [8]. With a thick SiO 2 layer as isolation layer, the characteristic impedance of the CPW line can be calculated as [9]: Z 0 = 30π K(k 0 ) (4) εeff K(k 0 ) where ε eff = 1 + ε r1 1 K(k 1 ) K(k 2 K(k 1 0 ) ) K(k 0 ) + ε r2 ε r1 K(k 2 ) K(k 2 K(k 2 0 ) ) K(k 0 ) (5) k 0 = k 1 = k 2 = W W + 2G sinh [πw/4(t 1 + t 2 )] sinh {[π(w + 2G)]/4(t 1 + t 2 )} sinh (πw/4t 2 ) sinh {[π(w + 2G)]/4t 2 } (6a) (6b) (6c) k n 1 = kn 2, n = 0, 1, 2 (6d) K is the first kind complete elliptic integrates, ε eff the effective dielectric constant, Z 0 the characteristic impedance, ε r1 the dielectric constant of silicon and is equal to 11.9, ε r2 is the dielectric constant of SiO 2 and is equal to 4.1. t 1 and t 2 are the thickness of the silicon substrate and the thickness of the SiO 2, respectively. Based on Eqs. (4) (6), a50 CPW transmission line is designed with dimensions of G/W/G = 10/50/10 m. The substrate used here is low-resistivity ( cm) silicon substrate with thickness of 725 m. A layer of SiO 2 with thickness of 18 m is deposited on the substrate as isolation layer. The dimensions of the DOG switch are listed in Table Electromagnetic modeling of DOG switch In the up-state position, the RF performance of the DOG switch is almost the same as that of the DOC switch. The insertion loss is dominated by the transmission line loss. Table 1 Design parameters of the DOG capacitive switch Design parameters Values Bridge width w ( m) 100 MIM area A 2 ( m 2 ) CPW center conductor width W ( m) 50 CPW slot width G ( m) 10 Initial metal bridge height g ( m) 2 Metal bridge thickness t b ( m) 1.2 SiO 2 layer thickness t ( m) 18 Space between bridge anchor and CPW ground ( m) 165 Dielectric layer thickness t d ( m) 0.15 Dielectric constant of SiN 7 In the down-state position, the RF performance can also be analyzed in the same way as that of the DOC switch. However, it should be noted that in the DOG switch, as the contact between the metal bridge and the CPW center conductor becomes DC contact, the down-state resistance R s should include both the metal bridge resistance and the contact resistance, thus, its value is around for most of the design, this will limit the highest isolation to db. The contact resistance depends on the size of the contact area, the mechanical force applied and the quality of the metal-to-metal contact. The down-state isolation can be expressed as: 2Z b S 21 = (7) 2Z b + Z 0 where Z 0 is the characteristic impedance of the CPW transmission line, Z b is the impedance of the metal bridge and can be expressed as: ( Z b = R s + j ωl ) 1 ωcd DOG Fig. 3(a) shows how the isolation changes with the down-state resistance R s, and the frequency. The down-state capacitance and inductance are assumed to be 31 pf and 5 ph, respectively. It is observed that when R s < 0.5, the peak of the isolation can be seen clearly at the LC resonant frequency f 0 = 12.4 GHz. The highest isolation can be expressed as: S 21 = 2R s Z 0 (9) It is also interesting to note that when R s > 0.8, the isolation just changes a little with frequency f > 10 GHz and its value is mainly determined by the inductance of the switch. Fig. 3(b) shows how the isolation changes with the inductance L, and the frequency. The down-state capacitance and the resistance are assumed to be 31 pf and 1, respectively. It is observed that when the inductance is larger than 5 ph, the isolation increases quickly when the frequency is higher than 10 GHz. Combining Fig. 3(a) and (b), it can be concluded that in order to achieve at least 20 db isolation till 40 GHz, the inductance and the resistance should be lower than 10 ph and 2, respectively. (8)

4 A.B. Yu et al. / Sensors and Actuators A 127 (2006) Table 2 USG deposition parameters Parameters Value N 2 O gas (sccm) 300 SiH 4 gas (sccm) 9500 Carrier gas N 2 (sccm) 50 RF Power (W) 800 Pressure (Torr) 2.2 Temperature ( C) 400 Deposition time (min) 36 is the same as that in the DOC shunt switch. This implies that for a DOG shunt switch, the down-state inductance is also mainly determined by the portion of the metal bridge over the CPW slots. Therefore, if the dimensions of the CPW slot are reduced, the inductance of the switch can also be reduced. 3. Fabrication of DOG switch Fig. 3. Variation of isolation with: (a) frequency and resistance; (b) frequency and down-state inductance. Smaller inductance is also helpful to increase the isolation in the high frequency range. Fig. 4 shows the simulated current distribution of the switch in the down-state. The software used here is high frequency structure simulator (HFSS) from Ansoft [10]. It can be seen that in the down-state, the current is mainly concentrated on the front edge of the metal bridge portion that is over the CPW slot. This As mentioned above, the DOG switch is fabricated on a lowresistivity ( cm) silicon substrate. In total, five masks are needed and the fabrication flow is given in Fig. 5. First, a layer of 18 m PECVD undoped-silica-glass (USG) is deposited as isolation layer (a); then 300 Å/1 m Ti/Au is deposited and patterned as CPW transmission line (b); after CPW patterning, a layer of 0.15 m PECVD SiN is deposited and patterned as dielectric layer on the CPW grounds and isolate the pull down electrodes (c); a layer of 2 m photoresist is coated and patterned as the sacrificial layer (d); then a layer of 0.2 m aluminum is evaporated and patterned as hardmask (e); to form the dimple, a layer of 0.5 m photoresist is etched away in the sacrificial layer using reactive ion etching (RIE) with O 2. The Al is removed by wet etch process. Each switch has two dimples with diameter of 25 m (f); another 1 m Al is evaporated and patterned as metal bridge (g); at last dry release metal bridge using RIE with O 2 (h). In this process, the 18 m thick USG deposition is a critical step. The deposition is processed using NOVELLUS PECVD machine, and the deposition parameters are listed in Table 2. The residual stress is controlled to be below 40 MPa, so that the following fabrication steps will not be affected. The SEM micrograph of the DOG switch is shown in Fig Experimental results and discussions Fig. 4. Simulated current distribution of the DOG switch in the down-state position. The RF performance of the switch is characterized using an HP8510C vector network analyzer and RF probe station. A full Thru-Reflect-Line (TRL) routine is used to calibrate with NIST software MULTICAL. A 35 V DC bias voltage is applied between the metal bridge and the CPW ground to driven the metal down during the RF measurement. Fig. 7(a) shows the measured and curve fitted results in the upstate position. The extracted up-state capacitance is 30 ff and the insertion loss is lower than 0.4 db upto 26.5 GHz. The insertion loss is mainly determined by the loss of the CPW transmission line, which is same as that in the DOC capacitive switch. Fig. 8

5 28 A.B. Yu et al. / Sensors and Actuators A 127 (2006) Fig. 5. Fabrication process flow of DOG switch. shows the measured insertion loss of the CPW transmission lines used in the DOG switch. It is observed that the loss varies from 0.15 to 0.3 db as the frequency is lower than 26.5 db. Therefore, it is predicted that the insertion loss results from the up-state capacitance is 0.1 db. Fig. 7(b) shows the measured and curve-fitted results in the down-state position. It is observed that the isolation is 15 db at 1 GHz, 26 db at 10 GHz and 27 db at 26.5 GHz. The extracted down-state capacitance is 30 pf at 1 GHz. The designed down- state capacitance is 31 pf. The small difference between the extracted value and the calculated value can be attributed to the fabrication and measurement error. Therefore, it can be concluded that the down-state capacitance degradation problem can be avoided for this DOG switch. The experimental capacitance ratio is This ratio is much larger than that of the DOC switch, which is around 150 at most. The extracted down-state resistance and inductance is 1.3 and 2 ph, respectively. Table 3 lists out the RF performances and the extracted RLC values for this DOG switch. Table 3 RF characteristics and extracted RLC values Up-state Down-state Return loss (db) 1 GHz GHz GHz Isolation (db) 1 GHz GHz GHz Capacitance (pf) a Inductance (ph) 2 Resistance ( ) 1.3 Fig. 6. SEM microphoto of DOG capacitive switch. a The capacitance is extracted at 1 GHz.

6 A.B. Yu et al. / Sensors and Actuators A 127 (2006) is as large as 30 pf is obtained. This ensures that the isolation is higher than 20 db from 2 to 26 GHz. Second, the switch configuration can be fabricated on low-resistivity silicon substrate where the width of the CPW slot is only 10 m. Therefore, this design does not only reduce the cost of the substrate, but also reduces the inductance of the switch, which results in higher isolation in the frequency band higher than 10 GHz. Capacitance ratio up to 1000 and small inductance imply that the DOG switch has the potential of keeping the isolation higher than 20 db till 40 GHz. References Fig. 7. Measurement and curve-fitted results. [1] J.J. Yao, RF MEMS from a device perspective (Topic Reviews), J. Micromech. Miroeng. 10 (2000) [2] J.B. Muldavn, G.M. Rebeiz, High-isolation inductively-tuned X-band MEMS shunt switches, 2000 IEEE MTT-S Int. Microwave Symp. Dig. (2000) [3] J.Y. Park, G.H. Kim, K.W. Chung, J.U. Bu, Monolithically integrated micromachined RF MEMS capacitive switches, Sens. Actuators A: Phys. 89 (2001) [4] A.B. Yu, A.Q. Liu, Q.X. Zhang, A. Alphones, L. Zhu, S.A. Peter, Improvement of isolation MEMS capacitive switch via membrane planarization, Sens. Actuators A: Phys. 119 (2005) [5] X. Rottenberg, S. Brebels, W. De Raedt, B. Nauwelaers, H.A.C. Tilmans, RF power: driver for electrostatic RF MEMS devices, J. Micromech. Microeng. 14 (2004) s43 s48. [6] X. Rottenberg, P. Fiorini, W. De Raedt, H.A.C. Tilmans, Novel RF MEMS capacitive switching structures, in: Proceedings of the EUMW, Milan, Italy, 2002, pp [7] K.F. Harsh, W. Zhang, V.M. Bright, K.C. Lee, Flip chip assembly for Si-based RF MEMS, in: Proceedings of the 12th IEEE International Conference on Microelectromechanical Systems, January, 1999, pp [8] J.N. Burghartz, D.C. Edelstein, Spiral inductors and transmission lines on silicon technology using copper-damascene interconnects and lowloss substrates, IEEE Trans. Microwave Theory Tech. 45 (1997) [9] R.N. Simons, Coplanar Waveguide Circuits, Components, and Systems, Wiley, New York, [10] Ansoft High Frequency Structure Simulator, Release , Ansoft Corporation, Biographies A.B. Yu received BE degree in Materials Science in 1993 from Shanghai Jiaotong University and ME degree in Electronic Material and Device in 1996 from Shanghai Jiaotong University. Currently, he is a Research Associate in the Division of Microelectronics, School of Electrical and Electronic Engineering, Nanyang Technological University. He is currently pursuing his PhD in the school. His research interests include Microfabrication process, RF MEMS design. Fig. 8. Insertion loss of CPW line used in the DOG switch. 5. Conclusions A DC contact capacitive shunt switch is designed, fabricated and characterized in this work. Two main advantages are achieved. First, the down-state capacitance degradation problem is avoided successfully and the down-state capacitance, which A.Q. Liu received his PhD in Applied Mechanics from National University of Singapore in His MSc was in Applied Physics and BE was in Mechanical Engineering from Xi an Jiaotong University in 1989 and 1982, respectively. Currently, he is an Associate Professor at the Division of Microelectronics, School of Electrical and Electronic Engineering, Nanyang Technological University. He is also an Associate Editor of the IEEE Sensor Journal. His research interests are MEMS design, simulation and fabrication processes. Q.X. Zhang received his BS degree and ME degree in semiconductors devices and physics from Harbin Institute of Technologies, China in 1986 and 1989, respectively. He received his PhD in microelectronics from the Institute of Microelectronics, Tsinghua University in He has been working in

7 30 A.B. Yu et al. / Sensors and Actuators A 127 (2006) Institute of Microelectronics on microsensors and MEMS since His major interests are MEMS design, simulation and process development. A. Alphones received PhD degree in Optically Controlled Millimeter Wave Circuits from Kyoto Institute of Technology, Japan, in Currently, he is an Associate Professor at the School of Electrical and Electronic Engineering, Nanyang Technological University. He is in the editorial review board of IEEE Microwave Theory and Techniques and Microwave and Wireless Components Letters. He has published and presented over 100 technical papers in International Journals/Conferences. His current interests are electro-magnetic analysis on planar RF circuits and integrated optics, EMC testing, microwave photonics, and hybrid fiber-radio systems. He received IEEE AES/Comm Chapter award 1986 in the area of communications. He had written a chapter on Microwave Measurements and Instrumentation in Wiley Encyclopedia of Electrical and Electronic Engineering He is a Senior Member of IEEE. H.M. Hosseini received his BE in Electronic Engineering from Isfahan University of Technology, Iran, in 1988, his MSc in Digital Electronics from Sharif University of Technology, Iran, in 1991, and his PhD in Electrical Engineering from the Adelaide University, Australia, in From 1988 to 1992, he was working at the Iranian Telecommunication Research Centre (ITRC) as a design engineer, where he developed software packages for digital circuits simulation. In December 1997, he joined Network Technology Research Centre (NTRC), School of EEE, Nanyang Technological University of Singapore as a research staff. In NTRC, he was involved in various networking projects, including a test system for ATM signaling interoperability. On August 2000, he joined school of Electrical and Electrical Engineering of NTU as an Assistant Professor. His research interests include multimedia security, video and image watermarking, E-Learning models, and pattern recognition.