KAI (H) x 3264 (V) Interline CCD Image Sensor

Transcription

1 KAI (H) x 3264 (V) Interline CCD Image Sensor Description The KAI Image Sensor is a 16 megapixel CCD in an APS H optical format. Based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, the sensor features broad dynamic range, excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs for full resolution readout up to 8 frames per second. A vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. The sensor is available with the TRUESENSE Sparse Color Filter Pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color Bayer part. The sensor shares common PGA pin out and electrical configurations with other devices based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, allowing a single camera design to be leveraged to support multiple members of this sensor family. Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Interline CCD; Progressive Scan Total Number of Pixels 4964 (H) x 3332 (V) Number of Effective Pixels 4920 (H) x 3288 (V) Number of Active Pixels 4896 (H) x 3264 (V) Pixel Size 5.5 m (H) x 5.5 m (V) Active Image Size mm (H) x mm (V) mm (diag.) APS H Format Aspect Ratio 3:2 Number of Outputs 1, 2, or 4 Charge Capacity 20,000 electrons Output Sensitivity 34 V/e Quantum Efficiency Pan ( AXA, QXA, PXA) R, G, B ( FXA, QXA) R, G, B ( CXA, PXA) Read Noise (f = 40 MHz) Dark Current Photodiode VCCD Dark Current Doubling Temp. Photodiode VCCD 43% 28%, 35%, 38% 29%, 35%, 37% 12 electrons rms 2 electrons/s 140 electrons/s 7 C 9 C Dynamic Range 64 db Charge Transfer Efficiency Blooming Suppression > 300 X Smear Estimated 100 db Image Lag < 10 electrons Maximum Pixel Clock Speed 40 MHz Maximum Frame Rates Quad Output Dual Output Single Output Package Cover Glass 8 fps 4 fps 2 fps 72 pin PGA AR coated, 2 Sides Figure 1. KAI CCD Image Sensor Features Bayer Color Pattern, TRUESENSE Sparse Color Filter Pattern, and Monochrome Configurations Progressive Scan Readout Flexible Readout Architecture High Frame Rate High Sensitivity Low Noise Architecture Excellent Smear Performance Package Pin Reserved for Device Identification Applications Industrial Imaging and Inspection Traffic Security ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. NOTE: All parameters are specified at T = 40 C unless otherwise noted. Semiconductor Components Industries, LLC, 2015 August, 2015 Rev. 7 1 Publication Order Number: KAI 16050/D

2 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description Marking Code KAI AXA JD B1 KAI AXA JD B2 KAI AXA JD AE KAI FXA JD B1 KAI FXA JD B2 KAI FXA JD AE KAI QXA JD B1 KAI QXA JD B2 KAI QXA JD AE Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI AXA Serial Number KAI FXA Serial Number KAI QXA Serial Number Table 3. EVALUATION SUPPORT Catalog Number Product Name Description 4H2207 G2 FPGA BD A GEVK FPGA Board for IT CCD Evaluation Hardware 4H2209 KAI 72PIN HEAD BD A GEVB 72 Pin Imager Board for IT CCD Evaluation Hardware 4H2211 LENS MOUNT KIT B GEVK Lens Mount Kit for IT CCD Evaluation Hardware See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at. 2

3 Table 4. NOT RECOMMENDED FOR NEW DESIGNS Part Number Description Marking Code KAI CXA JD B1 KAI CXA JD B2 KAI CXA JD AE KAI PXA JD B1 KAI PXA JD B2 KAI PXA JD AE Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade Gen1 Color (TRUESENSE Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 Gen1 Color (TRUESENSE Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 Gen1 Color (TRUESENSE Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI CXA Serial Number KAI PXA Serial Number 3

4 DEVICE DESCRIPTION Architecture RDc Rc VDDc VOUTc H2Bc H2Sc H1Bc H1Sc FDGcd SUB FDGcd H2Bd H2Sd H1Bd H1Sd RDd Rd VDDd VOUTd OGc H2SLc FLD OGd H2SLd V1T V2T V3T V4T V1T V2T V3T V4T DevID ESD H x 3264V 5.5 m x 5.5 m Pixels ESD V1B V2B V3B V4B V1B V2B V3B V4B RDa Ra VDDa VOUTa 12 Buffer 22 Dark FLD ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ (Last VCCD Phase = V1 H1S) RDb Rb VDDb VOUTb OGa H2SLa H2Sa H1Ba H1Sa FDGab H2Ba SUB FDGab H2Bb H2Sb H1Bb H1Sb OGb H2SLb Figure 2. Block Diagram Dark Reference Pixels There are 22 dark reference rows at the top and 22 dark rows at the bottom of the image sensor. The dark rows are not entirely dark and so should not be used for a dark reference level. Use the 22 dark columns on the left or right side of the image sensor as a dark reference. Under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. Dummy Pixels Within each horizontal shift register there are 11 leading additional shift phases. These pixels are designated as dummy pixels and should not be used to determine a dark reference level. In addition, there is one dummy row of pixels at the top and bottom of the image. Active Buffer Pixels 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. These pixels are light sensitive but are not tested for defects and non uniformities. Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create electron hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. 4

5 ESD Protection Adherence to the power up and power down sequence is critical. Failure to follow the proper power up and power down sequences may cause damage to the sensor. See Power Up and Power Down Sequence section. Bayer Color Filter Pattern RDc Rc VDDc VOUTc H1Bc H1Sc H2Sc FDGcd H2Bc SUB FDGcd H2Bd H2Sd H1Bd H1Sd RDd Rd VDDd VOUTd OGc H2SLc FLD OGd H2SLd V1T V2T V3T V4T B G G R B G G R V1T V2T V3T V4T DevID ESD H x 3264V 5.5 m x 5.5 m Pixels ESD V1B V2B V3B V4B B G G R B G G R V1B V2B V3B V4B RDa Ra VDDa VOUTa OGa H2SLa 12 Buffer 22 Dark FLD (Last VCCD Phase = V1 H1S) H2Ba H2Sa H1Ba H1Sa FDGab SUB H2Bb H2Sb H1Bb H1Sb Figure 3. Bayer Color Filter Pattern FDGab RDb Rb VDDb VOUTb OGb H2SLb TRUESENSE Sparse Color Filter Pattern RDc Rc VDDc VOUTc H1Bc H1Sc H2Sc FDGcd H2Bc SUB FDGcd H2Bd H2Sd H1Bd H1Sd RDd Rd VDDd VOUTd OGc H2SLc FLD OGd H2SLd V1T V2T V3T V4T G P R P P G P R B P G P P B P G G P R P P G P R B P G P P B P G V1T V2T V3T V4T DevID ESD H x 3264V 5.5 m x 5.5 m Pixels ESD RDa Ra VDDa VOUTa V1B V2B V3B V4B G P R P P G P R B P G P P B P G 12 Buffer G P R P P G P R B P G P P B P G 22 Dark FLD (Last VCCD Phase = V1 H1S) V1B V2B V3B V4B RDb Rb VDDb VOUTb OGa H2SLa H2Ba H2Sa H1Ba H1Sa FDGab SUB FDGab H2Bb H2Sb H1Bb H1Sb OGb H2SLb Figure 4. TRUESENSE Sparse Color Filter Pattern 5

6 PHYSICAL DESCRIPTION Pin Description and Device Orientation V3T V1T VDDd Rd H2SLd H1Bd H2Sd SUB N/C H2Sc H1Bc H2SLc Rc VDDc V1T V3T DevID V4T V2T VOUTd RDd OGd H2Bd H1Sd FDGcd FDGcd H1Sc H2Bc OGc RDc VOUTc V2T V4T ESD Pixel (1,1) ESD V4B V2B VOUTb RDb OGb H2Bb H1Sb FDGab FDGab H1Sa H2Ba OGa RDa VOUTa V2B V4B V3B V1B VDDb Rb H2SLb H1Bb H2Sb N/C SUB H2Sa H1Ba H2SLa Ra VDDa V1B V3B Figure 5. Package Pin Designations Top View 6

7 Table 5. PIN DESCRIPTION Pin Name Description 1 V3B Vertical CCD Clock, Phase 3, Bottom 3 V1B Vertical CCD Clock, Phase 1, Bottom 4 V4B Vertical CCD Clock, Phase 4, Bottom 5 VDDa Output Amplifier Supply, Quadrant a 6 V2B Vertical CCD Clock, Phase 2, Bottom 7 Ground 8 VOUTa Video Output, Quadrant a 9 Ra Reset Gate, Quadrant a 10 RDa Reset Drain, Quadrant a 11 H2SLa Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a 12 OGa Output Gate, Quadrant a 13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a 14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a 15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a 16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a 17 SUB Substrate 18 FDGab Fast Line Dump Gate, Bottom 19 N/C No Connect 20 FDGab Fast Line Dump Gate, Bottom 21 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b 22 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b 23 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b 24 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b 25 H2SLb Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b 26 OGb Output Gate, Quadrant b 27 Rb Reset Gate, Quadrant b 28 RDb Reset Drain, Quadrant b 29 Ground 30 VOUTb Video Output, Quadrant b 31 VDDb Output Amplifier Supply, Quadrant b 32 V2B Vertical CCD Clock, Phase 2, Bottom 33 V1B Vertical CCD Clock, Phase 1, Bottom 34 V4B Vertical CCD Clock, Phase 4, Bottom 35 V3B Vertical CCD Clock, Phase 3, Bottom 36 ESD ESD Protection Disable Pin Name Description 72 ESD ESD Protection Disable 71 V3T Vertical CCD Clock, Phase 3, Top 70 V4T Vertical CCD Clock, Phase 4, Top 69 V1T Vertical CCD Clock, Phase 1, Top 68 V2T Vertical CCD Clock, Phase 2, Top 67 VDDc Output Amplifier Supply, Quadrant c 66 VOUTc Video Output, Quadrant c 65 Ground 64 RDc Reset Drain, Quadrant c 63 Rc Reset Gate, Quadrant c 62 OGc Output Gate, Quadrant c 61 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c 60 H2Bc Horizontal CCD Clock, Phase 2, Barrier, Quadrant c 59 H1Bc Horizontal CCD Clock, Phase 1, Barrier, Quadrant c 58 H1Sc Horizontal CCD Clock, Phase 1, Storage, Quadrant c 57 H2Sc Horizontal CCD Clock, Phase 2, Storage, Quadrant c 56 FDGcd Fast Line Dump Gate, Top 55 N/C No Connect 54 FDGcd Fast Line Dump Gate, Top 53 SUB Substrate 52 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d 51 H2Sd Horizontal CCD Clock, Phase 2, Storage, Quadrant d 50 H2Bd Horizontal CCD Clock, Phase 2, Barrier, Quadrant d 49 H1Bd Horizontal CCD Clock, Phase 1, Barrier, Quadrant d 48 OGd Output Gate, Quadrant d 47 H2SLd Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d 46 RDd Reset Drain, Quadrant d 45 Rd Reset Gate, Quadrant d 44 VOUTd Video Output, Quadrant d 43 Ground 42 V2T Vertical CCD Clock, Phase 2, Top 41 VDDd Output Amplifier Supply, Quadrant d 40 V4T Vertical CCD Clock, Phase 4, Top 39 V1T Vertical CCD Clock, Phase 1, Top 38 DevID Device Identification 37 V3T Vertical CCD Clock, Phase 3, Top 1. Liked named pins are internally connected and should have a common drive signal. 2. N/C pins (19, 55) should be left floating. 7

8 IMAGING PERFORMANCE Table 6. TYPICAL OPERATION CONDITIONS Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions. Description Condition Notes Light Source Continuous red, green and blue LED illumination For monochrome sensor, only green LED used. Operation Nominal operating voltages and timing Table 7. SPECIFICATIONS All Configurations Description Symbol Min. Nom. Max. Units Sampling Plan Temperature Tested At ( C) Dark Field Global Non Uniformity DSNU 5 mvpp Die 27, 40 Bright Field Global Non Uniformity 2 5 %rms Die 27, 40 1 Bright Field Global Peak to Peak Non Uniformity PRNU %pp Die 27, 40 1 Bright Field Center Non Uniformity 1 2 %rms Die 27, 40 1 Notes Maximum Photoresponse Nonlinearity Maximum Gain Difference Between Outputs Maximum Signal Error due to Nonlinearity Differences NL 2 % Design 2 G 10 % Design 2 NL 1 % Design 2 Horizontal CCD Charge Capacity HNe 50 ke Design Vertical CCD Charge Capacity VNe 45 ke Design Photodiode Charge Capacity PNe 20 ke Die 27, 40 3 Horizontal CCD Charge Transfer Efficiency Vertical CCD Charge Transfer Efficiency HCTE Die VCTE Die Photodiode Dark Current Ipd 7 70 e/p/s Die 40 Vertical CCD Dark Current Ivd e/p/s Die 40 Image Lag Lag 10 e Design Antiblooming Factor Xab 300 Design Vertical Smear Smr 100 db Design Read Noise n e T 12 e rms Design 4 Dynamic Range DR 64 db Design 4, 5 Output Amplifier DC Offset V odc 9.4 V Die 27, 40 Output Amplifier Bandwidth f 3db 250 MHz Die 6 Output Amplifier Impedance R OUT 127 Die 27, 40 Output Amplifier Sensitivity V/ N 34 V/e Design 1. Per color 2. Value is over the range of 10% to 90% of photodiode saturation. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is 680 mv. 4. At 40 MHz 5. Uses 20LOG (PNe/ n e T ) 6. Assumes 5 pf load. 8

9 Table 8. KAI AXA, KAI QXA, AND KAI PXA 1 CONFIGURATIONS Description Symbol Min. Nom. Max. Units Sampling Plan Peak Quantum Efficiency QE max 43 % Design Peak Quantum Efficiency Wavelength QE 470 nm Design 1. This color filter set configuration (Gen1) is not recommended for new designs. Temperature Tested At ( C) Notes Table 9. KAI FBA AND KAI QBA GEN2 COLOR CONFIGURATIONS WITH MAR GLASS Description Symbol Min. Nom. Max. Units Peak Quantum Efficiency Blue Green Red QE max Sampling Plan % Design Temperature Tested At ( C) Notes Peak Quantum Efficiency Wavelength Blue Green Red QE nm Design Table 10. KAI CBA AND KAI PBA GEN1 COLOR CONFIGURATIONS WITH MAR GLASS Description Symbol Min. Nom. Max. Units Peak Quantum Efficiency Peak Quantum Efficiency Wavelength Blue Green Red Blue Green Red QE max QE This color filter set configuration (Gen1) is not recommended for new designs. Sampling Plan Temperature Tested At ( C) Notes % Design 1 nm Design 1 9

10 TYPICAL PERFORMANCE CURVES Quantum Efficiency Monochrome with Microlens Figure 6. Monochrome with Microlens Quantum Efficiency 10

11 Color (Bayer RGB) with Microlens and MAR Cover Glass (Gen2 and Gen1 CFA) Figure 7. Color (Bayer) with Microlens Quantum Efficiency Color (TRUESENSE Sparse CFA) with Microlens (Gen2 and Gen1 CFA) Figure 8. Color (TRUESENSE Sparse CFA) with Microlens Quantum Efficiency 11

12 Angular Quantum Efficiency For the curves marked Horizontal, the incident light angle is varied in a plane parallel to the HCCD. For the curves marked Vertical, the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens Relative Quantum Efficiency (%) Horizontal Vertical Angle (degrees) Figure 9. Monochrome with Microlens Angular Quantum Efficiency Dark Current versus Temperature Dark Current (e/s) VCCD Photodiode /T (K) T (C) Figure 10. Dark Current versus Temperature 12

13 Power Estimated Power (W) HCCD Frequency (MHz) Single Dual Quad Figure 11. Power Frame Rates Frame Rate (fps) HCCD Frequency (MHz) Single Dual (Left/Right) Quad Figure 12. Frame Rates 13

14 DEFECT DEFINITIONS Table 11. OPERATION CONDITIONS FOR DEFECT TESTING AT 40 C Description Condition Notes Operational Mode HCCD Clock Frequency Two outputs, using VOUTa and VOUTc, continuous readout 10 MHz Pixels Per Line Lines Per Frame Line Time Frame Time Photodiode Integration Time (PD_Tint) sec msec Mode A: PD_Tint = Frame Time = msec, no electronic shutter used VCCD Integration Time msec 3 Temperature 40 C Light Source Continuous red, green and blue LED illumination 4 Operation Nominal operating voltages and timing 1. Horizontal overclocking used. 2. Vertical overclocking used. 3. VCCD Integration Time = 1666 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. 4. For monochrome sensor, only the green LED is used. Table 12. DEFECT DEFINITIONS FOR TESTING AT 40 C Description Definition Grade 1 Grade 2 Mono Grade 2 Color Major dark field defective bright pixel PD_Tint = Mode A Defect 328 mv Major bright field defective dark pixel Defect 12% Minor dark field defective bright pixel PD_Tint = Mode A Defect 164 mv Notes Cluster defect A group of 2 to 19 contiguous major defective pixels, but no more than 3 adjacent defects horizontally. 20 n/a n/a 2 Cluster defect Column defect A group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally. A group of more than 10 contiguous major defective pixels along a single column n/a For the color devices (KAI CXA and KAI PXA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). 14

15 Table 13. OPERATION CONDITIONS FOR DEFECT TESTING AT 27 C Description Condition Notes Operational Mode HCCD Clock Frequency Two outputs, using VOUTa and VOUTc, continuous readout 10 MHz Pixels Per Line Lines Per Frame Line Time Frame Time Photodiode Integration Time (PD_Tint) sec msec Mode A: PD_Tint = Frame Time = msec, no electronic shutter used VCCD Integration Time msec 3 Temperature 27 C Light Source Continuous red, green and blue LED illumination 4 Operation Nominal operating voltages and timing 1. Horizontal overclocking used. 2. Vertical overclocking used. 3. VCCD Integration Time = 1666 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. 4. For monochrome sensor, only the green LED is used. Table 14. DEFECT DEFINITIONS FOR TESTING AT 27 C Description Definition Grade 1 Grade 2 Mono Grade 2 Color Major dark field defective bright pixel PD_Tint = Mode A Defect 200 mv Major bright field defective dark pixel Defect 12% Cluster defect Cluster defect Column defect A group of 2 to 19 contiguous major defective pixels, but no more than 3 adjacent defects horizontally. A group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally. A group of more than 10 contiguous major defective pixels along a single column Notes 20 n/a n/a 2 n/a For the color devices (KAI CXA and KAI PXA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). Defect Map The defect map supplied with each sensor is based upon testing at an ambient (27 C) temperature. Minor point defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. See Figure 13: Regions of interest for the location of pixel 1,1. 15

16 TEST DEFINITIONS Test Regions of Interest Image Area ROI: Pixel (1, 1) to Pixel (4920, 3288) Active Area ROI: Pixel (13, 13) to Pixel (4908, 3276) Center ROI: Pixel (2411, 1595) to Pixel (2510, 1694) Only the Active Area ROI pixels are used for performance and defect tests. Overclocking The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 13 for a pictorial representation of the regions of interest. VOUTc 12 dark rows 12 buffer rows Pixel 13, dark columns 12 buffer columns 4896 x 3264 Active Pixels 12 buffer columns 22 dark columns Horizontal Overclock Pixel 1, 1 12 buffer rows 12 dark rows VOUTa Figure 13. Regions of Interest 16

17 Tests Dark Field Global Non Uniformity This test is performed under dark field conditions. The sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. The average signal level of each of the 864 sub regions of interest is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Signal of ROI[i] = (ROI Average in counts Horizontal overclock average in counts) * mv per count Where i = 1 to 864. During this calculation on the 864 sub regions of interest, the maximum and minimum signal levels GlobalNon Uniformity 100 ActiveAreaStandardDeviation ActiveAreaSignal Units: %rms. Active Area Signal = Active Area Average Dark Column Average Global Peak to Peak Non Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. The sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 Units: %pp MaximumSignal MinimumSignal GlobalUniformity 100 ActiveAreaSignal Center Non Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). Prior to this test being performed Center ROI Uniformity 100 Units: %rms. Center ROI Signal = Center ROI Average Dark Column Average Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the Defect Definitions section. Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at approximately 476 mv. Prior are found. The dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. Units: mvpp (millivolts peak to peak) Global Non Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. Global non uniformity is defined as pixels in size. The average signal level of each of the 864 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Signal of ROI[i] = (ROI Average in counts Horizontal overclock average in counts) * mv per count Where i = 1 to 864. During this calculation on the 864 sub regions of interest, the maximum and minimum signal levels are found. The global peak to peak uniformity is then calculated as: the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. Defects are excluded for the calculation of this test. This test is performed on the center 100 by 100 pixels of the sensor. Center uniformity is defined as: Center ROI Standard Deviation Center ROI Signal to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. The average signal level of all active pixels is found. The bright and dark thresholds are set as: Dark defect threshold = Active Area Signal * threshold Bright defect threshold = Active Area Signal * threshold The sensor is then partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. 17

18 Example for major bright field defective pixels: Average value of all active pixels is found to be 476 mv Dark defect threshold: 476 mv * 12 % = 57 mv Region of interest #1 selected. This region of interest is pixels 13, 13 to pixels 148, 148. Median of this region of interest is found to be 470 mv. Any pixel in this region of interest that is ( mv) 413 mv in intensity will be marked defective. All remaining 836 sub regions of interest are analyzed for defective pixels in the same manner. KAI

19 OPERATION Table 15. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Operating Temperature T OP C 1 Humidity RH % 2 Output Bias Current I out 60 ma 3 Off chip Load C L 10 pf Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Noise performance will degrade at higher temperatures. 2. T = 25 C. Excessive humidity will degrade MTTF. 3. Total for all outputs. Maximum current is 15 ma for each output. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Table 16. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND Description Minimum Maximum Units Notes VDD, VOUT V 1 RD V 1 V1B, V1T ESD 0.4 ESD V V2B, V2T, V3B, V3T, V4B, V4T ESD 0.4 ESD V FDGab, FDGcd ESD 0.4 ESD V H1S, H1B, H2S, H2B, H2SL, R, OG ESD 0.4 ESD V 1 ESD V SUB V 2 1. denotes a, b, c or d 2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Power Up and Power Down Sequence Adherence to the power up and power down sequence is critical. Failure to follow the proper power up and power down sequences may cause damage to the sensor. V+ Do not pulse the electronic shutter until ESD is stable VDD SUB time ESD VCCD Low HCCD Low V Activate all other biases when ESD is stable and sub is above 3V Figure 14. Power Up and Power Down Sequence Notes: 1. Activate all other biases when ESD is stable and SUB is above 3 V 2. Do not pulse the electronic shutter until ESD is stable 3. VDD cannot be +15 V when SUB is 0 V 4. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 ma. SUB and VDD must always be greater than. ESD must always be less than. Placing diodes between SUB, VDD, ESD and ground will protect 19

20 the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See the figure below. The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage. Example of external diode protection for SUB, VDD and ESD. denotes a, b, c or d VDD SUB 0.0V ESD ESD ESD 0.4V Figure 15. All VCCD Clocks absolute maximum overshoot of 0.4 V Figure 16. Table 17. DC BIAS OPERATING CONDITIONS Description Pins Symbol Minimum Nominal Maximum Units Maximum DC Current Reset Drain RD RD V 10 A 1 Output Gate OG OG V 10 A 1 Output Amplifier Supply VDD VDD V 11.0 ma 1,2 Ground V 1.0 ma Substrate SUB VSUB +5.0 VAB VDD V 50 A 3, 8 ESD Protection Disable ESD ESD Vx_L V 50 A 6, 7, 9 Output Bias Current VOUT Iout ma 1, 4, 5 1. denotes a, b, c or d 2. The maximum DC current is for one output. Idd = Iout + Iss. See Figure The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is the nominal PNe (see Specifications). 4. An output load sink must be applied to each VOUT pin to activate each output amplifier. 5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise. 6. Adherence to the power up and power down sequence is critical. See Power Up and Power Down Sequence section. 7. ESD maximum value must be less than or equal to V1_L V and V2_L V 8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions 9. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application. Notes 20

21 R RD VDD Idd HCCD Floating Diffusion Iout OG VOUT Iss Source Follower #1 Source Follower #2 Source Follower #3 Figure 17. Output Amplifier 21

22 AC Operating Conditions Table 18. CLOCK LEVELS Description Pins 1 Symbol Level Minimum Nominal Maximum Units Capacitance 2 Vertical CCD Clock, V1B, V1T V1_L Low V 180 nf (6) Phase 1 V1_M Mid Vertical CCD Clock, Phase 2 Vertical CCD Clock, Phase 3 Vertical CCD Clock, Phase 4 Horizontal CCD Clock, Phase 1 Storage Horizontal CCD Clock, Phase 1 Barrier Horizontal CCD Clock, Phase 2 Storage Horizontal CCD Clock, Phase 2 Barrier V1_H High V2B, V2T V2_L Low V 180 nf (6) V2_H High V3B, V3T V3_L Low V 180 nf (6) V3_H High V4B, V4T V4_L Low V 180 nf (6) V4_H High H1S H1S_L Low 5.2 (7) V 600 pf (6) H1S_A Amplitude (7) H1B H1B_L Low 5.2 (7) V 400 pf (6) H1B_A Amplitude (7) H2S H2S_L Low 5.2 (7) V 580 pf (6) H2S_A Amplitude (7) H2B H2B_L Low 5.2 (7) V 400 pf (6) H2B_A Amplitude (7) Horizontal CCD Clock, H2SL H2SL_L Low V 20 pf (6) Last Phase 3 H2SL_A Amplitude Reset Gate R R_L 4 Low V 16 pf (6) R_H High Electronic Shutter 5 SUB VES High V 12 nf (6) Fast Line Dump Gate FDG FDG_L Low V 50 pf (6) FDG_H High denotes a, b, c or d 2. Capacitance is total for all like named pins 3. Use separate clock driver for improved speed performance. 4. Reset low should be set to 3 volts for signal levels greater than 40,000 electrons. 5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions 6. Capacitance values are estimated 7. If the minimum horizontal clock low level is used ( 5.2 V), then the maximum horizontal clock amplitude should be used (5.2 V amplitude) to create a 5.2 V to 0.0 V clock. If a 5 V clock driver is used, the horizontal low level should be set to 5.0 V and the high level should be a set to 0.0 V. The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. VES VSUB Figure

23 Device Identification The device identification pin (DevID) may be used to determine which ON Semiconductor 5.5 micron pixel interline CCD sensor is being used. Table 19. DEVICE IDENTIFICATION Description Pins Symbol Minimum Nominal Maximum Units Maximum DC Current Device Identification DevID DevID 144, , , A 1, 2, 3 1. Nominal value subject to verification and/or change during release of preliminary specifications. 2. If the Device Identification is not used, it may be left disconnected. 3. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent localized heating of the sensor due to current flow through the R_DeviceID resistor. Notes Recommended Circuit Note that V1 must be a different value than V2. V1 V2 R_external DevID ADC R_DeviceID KAI Figure 19. Device Identification Recommended Circuit 23

24 TIMING Table 20. REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units Notes Photodiode Transfer t pd 3 s VCCD Leading Pedestal t 3p 4 s VCCD Trailing Pedestal t 3d 4 s VCCD Transfer Delay t d 4 s VCCD Transfer t v 4 s VCCD Clock Cross over v VCR % 1 VCCD Rise, Fall Times t VR, t VF 5 10 % 1, 2 FDG Delay t fdg 2 s HCCD Delay t hs 1 s HCCD Transfer t e 25.0 ns Shutter Transfer t sub 1 s Shutter Delay t hd 1 s Reset Pulse t r 2.5 ns Reset Video Delay t rv 2.2 ns H2SL Video Delay t hv 3.1 ns Line Time t line 69.3 s Dual HCCD Readout Single HCCD Readout Frame Time t frame ms Quad HCCD Readout 1. Refer to Figure 25: VCCD Clock Rise Time, Fall Time and Edge Alignment 2. Relative to the pulse width 3. Refer to timing diagrams as shown in Figures 21, 22, 23, 24 and Dual HCCD Readout Single HCCD Readout 24

25 Timing Diagrams The timing sequence for the clocked device pins may be represented as one of seven patterns (P1 P7) as shown in the table below. The patterns are defined in Figure 21 and Figure 22. Contact ON Semiconductor Imaging Application Engineering for other readout modes. Table 21. Device Pin Quad Readout Dual Readout VOUTa, VOUTb Dual Readout VOUTa, VOUTc Single Readout VOUTa V1T P1T P1B P1T P1B V2T P2T P4B P2T P4B V3T P3T P3B P3T P3B V4T P4T P2B P4T P2B V1B V2B V3B V4B H1Sa H1Ba H2Sa 2 H2Ba Ra H1Sb P5 P5 H1Bb H2Sb 2 P6 P6 H2Bb Rb P7 P7 1 or Off 3 P7 1 or Off 3 H1Sc P5 P5 1 or Off 3 P5 P5 1 or Off 3 H1Bc H2Sc 2 P6 P6 1 or Off 3 P6 P6 1 or Off 3 H2Bc Rc P7 P7 1 or Off 3 P7 P7 1 or Off 3 H1Sd P5 P5 1 or Off 3 P5 P5 1 or Off 3 H1Bd H2Sd 2 P6 P6 1 or Off 3 P6 P6 1 or Off 3 H2Bd Rd P7 P7 1 or Off 3 P7 1 or Off 3 P7 1 or Off 3 P1B P2B P3B P4B P5 P6 P7 P6 P5 P6 P5 # Lines/Frame (Minimum) # Pixels/Line (Minimum) For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should be a multiple of the frequency used on the a and b register. 2. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver. 3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the unused c/d register into the image area. 25

26 Photodiode Transfer Timing A row of charge is transferred to the HCCD on the falling edge of V1 as indicated in the P1 pattern below. Using this timing sequence, the leading dummy row or line is combined with the first dark row in the HCCD. The Last Line is dependent on readout mode either 1666 or 3332 minimum counts required. It is important to note that, in general, the rising edge of a vertical clock (patterns P1 P4) should be coincident or slightly leading a falling edge at the same time interval. This is particularly true at the point where P1 returns from the high (3 rd level) state to the mid state when P4 transitions from the low state to the high state. Pattern td t3p tpd t3d td tv tv P1T P2T P3T tv/2 tv/2 tv/2 tv/2 P4T tv tv P1B P2B P3B P4B tv/2 tv/2 ths ths P5 Last Line L1 + Dummy Line L2 P6 P7 Figure 20. Photodiode Transfer Timing Line and Pixel Timing Each row of charge is transferred to the output, as illustrated below, on the falling edge of H2SL (indicated as P6 pattern). The number of pixels in a row is dependent on readout mode either 2492 or 4984 minimum counts required. Pattern t line t v P1T P1B P5 t v t hs t e /2 P6 t e P7 t r VOUT Pixel 1 Pixel 34 Pixel n Figure 21. Line and Pixel Timing 26

27 Pixel Timing Detail P5 P6 P7 VOUT t hv t rv Figure 22. Pixel Timing Detail Frame/Electronic Shutter Timing The SUB pin may be optionally clocked to provide electronic shuttering capability as shown below. The resulting photodiode integration time is defined from the falling edge of SUB to the falling edge of V1 (P1 pattern). Pattern t frame P1T/P4B SUB t hd t sub t int P6 t hd Figure 23. Frame/Electronic Shutter Timing VCCD Clock Edge Alignment V VCR 90% t V 10% t VR t VF t V t VF t VR Figure 24. VCCD Clock Rise Time, Fall Time and Edge Alignment 27

28 Line and Pixel Timing Vertical Binning by 2 t v t v t v t hs P1T P2T P3T P4T P1B P2B P3B P4B P5 t hs P6 P7 VOUT Pixel 1 Pixel 34 Figure 25. Line and Pixel Timing Vertical Binning by 2 Pixel n Fast Line Dump Timing The FDG pins may be optionally clocked to efficiently remove unwanted lines in the image resulting for increased frame rates at the expense of resolution. Below is an example of a 2 line dump sequence followed by a normal readout line. Note that the FDG timing transitions should complete prior to the beginning of V1 timing transitions as illustrated below. Figure 26. Fast Line Dump Timing 28

29 STORAGE AND HANDLING Table 22. STORAGE CONDITIONS Description Symbol Minimum Maximum Units Notes Storage Temperature T ST C 1 Humidity RH 5 90 % 2 1. Long term storage toward the maximum temperature will accelerate color filter degradation. 2. T = 25 C. Excessive humidity will degrade MTTF. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from. 29

30 MECHANICAL INFORMATION Completed Assembly Notes: 1. See Ordering Information for marking code. 2. No materials to interfere with clearance through package holes. 3. Units: IN [MM] Figure 27. Completed Assembly (1 of 2) 30

31 Notes: 1. Units IN [MM] Figure 28. Completed Assembly (2 of 2) 31

32 Cover Glass Notes: 1. Substrate = Schott D263T eco 2. Dust, Scratch, Inclusion Specification: a.) 20 m Max size in Zone A 3. MAR coated both sides 4. Spectral Transmission a.) nm: T 88% b.) nm: T 94% c.) nm: T 98% d.) nm: T 99% e.) nm: T 98% f.) nm: T 94% g.) nm: T 88% 5. Units: IN [MM] Figure 29. Cover Glass 32

33 Cover Glass Transmission Figure 30. Cover Glass Transmission ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor E. 32nd Pkwy, Aurora, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative KAI 16050/D