Exam Complex Systems Design Methodology

Transcription

1 Exam Complex Systems Design Methodology Thursday, 21 January 2010 at 8.30 Prof. Dirk Stroobandt name: Some remarks Write your name on this page and write your initials on all pages you hand in. This exam has to be solved within 3 hours. Write the answers in the allocated zones. Most answers are short. Do not use green ink or pencils. This is an open book exam. You are allowed to use the PowerPoint slides presented in both theory and lab sessions and the course notes. The use of electronic devices is prohibited. You are not allowed to ask fellow students for help. This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents. 1

2 Question 1. Industrial bakery (4 points) The figure shows the production line of an industrial cake bakery. Most cakes (90%) require 5 production steps: A, B, C, D, and E, in alphabetical order. Some cakes (10%) do not need filling and can therefore skip steps B and C. In steps C, D, and E a choice between different materials has to be made. The machines C, D, and E are set to automatically make the right choice for each cake. Each of these three machines only processes one cake at a time. Choosing the correct material does not take any time. The figure below shows the duration for each step. It should be noted that putting the cherry on a cake (step E) takes less time than writing chocolate text on the cake. step A basic cake step B cut in half step C cake filling step D top layer step E finishing touch TEXT pipeline each cake is in the oven for 36 min. 12 cakes at a time duration: 1 min. 4 options duration: 2 min. 3 options duration: 2 min. 2 options cherry: 1 min. text: 5 min. (a) Possible problems Describe two different cases which lead to a throughput problem in the production line. Clearly indicate where in the line these problems occur. 2 This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents.

3 (b) Solutions Describe which buffers you would add to the system to improve the production line and thus resolve the problems from (a). Calculate the minimal buffer sizes. Does this solve all problems? If so, prove this is the case. If not, indicate which problems remain and why they still exist. You may include a possible solution. (c) Deadlock Can a deadlock occur in this production line? If so, give an example. If not, explain why this is not possible. This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents. 3

4 (d) Consequences of changing step C How do the flow and buffers of the production line change when step C takes 3 times as long? (e) Change the ratio to 50/50 How do the buffer lengths and flow change if the ratio between cakes that have to pass step B and C and cakes that can skip B and C, changes to 50/50 instead of 90/10. Explain your answer extensively. 4 This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents.

5 Question 2. Digital design (4 points) For JPEG compression images are converted from RGB representation to YUV. Practically this means that each pixel in the original image is represented by 3 bytes: 1 for red, 1 for green, and 1 for blue. After the conversion these 3 bytes are: 1 for Y (the luminance), 1 for U, and 1 for V. In which V and U contain the chrominance information. Notice that both R, G, B and Y, U, V represent numbers between 0 and 255. The conversion is done using the following equations: Y = (306 * R * G * B) >> 10; U = (- 172 * R * G * B ) >> 10; V = (512 * R * G - 83 * B ) >> 10; For the hardware implementation you can use adders and multipliers with two operands. The adders can add two 18-bit numbers, the multipliers work with two 10-bit numbers. An addition takes 1 clock cycle, a multiplication 4 cycles. (a) Hardware implementation Sketch the fastest possible hardware implementation that achieves this conversion. Also indicate how many clock cycles your solution requires, and the amount of adders, multipliers and registers you need. This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents. 5

6 (b) Efficient hardware implementation Make a new solution using, at most, 4 adders and 4 multipliers. You choose the fastest solution within the specified limits. Again, indicate how many clock cycles your solution requires and specify the amount of adders, multipliers and registers you need. (c) Improvement of the efficient implementation You can now use internally pipelined multipliers. Is it possible to optimise solution (b), using these multipliers? Describe how you would do this, and estimate how many clock cycles you would now need to complete the calculations. 6 This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents.

7 (d) Without multipliers Make an implementation for the RGB-to-YUV conversion without multipliers. This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents. 7

8 Question 3. Custom memory hierarchy (4 points) (a) One main memory Make a data use diagram (without reuse), with only 1 main memory. Indicate how big this memory is, how many data accesses there are (for a single iteration of i) and make an estimation of the energy use. Assume a main memory that is exactly as big as the different elements of matrix A, read by this perfect loop nest. for (i=0; i < 36; i++) for (j=0; j < 6; j++) for (k=0; k < 12; k++) for (l=0; l < 4; l++) for (m=0; m < 8; m++) B[i] += A[47*i + 4*k + m]; (b) Data reuse Find three different possibilities for data reuse and design a memory hierarchy for each of these possibilities. Make a data reuse diagram for each possibility. Indicate how big each memory is, how many data accesses there are and estimate the energy usage. Use the original code without additional loop transformations. 8 This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents.

9 (c) Pareto Draw the four possible memory configurations on a Pareto curve. Make a trade-off between chip area and energy consumption. This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents. 9

10 t3[c==1] Question 4. Multi functional cake machine (4 points) Cake machine S5 clock[a+b+c>0]/r=0 timeout[s2 & r==1]/t1 timeout[s2 & r==0]/r=1 S6 20 min. S1 t1[a!=1]/a-- S2 S8 3 min. timeout S7 12 min. S3 timeout S4 Clock 1 min. t3[c!=1]/c-- t2[b!=1]/b-- timeout/clock This StateChart describes a machine that produces 3 different cakes: Cake A is baked two times on a low temperature. Cake B is first baked on a low temperature and then on a high temperature. Cake C is baked first on a low temperature, then glazed and lastly baked on a high temperature. In addition to a clock, this StateChart has a part that describes the production process and a part that describes the control process. The amount of cakes is controlled by the variables A, B, and C, which represent the amount of cake A, cake B, and cake C that are to be made. (a) Identify S6, S7, and S8 Using the information given above, determine which of the different production steps, baking on a low temperature, baking on a high temperature and glazing, corresponds with S6, S7, and S8. 10 This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents.

11 (b) Find the error The control part of the StateChart still contains an error that could block the system. Describe clearly in which situations this problem occurs and indicate how the StateChart should be changed to solve this problem. (c) Change the StateChart Make an alternative StateChart description, one that does not use an AND super state, except for the clock. In this simplified representation the control and production parts are merged. This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents. 11

12 Question 5. Complex data accesses (4 points) Data is saved in a specific structure, indicated by matrix B[15][3]. The pseudo code on the left indicates how the function visit(int N) reads and adds up this data. int visit(int N) { if (B[N][0]!= -1) { return visit(b[n][0]) + visit(b[n][1]) + B[N][2]; } } else { return B[N][2]; } (a) Data accesses Indicate on matrix B in which order the data is read when visit(0) is called. You can use the space below for some additional explanations. (b) Data structure Which data structure can you recognise in this access pattern? Draw this data structure. 12 This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents.

13 (c) Optimisation Optimise the locality of the data accesses to matrix B. Draw the improved data structure. This exam is printed on recycled paper made from 100% post-consumer waste pulp. De-inked without bleaching. Free from optical brightening agents. 13