RH850/P1L-C 100-pin PiggyBack board V1 Y-RH850-P1XC-100PIN-PB-T1-V1

Transcription

1 User`s Manual RH0 valuation Platform RH0/PL- 00-pin Piggyack board V Y-RH0-PX-00P-P-T-V All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas lectronics orp. without notice. Please review the latest information published by Renesas lectronics orp. through various means, including the Renesas Technology orp. website ( The newest version of this document can be obtained from the following web location R0UTD000, Rev

2 Table of ontents hapter Introduction... hapter Overview.... Overview.... Mounting of the device... hapter Power supply.... oard power connection.... Voltage distribution... hapter lock sources..... MainOsc..... Programmable Oscillator... hapter Debug and Programming interface... hapter onnectors for ports of device onnectors for AD voltage supply Push button for RST Mode Selection onnectors to Mainoard..... onnector N..... onnector N..... onnector N... hapter Other circuitry.... Signalling for VMZ and RRORZ.... Pin Headers for Pull-Down and Pull-Up.... Signalling LDs... hapter Precautions... hapter Mechanical dimensions... hapter 0 Schematic... hapter Revision History... R0UTD000 Rev

3 hapter Introduction The RH0/PL- Application oard is part of the RH0 valuation Platform and serves as a simple and easy to use platform for evaluating the features and performance of Renesas lectronics -bit RH0/PL- microcontrollers in a QFP00 package. The Piggyack board (Y-RH0-PX-00P-P-T-V) can be used as a standalone board, or can be mated with a mainboard (Y- RH0-XX-M-Tx-Vx) for extended functionality. Main features: Socket for mounting of device Standalone operation of the board Direct supply of device voltage (typ..v and V) Device programming capability Device debugging capability Pin headers for direct access to each functional device pin Reset switch MainOS circuitry onnectors to Mainoard Operating temperature from 0 to +0 This document describes the functionality provided by the Piggyack board and guides the user through its operation. For details regarding the operation of the microcontroller, refer to the corresponding User s Manual. R0UTD000 Rev

4 hapter Overview. Overview Figures and provide a schematic view of the Piggyack board. Figure Piggyack oard Schematic Top View The black arrow denotes the position of socket pin #. Figure Piggyack oard Schematic ottom View R0UTD000 Rev

5 . Mounting of the device The board is designed for use with the following device: RH0/PL- in 00pin QFP with 0.mm pin pitch The device must be placed inside the socket I. To insert the device, press down the lid of the socket, align the # pin of the device to the # pin of the socket, insert the device into the socket and release the lid. R0UTD000 Rev

6 hapter Power supply. oard power connection For operation of the device, a supply voltage must be connected to the board. There are several possibilities to power the device. Within this document the following voltages are considered as typical connections: Voltage = V Voltage =.V Direct voltage supply Two different voltages can be supplied to the board. The following connectors are available to supply those voltages directly: Three mm banana-type connectors: - Two red connectors for voltages Voltage (N) and Voltage (N). - A black connector for ground (GND) connection (N). Note: The three connectors are supplied with the board but not assembled. For details about voltage distribution, refer to hapter. Voltage distribution. Supply by emulator The emulator that is used for debug purposes and flash programming can also supply a single operating voltage ( Dbg_Voltage ). This voltage is connected via 0V to the board. See the documentation of the and hapter Debug and Programming interface for details. Supply by Mainoard In case the Piggyack board is mounted on a Mainoard, the voltage Voltage and Voltage is supplied by the on-board regulator of the Mainoard. AUTION: Do not supply Voltage or Voltage directly to the Piggyack board in case it is mounted on the Mainoard. For each of the voltages, Voltage and Voltage a green LD (LD and LD, respectively) is available to signal that the related voltage is available on the Piggyack board. The corresponding LDs are placed directly beneath the connectors of the related voltage. R0UTD000 Rev

7 . Voltage distribution The table shows the required device power supply pins and their function. For detailed explanation of their function, please refer to the user documentation of the corresponding device: SYSV V Device Supply Pin nv (n = 0, ) AnV (n = 0, ) AnVRFH (n = 0, ) Additional one power supply for the Mainoard can be selected: Supply voltage VDDIOF Function IO supply voltage for components located on a connected mainboard. The following figure shows the configurable voltage distribution on the Piggyack board. Voltage # # JP # # JP0 # # # Voltage JP0 JP JP JP JP JP JP V 0V V SYSV VDDIOF (to mainboard) N (uneven pins) JP # # # JP JP A0V A0VRFH Figure Voltage Distribution on the Piggyack oard All power supply lines can be interrupted by jumpers. This provides the possibility to measure the current consumption of each individual power domain of the device. The IO supply voltage for the Mainboard (VDDIOF) can be connected via jumper JP to Voltage or Voltage, if the Piggyack board is mounted on a Mainoard. The voltage available at the uneven pins of N is configurable via jumper JP R0UTD000 Rev

8 hapter lock sources.. MainOsc One external crystal oscillator for the device clock supply is provided with the board. A crystal or ceramic resonator can be mounted on socket X. A Mhz oscillator is supplied with the board... Programmable Oscillator It is possible to mount a programmable crystal oscillator on the Piggyack board at OS. The available footprint and circuitry is designed for a SG-00 programmable crystal oscillator from pson Toyocom. The output from this oscillator can be connected to port X via jumper JP. The SG-00 is neither mounted nor provided with the board. For details about the available circuitry refer to hapter 0 Schematic. A resonator mounted on socket X must not be used in parallel to another clock source. R0UTD000 Rev

9 hapter Debug and Programming interface For connection of the microcontroller debug and flash programming tools, the connector N with fourteen pins is provided. The signal connection of the connector N is shown in the table below: N Pin Device Port Device Signal JP0_ TK / LPDLK / FLSISKI GND GND JP0_ TRSTZ FLMD0 FLMD0 JP0_ TDO / LPDO / FLSITXD - - JP0_0 TDI / LPDI / FLSIRXD / FLSITXD Dbg_Voltage 0V JP0_ TMS JP0_ RDYZ / LPDLK GND - RST RSTZ GND - R0UTD000 Rev

10 hapter onnectors for ports of device onnection to each functional pin of the devices is possible via the connectors N to N. AUTION: The pin headers are directly connected to the pins of the device, therefore special care must be taken to avoid any electrostatic or other damage to the device.. onnectors for AD voltage supply It is possible to apply the AD related reference, as well as one input voltage via SMA connectors (N0 and N). These are directly connected (JP is bypassed) to the following pins of the device Device Port N -> AD0I0 N0 -> A0VRFH The SMA connectors are not mounted on nor provided with the boards. SMA connectors that fit to the following mounting holes available on the board can be mounted on the board.mm.mm Ø.mm Figure Mounting Holes for SMA onnectors. Push button for RST In order to issue a RST to the device, the push-button SW is available.. Mode Selection The Piggyack oard gives the possibility to configure the following mode pins FLMD0 via jumper JP FLMD via jumper JP MOD0 via jumper JP MOD via jumper JP To apply High or Low to the mode pins, the pins and, or the pins and of the corresponding jumper must be shorted, respectively. Note: Pin of the jumpers is marked by a small circle. AUTION: e careful in configuration of mode related pins, as wrong configuration can cause irregular behaviour of the devices. e sure to check the corresponding User Manual, for details, which modes can be selected for the used device. R0UTD000 Rev

11 . onnectors to Mainoard Three connectors (N, N and N) are available to connect the Piggyack board to a Mainoard. Regarding the function on the Mainoard, please refer to the UM of any supported Mainoard (Y-RH0-XX-M-Tx-Vx). Some functions might not be available for every device. Therefore, please refer to the corresponding User s Manual for available pins on the used device, and a detailed explanation of their function... onnector N Pin Function on Mainoard Device Port Pin Function on Mainoard Device Port Voltage - Voltage - Voltage - Voltage - RST RSTZ NMI P_ T0 P_ 0 T P_ T P_ T P_ UART0TX P_ UARTTX P_ UART0RX P_ UARTRX P_ L0TX P_ 0 LTX P_ L0RX P_ LRX P_ II0SDL P_0 - - II0SDA P_ - - AN0TX P_ ANTX P_ AN0RX P_0 0 ANRX P_ SNT0 P0_0 SNT P0_ SNT0 P_ SNT P_ R0UTD000 Rev

12 Pin Function on Mainoard Device Port Pin Function on Mainoard Device Port DIGIO_0 P_ DIGIO_ P_ DIGIO_ P_0 DIGIO_ P_ DIGIO_ P_ 0 DIGIO_ P_ DIGIO_ P_0 DIGIO_ P_ DIGIO_ P_ DIGIO_ P_ DIGIO_0 P_ DIGIO_ P_ DIGIO_ P_ DIGIO_ P_ DIGIO_ P_ 00 DIGIO_ P_ MUX0 P_0 0 MUX P_ 0 MUX P_ AD0 AD0I0 0 AD AD0I 0 AD AD0I 0 AD AD0I0 AD AD0I AD AD0I AD AD0I AD AD0I VDDIOF - VDDIOF - Voltage - Voltage - Voltage - 0 Voltage -.. onnector N N is mounted on the Piggyack board to enable a stable mechanical connection to the currently available Mainoard (Y-RH0-XX-M-Tx-Vx). No function is assigned to N.. onnector N Pin Function on Mainoard Device Port Pin Function on Mainoard Device Port R0UTD000 Rev

13 Pin Function on Mainoard Device Port Pin Function on Mainoard Device Port SIHSS0 P_ SIHSS P_ SIHSS P_ DIGIO P_ - - SIHSO P_ SIHS P_ 0 SIHSI P_ DIGIO P_ R0UTD000 Rev

14 Pin Function on Mainoard Device Port Pin Function on Mainoard Device Port R0UTD000 Rev

15 hapter Other circuitry. Signalling for VMZ and RRORZ Two red LDs, LD and LD are available two indicate a low output signal from VMZ and RRORZ, respectively.. Pin Headers for Pull-Down and Pull-Up A connector N is available to enable easy connection to Voltage/Voltage (V/.V) or GND via pull-up or pull-down resistances, respectively. The voltage supply to the uneven pins can be configured via JP. See. Voltage distribution for details. Hereby uneven pins from to (in total ten) are configured as pull-up pin headers, while the even numbers from to 0 (in total ten) can be used for pulldown. y connecting device port pins from N to N it is therefore possible to pull a desired port pin to Low or High.. Signalling LDs ight LDs are provided to allow visual observation of the output state of device port pins. Device pins P_ to P_ are connected to the uneven pins to of the pin header N, while the LDs to are connected to the even pins to, respectively. Thus the LDs can be either connected to the device port pins P_ to P_ via jumper or any device port pin can be connected directly to the even pin headers. R0UTD000 Rev

16 hapter Precautions No limitations are known at the release of this document. R0UTD000 Rev

17 hapter Mechanical dimensions 00,00mm 0,00mm N 0,00mm,00mm N,00mm 0,00mm,00mm N R0UTD000 Rev

18 hapter 0 Schematic AUTION: The schematic shown in this document is not intended to be used as a reference for mass production. Any usage in an application design is in sole responsibility of the customer. The following components described in the schematic are not provided with the board: SMA connectors o o N0 N Jumper JP Oscillator OS apacitors o o Resistances o o o R R R Mainboard onnector N The following components described in the schematic are provided with but not mounted on the board: Standard mm power lab sockets o o o N N N R0UTD000 Rev

19 F D GND O VL_.V 0 0n 0n. OR V V. OR V LK SG00-MHz OS V.V R VL_0 K0 V n 00n. OR V 0V 00n. OR V 00n 00n. OR V V V.V VL_0 RRORZ P<..> P<..> P<..0>. OR V Z_PS<00..>.p X.000 MHZ + SOKT PF.p header way jumper.mm JP 00n V 00n 00n. OR V 0 A0VRFH AD0I<..0> P<0> P<..> P<0..0> P<0..0> P<..0> P[0] P[] P[] P[] P[] P[] P[] P[] P[] P[] P[] P[] P[] V[] VSS[] P[] P[] P[] P[] P[0] P[] P[] V VSS[] RRORZ. OR V P<..> RSTZ A0V Z_PS<00..>. OR V V VV.V.V VL_ I RH0_dv_00_yam_Socket 00n. OR V SYSV 0. OR V. OR V 0V 0 SYSV 0 A 0 P[] P0[] P0[0] P[] P[] P[] P[] P[0] P[] P[] P[] P[] P[] P[] P[] P[0] AD0I[0] AD0I[] AD0I[] AD0I[] AD0I[] AD0I[] A0V A0VSS A0VRFH P0<> FLMD0 VMZ P0<..0> JP0<..0> N SMA straight P<..0> AD0I<..0> P<0..> P<..> P0<..0> P<..0> AD0I<0>. OR V A0V. OR V A0VRFH. OR V A0VRFH SMAs onnectors N0 SMA straight VSS[] V[] P[] P[] P[] SYSV X OSVSS X VL[] VSS[] RSTZ JP0[] JP0[0] JP0[] JP0[] JP0[] JP0[] P0[] P0[0] 0V 0VSS VMZ FLMD0 P0[] P[] P[0] P[] P[] P[] P[] P[] P[] P[] 0 VSS[0] V[0] P[] P[] P[0] VL[0] VSS[0] P[] P[] P[0] 0 AD0I[] AD0I[] AD0I[] AD0I[] AD0I[] AD0I[0] Version VMZ R0 0K R TR0. OR V oard_v P0ART 0 0 TR red LD 0 0 N header way THT N header way THT N header way THT N header way THT 0 0 P0ART R Z_PS<00..> R 0K. OR V oard_v hanges R red LD RRORZ R Signalling for VM and RROR K K 0 0 R0UTD000 Rev Date: A Size Title omponent PAG OF SS Thu May 0:0:0 0 Document Number.00 lectronics urope GmbH RH0-PX-00P-P-T-V Z_PS<00..> Date F D A

20 DUG AND PROGRAMMG TRFA 0V. OR V POWR SUPPLY V STD POWR LA SOKT MM RD N SMATG_.V GND STD POWR LA SOKT MM LAK N.V STD POWR LA SOKT MM RD N D SMATG_.V GRN PV0 VV.0V header way long jumper.mm V JP PV.V header way long jumper.mm JP0 header way long jumper.mm 00u JP 00u header way long jumper.mm A0V JP. OR V header way long jumper.mm A0VRFH JP. OR V TOP OTTOM GND TST POT RUR FT VOLTAG DISTRIUTION PUSH UTTON FOR RST Min.ms from V up to resetz up LD - P<..> lectronics urope GmbH RH0-PX-00P-P-T-V Size Document Number A SS Date: Wed May 0:: 0 PAG OF.00 0 K K K K LD GRN yellow yellow yellow yellow R Port 0K NXP_ K K V_V V 00U V_.V.V PV0.0V oard_v. OR V D NHW NHW D 00U AV0 AV0.V V header way long jumper.mm JP0 TP TP FIDUIAL_MM FIDUIAL_MM TP TP FIDUIAL_MM FIDUIAL_MM TP GND-TSTPOT TP GND-TSTPOT TP GND-TSTPOT TP GND-TSTPOT TP GND-TSTPOT TP0 GND-TSTPOT RUR FOOT D=.MM/H=MM GRY MP RUR FOOT D=.MM/H=MM GRY MP VV VV V.V header way long jumper.mm VDDIOF JP. OR V oard_v. OR V 0 0 R K R Port 0K R Port 0K NXP_ R Port 0K NXP_ K K K K K yellow yellow yellow yellow NXP_ K K K TR TR R R Port 0K NXP_ Port 0K NXP_ Port K V. OR V.0u V. OR V.0u SYSV. OR V.0u R Port 0K Port Port Port Port 0 0 Port Port Port Port N header way 0 K0 K0 K 00U PV.V 0V. OR V.0u RUR FOOT D=.MM/H=MM GRY MP RUR FOOT D=.MM/H=MM GRY MP RUR FOOT D=.MM/H=MM GRY MP RUR FOOT D=.MM/H=MM GRY MP oard_v. OR V R0 PUSH UTTON P SMD SW 0K.0u 0.0u.0u TL0ID I V 0n. OR V 0V. OR V SNLVGDK 00n I O Z V 0K 0K R VV.V header way long jumper.mm JP header way long jumper.mm JP header way long jumper.mm JP header way long jumper.mm JP oard_v oard_v oard_v oard_v. OR V. OR V. OR V. OR V NXP_ oard_v oard_v oard_v oard_v. OR V. OR V. OR V. OR V NXP_ R0 0K 0 0K HADR WAY SHROUDD N FPMD0 0 0 R R R R R LD LD LD LD R R0 R R TR R TR R TR R TR R LD0 LD LD LD R R R R TR R R R TR R 0K R RSTZ JP0<..0> R D R R R LD FLMD0 P<0..0> RST_ RS RSTZ P<..0> ONTROL RST T RST_Z* RS* SNS GND A Y GND V D Title D A F A F R0UTD000 Rev

21 onnector ONNTOR MOD MOD0 FLMD ONNTOR MOD Jumper PULL UP PULL DOWN ONNTOR ONNTOR TO MA OARD ONNTORS Thu May 0:0: 0 lectronics urope GmbH RH0-PX-00P-P-T-V SS PAG OF header way long jumper.mm K0 QTH-00-0-F-D-A. OR V VDDIOF. OR V VDDIOF K0 K0 K0 K0 K0 header way long jumper.mm header way long jumper.mm K0. OR V 0V. OR V V V V. OR V K0 K0 K0 K0 K0 K0 K0 K0 K0 K0 K0 K0 K0 K0 K0 K0 K0 V VV K0 QTH-00-0-F-D-A.0V PV0 PV0.V QSH-00-0-F-D-A PV.V VV K0. OR V header way long jumper.mm header way long jumper.mm PV QSH-00-0-F-D-A.0V.V R0 R R JP R R R R JP R0 JP R JP JP R R R R0 R R R R R R R R R N R R R R N N N N P<> P<> P<0> P<> AD0I<0> AD0I<> AD0I<> AD0I<> P<> P<> P<> P<> P<0> P<> P<> P<0> P<..0> P<..0> FLMD0 P<..0> P<> P<> P<> P<> P<> P<> P<> P<> AD0I<> P<> AD0I<> AD0I<0> AD0I<> P<> P<> P<> P<> P<> P<> P<> RSTZ P<> P<> P<0> P0<0> P<> P<> P<> P<> P<0> P<> P<> P<> P<> P<> P<> P<> P<> P<> P<> P<> P0<> P<> Size Document Number A Title Date: A D F A D F R0UTD000 Rev

22 hapter Revision History The table provides information about the major changes of the document versions. Date Version Description Initial release R0UTD000 Rev

23 Notice. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. efore purchasing or using any Renesas lectronics products listed herein, please confirm the latest product information with a Renesas lectronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas lectronics such as that disclosed through our website.. Renesas lectronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas lectronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas lectronics or others.. You should not alter, modify, copy, or otherwise misappropriate any Renesas lectronics product, whether in whole or in part.. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas lectronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas lectronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas lectronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.. Renesas lectronics has used reasonable care in preparing the information included in this document, but Renesas lectronics does not warrant that such information is error free. Renesas lectronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.. Renesas lectronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas lectronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas lectronics product before using it in a particular application. You may not use any Renesas lectronics product for any application categorized as "Specific" without the prior written consent of Renesas lectronics. Further, you may not use any Renesas lectronics product for any application for which it is not intended without the prior written consent of Renesas lectronics. Renesas lectronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas lectronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas lectronics. The quality grade of each Renesas lectronics product is "Standard" unless otherwise expressly specified in a Renesas lectronics data sheets or data books, etc. "Standard": omputers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality":Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti- crime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.. You should use the Renesas lectronics products described in this document within the range specified by Renesas lectronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas lectronics shall have no liability for malfunctions or damages arising out of the use of Renesas lectronics products beyond such specified ranges. R0UTD000 Rev

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