SWITCHED CURRENT POWER CONVERTER TRANSIENT AND FREQUENCY RESPONSE

Transcription

1 EDWARD HERBERT DESIGNS SWITCHED CURRENT POWER CONVERTER TRANSIENT AND FREQUENCY RESPONSE July 29, 2005 Solutions for Advanced Performance Power Supplies On behalf of Edward Herbert For more information, contact: Arnold Alderman Anagenesis, Inc Century Park East Suite 600 Los Angeles, CA, Tel: Fax: Cell: Anagenesis, Inc., and Arnold N. Alderman, President are not patent attorneys or lawyers, and it is not expressed or implied that any legal services or legal opinions are offered on behalf of the client. Any reference to legal issues are only to help inventors and interested parties to better understand how these issues and patents effect the marketing aspects of invention commercialization. We highly recommend that you consult a qualified attorney regarding the law and patenting.

2 Switched Current Power Converter Transient and Frequency Response Edward Herbert July 29, 2005 The switched current power converter provides a very fast current and voltage control suitable for high di/dt without the usual bulk converter. With supplemental switched charge circuits, very rapid power up (< 1µsec) is possible as well as voltage regulator down transitions (< ¼ µsec). This presentation provides a short overview of the current control loop for a switched current power converter, or SCPC. There are several methods for controlling a SCPC, but a flash analog digital to analog converter fed by total charge sensing was chosen for this presentation for its high bandwidth (> 5 MHz) and good phase margin (> 145 ). There is a short discussion of the current control methods. This is followed by a summary of the results of a SPICE simulation. A transient response shows step changes in output current with di/dt of 100 and 200 amps per microsecond. Full control of the voltage is maintained through the current transitions. A graph of the output impedance from 100 khz to 20 MHz is also shown. The impedance remains below 0.5 mω to 5 MHz. There is a short discussion of the voltage control methods, both for power up and for voltage regulator down transitions. Following the summary report there are four appendices. Appendix 1 is incomplete, but in future revisions it will provide design guidelines for the selection of the impedance slope, hysteresis and capacitor size. Appendix 2 provides a fuller explanation of the total charge measurement system. Neither current measurement nor voltage measurement are suitable for a fast control. Total charge measurement is presented as an alternative having a much faster response. Appendix 3 describes a SPICE network with a power distribution that is based upon the impedances from an Intel guideline for VRM design. The bulk capacitors are left out because the control is fast enough that they are not needed. The SPICE models for the transient analysis and frequency response are described with the graphs from a number of simulations. Appendix 4 has SPICE simulations of several voltage control models. Graphs reflecting various scenarios are presented along with the SPICE models used to generate them. Following that is an analysis of the loss during charge transfer. Limitations due to connector impedance that were previously encountered with VRMs are alleviated. A fairly large additional series impedance is added to the SPICE model, to simulate a VRM that is not optimally close to the processor. The decoupling capacitors should be on the motherboard near the processor. The SCPC handles the extra impedance well, largely mitigating it. The model was chosen to show off this feature. July 29, 2005 Page 1 of 63

3 1.0. Switched Current Control: The control strategy of the switched current power converter is very simple: A current is established, and then it is switched to the output capacitor and the load as required. Figure 1.1. There is no faster control method than turning a switch on and off. For a higher current load, it is preferred to divide the current into a number of parallel paths. For a given total current, the total silicon area for the switches is comparable, so this can be done without an unreasonable cost penalty. It is tempting to compare a SCPC with a multi-phase buck converter, but that circuit has a very complicated control. A better analogy is a totem-pole buffer driver circuit. Figure 1.2. For currents that are less than full load, one or more of the switches is pulse width modulated so that the average current is correct. There are several designs for the current sources, and there are several designs for controlling the current. All have in common the digital interface to the MOSFET drivers, so the current source design and the control design are very independent, and the common interface allows great flexibility in circuit applications, mixing and matching easily for various power sources and various loads. July 29, 2005 Page 2 of 63

4 2.0 Measurement: 2.1. Flash Analog to Digital Converter: A fast current modulator needs a fast measurement and control system, and there probably is no faster measurement than a flash analog to digital converter. A number of comparators have as their references the nodes of a resistor ladder network. Figure 2.1. The outputs of the comparators of a flash analog to digital converter directly control the current switches, which are totem pole MOSFETs. This is a very fast control. The delay time from sensing a change of state to a change in output is the propagation time of the comparators and the switching time of the MOSFETs with their drivers, which is tens of nanoseconds. The comparators on the resistor ladder network directly control the current switches of the switched current power converter. The characteristic of a power converter with such a control has a decreasing voltage with increasing current, exactly what is usually specified for a processor power supply. For a simple system, no additional control or compensation is required. The accuracy is the accuracy of the resistor ladder network and the offset voltages of the comparators. There are no other amplifiers, with their accuracy, bandwidth and slew rate limitations. If there are several capacitors with significant parasitic impedance between them, using the output voltage as the control input requires a compensation network for stability. This can be avoided by using total charge measurement, explained below. July 29, 2005 Page 3 of 63

5 This presentation and the SPICE simulation are based upon a design with a fixed voltage reference. For specialized applications, the voltage reference may be replaced with an input pin or d-a converter, so that the output voltage can be varied in response to an external signal or VID. There may be an outer voltage loop, for a fixed output voltage or for remote sense. Because the current control loop is extremely fast, a very high bandwidth voltage control can be implemented. Figure 2.3. The output characteristics have a decreasing voltage with increasing current, just as is specified for many processors. However, it is difficult to have as large an output impedance as is usually specified for processors. Because the nodes of the resistor ladder network are at successively lower voltages, the output characteristics have a decreasing voltage with increasing current, as shown in figure 2.3. By dividing the voltage droop by the current, the output impedance is defined. Many processors specify a power source with a decreasing voltage with increased current. However, it is difficult to make a SCPC with an output impedance as high as is usually specified. The existing specifications for voltage droop are believed to represent the best capabilities of present power converters rather than a desired feature for processors. It stands to reason that a higher voltage at idle conditions does nothing for the operation of the processor, but it does substantially increase the power consumed by the leakage currents when the processor is not busy. These losses increase as a factor of voltage squared, so a lower output impedance is very beneficial. A practical resistor ladder network is somewhat more complex than the one shown in figure 2.1, because hysteresis must be added to limit the switch cycle frequency. See Appendix 1 for further considerations on hysteresis, output impedance, timing and capacitance size. July 29, 2005 Page 4 of 63

6 2.2. Total Charge Measurement: A total charge measurement with a flash analog to digital converter provides an extremely fast and stable control. It is extremely simple, thus inexpensive, and only the resistors of the ladder network and its voltage reference need be particularly accurate. It is unconditionally stable at any frequency and has a phase margin of nearly 180 degrees. Conceptually, the current can be controlled directly as a function of the output voltage. Practically, the voltage at the output is not a suitable control input if there are several capacitors with significant parasitic impedance between them, due to settling time. An objective of a power converter control is to provide a converter current that is equal, on average, to the output current demand, with small variations as needed to correct voltage errors. Ideally, as soon as there is a change in the output current demand, the converter current being supplied will change to equal it. For a high speed system, current measurement is not practical. Not only are current measurement circuits very complex, they are also hopelessly slow. Voltage measurement at the output is not suitable either, as it may take a long time to settle down, far longer than is useable for control purposes for a fast power converter. The solution is to measure the total charge of the capacitors in the power distribution system. This is an exquisitely sensitive measurement and it is immune to the voltage transients and ripple within the power distribution path. Remembering that current, in amperes, is the flow of charge, in coulombs per second, any mismatch of the input and output currents shows very quickly as a change in the total charge. Total charge is easily measured with a resistor network, with one resistor connected to each capacitor or group of capacitors. If the conductivity each resistor is proportional to the capacitance with which it is associated, the common node has a voltage that is proportional to the total charge on the capacitors in aggregate. Figure 2.4. The total charge on several capacitors can be measured with a resistor connected to each capacitor or group of capacitors. The conductivity of the resistor is proportional to the capacitance with which it is associated. July 29, 2005 Page 5 of 63

7 The total charge sense point becomes the inputs to the comparators of the flash analog to digital converter of figure 2.1. The resistors need not be particularly accurate and no amplifiers or active circuits are needed. The total charge sense can be thought of as a weighted average voltage measurement, nominally equal to the output voltage. If there is only one output capacitor, the total charge measurement and the output voltage are the same. The lead inductance of the capacitors causes some spiking in total charge sense signal that is easily rolled off with a small capacitor. The size of the capacitor is not critical, fortunately, as the lead inductance factor may not be well controlled. Performance is improved if an additional resistor is taken to the output voltage. The total charge system has a droop in the output voltage with increasing current, and the resistor to the output voltage partly compensates. The propagation delay through the comparators and the MOSFETs with their drivers is a lag, but it is small. Figure 2.5. The output voltage Vo as a function of the output current Io using total charge ΣQ control. With a total charge control, the steady state output voltage is given by the following equation, as shown graphically in figure 2.5. Vo = ΣQR Io RE Where (with reference to figure 2.4): ΣC = C1 + C2 + C3, in farads ΣQ = C1 V1 + C2 V2 + C3 V3 July 29, 2005 Page 6 of 63

8 ΣQR = ΣQ / ΣC, in volts RE = ( C1/ΣC) R4 + ((C1 + C2)/ΣC) R5 + R6, in Ω It can therefore be seen that ΣQR equals the no load output Voltage, Vo0, and RE is an impedance term. It can be seen that if C1 and C2 are small compared to the total capacitance ΣC, then RE is dominated by R6. For a dynamic analysis, substitute the appropriate complex impedance Z into the equations. The equations suggest that accurately measuring the charge Q on each capacitor is critical, which would raise concerns about the change of capacitance. In reality, the measurement still remains a voltage measurement, but it is weighted by a charge factor that provides stability in transients and at high frequency. In the SPICE model, changes of 50 percent had no noticeable effect on the output voltage or the dynamic response. Note in particular that the effects of the impedance R4 are reduced by the factor C1/ΣC. This means that if C1 is small compared to the total capacitance, the effect of the parasitic impedance R4 becomes small. This has particular implications for using the SCPC as a voltage regulation module (VRM) that is connected to a power distribution system through a connector. Any parasitic impedance in a power distribution system is undesirable, but if the output capacitance on the VRM is small compared to the total capacitance, and if a total charge measurement is used, the problem of the connector is largely mitigated. Note also that the RE term is attributable to the impedance of the current path through the power distribution system, and it is good practice to minimize this impedance to the extent possible. The total charge measurement system is shown in this presentation as a passive measurement with passive compensation as an input to a flash a-d converter directly driving a SCPC. Its performance is very good, so there may be little incentive to improve on it. However, it is also a suitable input for an error amplifier feedback system, which may allow more elaborate compensation schemes and active error reduction with a very high bandwidth. Conventional error analysis and feedback control techniques are applicable. The total charge measurement system is explained in further detail in Appendix 2 July 29, 2005 Page 7 of 63

9 3.0. Voltage Control for SCPCs: 3.1. Voltage Control by Varying the VID. With reference to figure 2.1, the output voltage Vo of a switched charge power converter can be changed by changing the reference voltage, Vref. The reference can be an analog input signal or it could use a d-a converter. If the VID is changed, the output voltage will follow if the change is not too fast. A reasonable limit for the model used for this presentation is about 90 mv per µsec increasing, and about half that decreasing. The limitation is the current available to charge the output capacitors, and the size of the output capacitance. For the example of a SCPC with 100 amp rated current, if the load is 35 amps, there is just 65 amperes available to charge the capacitor to a higher voltage. Reducing the voltage is a worse situation, as the SCPC usually cannot sink current, so decreasing the voltage relies on the load absorbing charge from the output capacitor. SPICE simulations and the models used are shown in Appendix Voltage Control by Switched Charge. The voltage V on a capacitor is given by the charge Q times the capacitance C. If the charge is changed, the voltage will change proportionately. If a precise charge is added to, or removed from, a capacitor, its voltage will step by a precise amount, and this can be achieved very quickly with solid state switching. Figure 3.1. When the switch changes state, a fixed charge Q is added to or removed from the output capacitor, resulting in a fixed step in the output voltage, up or down. Figure 3.1 shows a basic switched charge circuit, consisting of a totem pole driver and a capacitor Cq. When the driver goes high, as precise charge is transferred to the output capacitor, and when it goes low, a precise charge is removed, causing a precise and very fast output voltage step. The switched charge circuit has no ability to regulate the output voltage, only to step it rapidly. Continued voltage control is by controlling the current. The voltage reference July 29, 2005 Page 8 of 63

10 VID must simultaneously step by the same amount, or the current control would rapidly change the voltage Accuracy Considerations: Transferring a precise charge requires precision capacitors, not an attractive option in large scale manufacturing. Given the large variations in capacitance within the allowable tolerance, it may be necessary to trim the capacitance if precise steps are needed. Capacitors also change with operating conditions. However several aspects of the design are helpful. One is that the absolute accuracy of the capacitors is less important if the relative accuracy is good. Most environmental variables can be controlled by using the same style capacitor for all of the capacitors and having them mounted together so that their temperatures are the same. Another important consideration is that the accuracy of the output voltage is ultimately controlled by the VID input. If a step change is not precise, the voltage will rapidly slew to the voltage of VID input. As overshoot may be more serious than undershoot, the step change circuits may be designed somewhat low, maybe 10 percent. In this scenario, the voltage would step 90 percent of the transition, then slew the remaining 10 percent. This is a little slower, but an order of magnitude faster than slewing for the entire voltage transition Power Loss in Transferring Charge. When charge is transferred, some of the energy is lost. Over a number of cycles, this could represent a significant power loss. A processor uses much less power at a lower voltage, and none if the voltage is zero. If a processor can remain in a lower power state, or off, for more of the time by using switched charge voltage transitions, the trade-off is sound. Appendix 4 analyzes the power loss, with examples. If the power is cycled on and off fewer than 1,000 times per second, and if it changes level fewer than 10,000 times per second, the net power savings may be significant. July 29, 2005 Page 9 of 63

11 4.0. SPICE Simulations: A number of SPICE simulations have been done, and the results of one of them presented here. A further discussion of the details of the SPICE schematic and the response at various frequencies is shown in Appendix 3. The simulation is based upon a quite conservative model reflecting representative parasitic impedances from an Intel application notes, Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2, Intel document number (March 2005). The large bulk capacitors are left out, and additional impedance is added to simulate the SCPC being located in a separate module. Figure 4.1. The impedance versus frequency of the SCPC for a family of SPICE simulations using conservative motherboard and connector parasitic inductances. July 29, 2005 Page 10 of 63

12 Figure 4.2. A spice simulation of 50 amp step at 100 amps per µsec using conservative motherboard and connector parasitic inductances. July 29, 2005 Page 11 of 63

13 Figure 4.3. A spice simulation of 50 amp step at 200 amps per µsec. The dynamic impedance is increasing, so this may be the practical limit for di/dt unless parasitic impedances can be reduced. July 29, 2005 Page 12 of 63

14 Appendix 1 Design Guidelines A1.1. Hysteresis, Impedance, Capacitor Size and Timing In some respects, a SCPC controlled by a flash analog to digital converter is a modified hysteretic control. It is self-timing (though it can be synchronized to a clock if desired), with transitions occurring as the voltage reaches various thresholds. In a power converter with a specified maximum current and a given output capacitor, there are some useful bounds on how fast the output voltage can change. For example, with a maximum current of 100 amperes, and a 500 µf capacitor, the maximum rate of change of the capacitor voltage is 200 mv per µsec. For a SCPC that has multiple currents and a flash analog to digital control, another key parameter is the time that it takes to cross successive thresholds of the ladder network with a current error of one increment. Using the example of a SCPC with a maximum of 100 amperes having ten channels of 10 amperes each, the maximum rate of change in the capacitor voltage with a 10 amp error current is 20 mv per µsec, or 0.02 mv per nsec. Thus it takes 50 nsec for the voltage to change 1 mv with a 10 amp error current. This is significant, because that is a reasonable number for the propagation delay through a comparator and a MOSFET switch and its driver. In an ideal system, when the capacitor voltage ramps up to a threshold of the ladder network, the switch opens instantly. In practice, there is a propagation delay through the comparator and the MOSFET with its driver. As a result, the voltage continues to increase for the duration of the propagation delay, and the voltage will overshoot. It is important to know how much the voltage may overshoot for various conditions and to take it into account in the system design and tradeoffs. To be continued and expanded, with figures and equations. July 29, 2005 Page 13 of 63

15 A2.1. Total Charge Control: Appendix 2 Total Charge Sensing If there is a single capacitor in a power system, total charge sensing and voltage sensing are equivalent, as the charge is linearly related to voltage. Q = C V, so V = Q / C. For many purposes, total charge sensing can be equated to output voltage sensing. However, there are important differences, which are explained below. Figure A2.1. Total charge sensing can be substituted for output voltage sensing, and it is unconditionally stable This problem of instability due to the parasitic inductances is overcome if the charges on all of the capacitors in the power converter are measured and summed as the control input. The circuit is exquisitely sensitive to differences between the converter current and the output current demand. The converter current is precisely controlled, the bandwidth is very high (greater than 100 MHz) and it is unconditionally stable. If the power distribution system is under-damped, there may be oscillations and ringing in the voltages on the various capacitors, but this is invisible to the control system. In SPICE simulations, using representative parasitic impedances from several microprocessor specifications, it seems that a typical layout is fairly well damped, but this is an area of concern for designers. In one simulation, using reduced capacitance and reduced stray impedances to anticipate future developments, some ringing was seen. This may not be a problem in real world power distributions. Sometimes SPICE simulations give an unrealistically optimistic performance. However, using pure inductance, not complex inductance, likely simulates a higher Q circuit than would exist in real circuits. The imaginary part of the complex impedance is lossy and the loss increases rapidly with frequency, so a real parasitic inductance may be well damped at the ring frequency. July 29, 2005 Page 14 of 63

16 A2.2. Total Charge Measurement, ΣQ: If the total charge in the various capacitors is measured and summed, a very fast and accurate control is possible. To introduce the concept of total charge, ΣQ, please see figurea2.2, which implements the voltage measurement of figure A2.1, except that differential measurement is used to account for ground differences. The voltages of the various capacitors C1 through C3 are measured differentially, to account for ground differences. The charge on a capacitor is determined as the voltage times its capacitance. If the summing resistors R1 through R3 have their conductivity (1/R) proportional to the capacitance, the output of the summing amplifier is proportional to the total charge, ΣQ. Because the total charge ΣQ is linearly proportional to the voltage, it can be used for control purposes as a substitute for the output voltage, with appropriate scaling. ΣQ = Σ(Vn Cn), and the total capacitance ΣCn is assumed to be constant. Figure A2.2. The voltages of the various capacitors in the system are measured differentially, to remove ground differences. The voltages can then be summed, factored by the value of each capacitor. The sum is the total charge, ΣQ. July 29, 2005 Page 15 of 63

17 A2.3. Simpler, Faster Charge Measurement: Figure A2.3. If the conductivity (1/R) of the resistors is proportional to the capacitance of the associated capacitors, the output is proportional to the total charge, ΣQ. The circuit of figure A2.2 is useful for explaining the concept of total charge measurement, but it has the disadvantage that a large number of precision resistors and very fast amplifiers are needed, if a large number of points in the circuit are to be measured. Further, the settling time through the amplifiers in series, each with its response and slew rate limitations, results in a significant lag. A much simpler and faster circuit is shown in figure A2.3. It is suggested that two layers of the current distribution bus be devoted to the total charge measurement. Because these two layers do not conduct significant current, their foils may be thinner. At a number of points throughout the system, measurement points consisting of two resistors can connect the various capacitors throughout the power distribution to the total charge measuring system, as shown, one on the power side and one on the return side at each point. Three resistor pairs are shown in figure 2.4.4, for simplicity, but it is contemplated that a large number of measurement points would be used, including points on the processor die. The resistors need not be precise. Likely, screened on resistive ink would suffice. The relationship of the resistors can be expressed by the following equations: C1 R1a = C2 R2a = C3 R3a = = Cn Rna C1 R1b = C2 R2b = C3 R3b = = Cn Rnb There may be transmission line effects, and it may be advantageous to consider impedance matching in choosing the value of the resistors, particularly the ones that are July 29, 2005 Page 16 of 63

18 furthest from the control circuits. Obviously, they cannot all be the ideal value for impedance matching, but the more critical resistors can be optimized, and the others can be selected as ratios of them using the above formulae. Note that the equations do not require that the high side resistors and the low side resistors be equal, and it may be desirable to use smaller resistors in the return side, for a lower impedance ground return. Such considerations are a tradeoff of a particular application. SPICE simulations show that the circuit is quite insensitive to the values of the resistors and capacitors, with variations of 50 percent having little effect on the performance. A2.4. Calculating the Output Voltage, Vo: Control of the total charge ΣQ does not control the output voltage Vo directly, unless the output voltage Vo is taken directly from the capacitor and there is only one capacitor (or there is zero impedance between capacitors). With distributed capacitors having impedance between them there will be voltage drops in the system, which will affect the output voltage Vo. At steady state conditions, only the resistances are applicable, and the output voltage calculations are straightforward. Figure A2.4. For steady state conditions, the circuit of figure A2.1 reduces to this equivalent circuit. Because R7, R8 and R9 are large, they conduct negligible current, so the current from the SCPC equals the output current Io. To calculate the output voltage Vo at steady state conditions (with reference to figure A2.4), let V1, V2 and V3 equal, respectively, the voltages on the capacitors C1, C2 and C3. By inspection, the charge on the three capacitors is Q1 = C1 V1 Q2 = C2 V2 Q3 = C3 V3. July 29, 2005 Page 17 of 63

19 Therefore, the total charge ΣQ is given by ΣQ = C1 V1 + C2 V2 + C3 V3 Also, by inspection, given an output current Io, V1 = Vo + Io (R4 + R5 + R6) V2 = Vo + Io ( R5 +R6) V3 + Vo + Io R6 To simplify the final expression, let us define a total capacitance ΣC, a total charge reference ΣQR, and an equivalent resistance RE as follows: ΣC = C1 + C2 + C3, in farads ΣQR = ΣQ / ΣC, in volts RE = ( C1/ΣC) R4 + ((C1 + C2)/ΣC) R5 + R6, in Ω Substituting, collecting terms and rearranging yields the following expression for the output voltage Vo: Vo = ΣQR Io RE It can therefore be seen that ΣQR equals the no load output Voltage, Vo0, and RE is a resistive impedance term. It can be seen that if C1 and C2 are small compared to the total capacitance ΣC, then RE is dominated by R6. July 29, 2005 Page 18 of 63

20 Figure A2.5. The output voltage Vo as a function of the output current Io using total charge ΣQ control. The equations suggest that accurately measuring the charge Q on each capacitor is critical, which would raise concerns about the change of capacitance. In reality, the measurement still remains a voltage measurement, but it is weighted by a charge factor that provides stability in transients and at high frequency. In the SPICE model, changes of 50 percent had no noticeable effect on the output voltage or the dynamic response. The extension to ac analysis is straight forward. For each of the resistors in figure A2.4 that represent parasitic impedances, the ac impedance Z can be substituted. Also include the ac impedances representing the capacitor ESL and ESR. The equations rapidly become complex, so SPICE simulations are suggested, and that is the approach taken in Appendix 3 and Appendix 4 and summarized below. A2.5. Output Voltage Vo for a SCPC Using Total Charge Control: When total charge control ΣQ is used with a switched current power converter that uses a flash a-d to directly control the current switches, as in figure 2.1, the total circuit impedance is the sum of the impedance Rs attributable to the resistor ladder network plus the impedance RE due to the total charge ΣQ control. Vo = Vo0 Io (Rs + RE) Figure A2.6. When total charge ΣQ control is used with a switched current power converter in which a flash a-d directly controls the current switches, Rs and RE combine to define the total circuit impedance. It can be seen from the equations that the impedance beyond the last capacitor is very critical. It is also desirable to have as much of the capacitance as close to the load as possible. Output voltage ripple is decreased if the upstream capacitors are smaller, July 29, 2005 Page 19 of 63

21 relative to the total capacitance, as this largely mitigates the effects of the upstream motherboard and connector parasitic resistance and inductance. A2.6. Overcoming Parasitic Impedance. For a low voltage, high current power supply of conventional design, parasitic impedances in the path of current flow is a serious problem. It takes a significant driving voltage to increase the rate of current flow in an inductor, and a higher voltage just is not available. This problem is largely overcome with a SCPC using total charge measurement and control. The equations from A2.4, repeated below, show that the impedance R4 is significantly attenuated if C1 is small compared to the total capacitance, ΣC. In the circuit of figure A2.4, the impedance R4 simulates an impedance at the connector of a remote VRM. The decoupling capacitors are assumed to be on the motherboard near the processor. RE = ( C1/ΣC) R4 + ((C1 + C2)/ΣC) R5 + R6, in Ω Vo = ΣQR Io RE An expression in an equation may not make much sense without a feel for what is happening in the circuit. The capacitor C1 may, as an example, be an output capacitor of a VRM that is remote from the decoupling capacitors and the load. However, it is part of the total charge sensing circuit, and, being directly connected to the VRM, it will be the first to see a response to a drop in the output voltage and the total charge. As an example, let us consider a twp capacitor system with an output capacitance of 380 µf, and C1 is 20 µf,.for a total capacitance ΣC of 400 µf. If the output voltage decreases 5 mv, the charge Q is decreased by 2 µc. If this charge is replaced entirely on C1, it will result in a voltage rise of 100 mv. This is sufficient voltage to drive the current through the parasitic impedance much more rapidly. Yet the total charge sensing and control prevents the voltage from rising excessively, and as the charge is transferred to the output capacitor, the voltage on the input capacitor C1 decreases so that the total charge remains correct. The total charge system measures total charge, and is immune to voltage oscillations within the power distribution network. It will maintain the correct total charge even if the capacitors are ringing. It is very desirable that the power distribution be a damped system. Because the imaginary part of the complex inductance is lossy, and the losses increase rapidly with frequency, it is likely that most real power distribution systems will be damped at the critical frequency. A2.7. Modified Total Charge Sensing Performance may be improved with the addition of a resistor to the output voltage Vo from the total charge sense line. In the SPICE models discussed in this presentation, a lead-lag network was used here, resulting in lower impedance to a higher frequency. July 29, 2005 Page 20 of 63

22 Figure A2.7. The total charge sense can be modified with a resistor to the output voltage. In the SPICE models, a lead-lag network was used for R3. Let us define a resistance Rp equal to the parallel combination of R7, R8, and R9. Using R3, the equation of A2.4 (Vo = ΣQR Io RE) becomes R3 Vo = ΣQR Io * RE R3 + Rp In the SPICE models, R3 is approximately equal to Rp and has a lead lag around it. The impedance attributable to the total charge sense is reduced by one half and the response at 5 MHz was significantly improved. In the limit, with a very small R3, the circuit reduces to a feedback from Vo, and stability issues will be seen. ΣQR was shown in A2.4 to be the no load voltage, which in many processor power supplies is a digital input VID. July 29, 2005 Page 21 of 63

23 A3.1. Schematic: Appendix 3 Switched Current SPICE Simulations: The schematic in figure A3.1 shows the SPICE schematic used for the transient and frequency response simulations. The load impedance network is based upon the equivalent circuit for the motherboard and socket from Intel Design Guidelines, Document Number , Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2, March 2005, The large bulk capacitors were left out, as they are not necessary for the switched current power converter. An additional parasitic inductance (L1) and resistance (R6) were added to simulate case where the power converter is not optimally close to the power supply, though it is assumed that the bypass capacitors are optimally close to the processor on the motherboard. These were used to simulate a VRM connector, and to show off that the total charge measurement and control system largely negates its effects. Because the decoupling capacitors are to be on the motherboard, the impedances for the EVRD model were used. Various funny components appear in the circuit, and are necessary for the SPICE simulation to run well. Some of these are mysterious, and serve as a caution that these simulations must be accepted for what they are, simulations. In the SPICE model schematic of figure A3.1, the switch current power converter is the behavioral current source B3 at the left. The total charge measurement system is shown at the bottom, and the node TQ (for total charge ) is the control input for the current control algorithm. The SPICE used is Intusoft ICAP/4. It is suggested that the reader duplicate the model and try the simulations. The load is the behavioral current source B1, and its current is controlled by the programmed voltage source V1. The capacitor C9 was needed for the current source B1 to operate correctly. For the transient simulation, the current may be programmed as shown in the chart at the right. The transient simulation time is 11 microseconds, of which the first microsecond is not displayed, to allow for the initial conditions to settle. Four 50-amp pulses, from 35 to 85 amperes, are shown, with di/dt, respectively, of 200, 500, 1000 and 2000 amps per microsecond. This simulation is not shown in this revision of the write-up, as the higher di/dt is very dependant on the parasitic impedances, and this presentation is directed to the response of the SCPC. Step current changes were also simulated from 35 to 85 amperes at 100 and 200 amps per µsec, to show the usual Intel step load test and to show the circuit at its practical limit, respectively. July 29, 2005 Page 22 of 63

24 Figure A3.1. The SPICE model for the transient and frequency response measurements. July 29, 2005 Page 23 of 63

25 For the frequency response and impedance measurements, the voltage source V1 is programmed as a sine function with a 50 ampere offset and a 50 ampere peak to peak sine wave at the various frequencies. The impedance in the graph is the peak to peak voltage at the output Vo divided by 50, the peak to peak current Io. The details of the switched current power converter SPICE model is shown in figure A3.2. The algorithm for the behavioral current source B3 provides a current output as a function of the control input TQ. The fundamental equation is: Ic = * TQ By using the int function, the decimal part of the expression is discarded. By applying this to an expression of one-tenth the value, then multiplying by ten, the output is constrained to be in discrete 10 amp increments, as in a switched current power converter with ten channels of 10 amps each. The expression is limited to values between 0 and 100 amperes. The Vhys function simulates hysteresis. Figure A3.2. The SPICE model for the switched current power converter. The filters on the Vhys and TQ functions were necessary for the SPICE simulation. July 29, 2005 Page 24 of 63

26 A3.2. Transient Response Simulation: The figure A3.3 shows the SPICE simulation for the circuit described above for a 50 ampere step in current with a di/dt of 100 amps per µsec. This is one of the tests often cited in Intel specifications and application guides. It is easily handled by a switched current power converter as the transition is slow enough that the voltage is regulated through the transition. Figure A3.4 shows the SPICE simulation at 200 amps per µsec. This may be about the practical di/dt limit to maintain regulation through the current ramp. It can be seen that the current has saturated high, allowing an undershoot. The SPICE simulation does not simulate the propagation delay through the comparators and the MOSFET switches and their drivers. With a rise time of 250 ns, the delay will make the real undershoot greater. A 50 nsec delay may be practical, which would suggest that the undershoot might be 20 percent more. Higher di/dt capability will depend upon a significant reduction in the parasitic impedances. This may be practical, but it is the subject of a future presentation. July 29, 2005 Page 25 of 63

27 Figure A3.3. The static and dynamic impedance with a 50 amp step current from 35 to 85 amps at 100 amps per µsec. July 21, 2005 Page 26 of 63

28 Figure A3.4. The static and dynamic impedance with a 50 amp step current from 35 to 85 amps at 200 amps per µsec. July 21, 2005 Page 27 of 63

29 A3.3. Frequency Response Simulation: Figure A3.5 shows the output impedance Z versus frequency for the switched current power converter SCPC. The impedance is the peak to peak output ripple voltage divided by 50, the peak to peak load current ac component. The Natural curve was taken with a fixed dc 50 amp current Ic from the power converter source B3, so that the only source for the 50 amp ac component of the load current Io is from the capacitors. Figure A3.5. The output impedance of the switched current power converter SCPC is the peak to peak output voltage divided by 50, the peak to peak current load, at various frequency. Following are eight graphs showing the raw simulation data for the impedance curve of figure A3.6. In each case, the simulation was run for several cycles before the graph was started, so initial conditions could settle. The ripple voltage is about 5 mv peak to peak. July 21, 2005 Page 28 of 63

30 July 21, 2005 Page 29 of 63

31 July 21, 2005 Page 30 of 63

32 July 21, 2005 Page 31 of 63

33 July 21, 2005 Page 32 of 63

34 July 21, 2005 Page 33 of 63

35 July 21, 2005 Page 34 of 63

36 July 21, 2005 Page 35 of 63

37 July 21, 2005 Page 36 of 63

38 Appendix 4 Voltage Transition SPICE Simulations: A4.1. Voltage Change by Ramping VID: A very simple way to vary the output voltage of a switched charge power converter is to vary the reference voltage on the resistor ladder network. This can be from an input analog signal, from a d-a converter or from an amplifier in a feedback system. While very simple, this method of voltage control is limited by the saturation current, high or low, of the switched current sources. The fastest scenario is to step change the voltage reference, then have a voltage good signal when the voltage matched. With a slower varying reference, the output voltage will track the VID faithfully. Presently, when a processor changes voltage to save power, the phase locked clock is resynchronized. Perhaps with a well-behaved power supply, the processor clock can be designed to slew, commanding the necessary input voltage as the clock rate varies. Following is a SPICE simulation in which the VID input was ramped slowly enough so that the switched current source did not saturate. At the start of the simulation it is assumed that the voltage and current are stable at the minimum voltage and a 35 amp output current. Because a 35 amp, and the maximum current available is 100 amps, the ramp up is faster than the ramp down, The limit increasing is about 90 mv per µsec, and decreasing it was about half that. Following the SPICE simulation is the SPICE schematic. The reader is encouraged to do his own SPICE simulation and experiment with various scenarios. In the SPICE schematic, the VID response is included in the current source algorithm. The VID input is simulated in the programmed voltage source VID. The program steps (time and voltage) are shown in the table next to the voltage source. A second voltage source V1 programs the output current. July 21, 2005 Page 37 of 63

39 July 21, 2005 Page 38 of 63

40 July 21, 2005 Page 39 of 63

41 A4.2. Voltage Change using Switched Charge and Ramped VID: A switched charge circuit is a totem pole output driving a capacitor. When the driver changes state, a fixed charge is added to or removed from the output capacitor(s). Adding or removing a fixed charge causes a fixed change in the output voltage, up or down. The voltage step is accurate, but the final output voltage depends upon the starting voltage. One application for a switched charge circuit is to ensure a rapid turn on. In the SPICE simulation following, a switched charge circuit adds sufficient charge to the output capacitors to step the output voltage from zero to the minimum VID voltage. From that point, voltage control is by VID ramping. At the end, the voltage is returned to zero. The voltage rises to the minimum VID in a few hundred nanoseconds without significant overshoot. Full load current can be applied immediately. Because the switched charge controls the voltage step, the final output voltage depends upon the starting voltage. It may be well to include some protective circuits to ensure that the step does not occur if the starting voltage is too high. For a step from zero, a MOSFET clamp to ground during the off time would suffice. The accuracy of the voltage step requires that the capacitors have a fairly accurate relationship. The absolute accuracy is less important, but the relative accuracy determines the accuracy of the step voltage. Temperature effects may be compensated by using the same style capacitor close together, so that they are at the same temperature. It may be necessary to trim the capacitors at assembly. The step voltage also depends upon the driving voltage source, so an auto-trim is possible. The SPICE schematic follows. Because the switched current circuits have four capacitors separated by parasitic inductance, the totem pole driver (simulated as a controlled voltage source Vs) drives four capacitors. It is probably sufficient to use one capacitor feeding the largest output capacitor, but the extra small capacitors are not a significant expense. July 21, 2005 Page 40 of 63

42 July 21, 2005 Page 41 of 63

43 July 21, 2005 Page 42 of 63

44 A4.3. Using Switched Charge for Voltage Regulator Down. Newer processors enter a reduced voltage mode to save power. With present power supplies, this is a long and complicated process. A switched charge circuit can be used to change voltage in a discrete increment very rapidly and accurately. The switched charge circuit only causes a step in voltage, it has no ability to regulate the output voltage. Accordingly, there must be a simultaneous step change in the VID reference voltage. The accuracy of the voltage steps is dependent upon the relative values of the capacitors. If the accuracy is uncertain, the voltage steps can be designed to be nominally somewhat low. As long as the step in the VID reference is to an accurate voltage, the output voltage will step rapidly to nearly the correct voltage, then it will ramp quickly to a very accurate final value. Following is a SPICE simulation showing a switched current power converter having a switched charge circuit that can step the output voltage up and down about 0.4 volts on command. The settling time is about 100 nsec. Three scenarios are shown, as illustrations. In the first, from 0 to 10 µsec, the voltage is stepped from 0 volts to a minimum VID. Then it is stepped 0.4 volts more. Finally, it is stepped back to 0 volts. Full output current is immediately available, as can be seen in the output current trace Io. The next example, from 15 to 25 used, shows the voltage stepping from 0 volts to a minimum VID, then ramping up to a working VID. When commanded, the voltage steps to a higher working VID, then back, then up again, then ramps down, then steps back to 0 volts. The third example shows the voltage steps commanded at the same time, so the voltage steps to the higher VID immediately. It may then ramp down somewhat, to adjust the output voltage to an optimum upper VID. From there it can step down to a lower working VID. Between the switched charge steps and the VID ramping, any voltage within its range can be achieved. The SPICE schematic follows. Because it was getting rather busy, the schematic has been divided into two pages, and the switched charge circuits are on the second page with the programmed voltage source tables. This is the SPICE model from which the graph was run. The reader is encouraged to make his own model and experiment with it. This SPICE model includes a clamp at 0 volts. The resistor R38 on the second page is either 0.01 Ω 1,000 Ω, depending on the output of the behavioral circuit B5. This senses VID, but it could as well be a digital command for off. July 21, 2005 Page 43 of 63

45 July 21, 2005 Page 44 of 63

46 July 21, 2005 Page 45 of 63

47 July 21, 2005 Page 46 of 63

48 A4.4. Voltage Change with Multiple Switched Charge Circuits. For faster output voltage changes, the voltage can be changed entirely with switched charge circuits. In the example shown, the output voltage steps to a minimum VID, then there are two more increments of about 0.4 volts. These can be used in any combination, superposed or sequenced, and the SPICE simulation graph following shows some representative examples. In the first scenario, from 1 to 10 µsec, the voltage steps up in three increments, in sequence, then it steps back to 0 volts in one step. The rest of the graph shows the output voltage immediately stepping to the highest voltage, then following a number of steps as examples, finally stepping to 0 volts. An entirely digital voltage control can be implemented using a binary series of switched charge circuits. Any binary change will result in an step change to the new value. As before, there must be a simultaneous step change in the VID reference voltage, and any errors in the voltage steps will be adjusted by rapidly slewing to the desired voltage. The switched charge circuits lose some energy at each transition, so the frequency of voltage change may have to be limited. An analysis of each scenario must be done at design. It is conservative, it seems, to step from 0 volts to operating volts and back 1,000 times per second, and between voltage levels in steps at 10,000 per second. July 21, 2005 Page 47 of 63

49 July 21, 2005 Page 48 of 63

50 July 21, 2005 Page 49 of 63

51 July 21, 2005 Page 50 of 63

52 A4.5: Binary Switched Charge SCPC. The fastest and most flexible voltage control option is the switched current power converter with a binary switched charge circuit. In the example, five switched charge circuits have a binary relationship, each subsequent switched charge circuit having half the capacitance of the previous one, so that charge is transferred to, or removed from, the output capacitor in binary increments. With five binary switched charge circuits, 32 discrete increments of voltage may be.commanded. In addition, a sixth switch charge circuit is used for turn on, and adds sufficient charge to the output capacitor to establish the minimum output voltage, if used alone. Because any combination of the switches can be turned on, the output voltage can rise to any increment within its operational range upon turn on or at any time thereafter. Bu changing the binary command in a step, the voltage will step to any other increment within its operational range or it may be stepped to zero. The binary steps may also be commanded very rapidly in sequence, to achieve a very fast and accurate voltage slew between the first and final binary values. In the graph following, a number of scenarios are played out. Between 1 and 5 µsec, the output voltage steps, following the VID, as the load is pulsed. At 9 µsec, the voltage goes to zero simultaneously with the load going to zero. Between 13 and 14 µsec, the foltage slews very rapidly from the minimum to the maximum of its operational range. Again at 15 µsec, it turns off. Between 17 and 19 µsec, the circuit turns on, a pulse of maximum current is applied and removed, then it turns off, all within about 1 ½ µsec. This last scenario may be important for power reduction for a processor that has to respond rapidly and intensively when interrupted but is idle most of the time. Its net power consumption is very low, for cool operation or long battery life. The six switched charge circuits can be seen on the second page of the SPICE model, following the graph. July 21, 2005 Page 51 of 63