Understanding and Optimizing Electromagnetic Compatibility in Switchmode Power Supplies

Transcription

1 Understanding and Optimizing Electromagnetic Compatibility in Switchmode Power Supplies Bob Mammano and Bruce Carsten ABSTRACT Electromagnetic noise issues have long been a concern with switching power supplies, as their highfrequency switching of voltage and current generate higher order harmonics that have the potential to cause interference with system operation. While international specifications and standardized testing procedures have at least provided a greater understanding of the problems, optimum solutions must still come from techniques that are applied during the design process. This topic attempts to describe the more significant causes of EMI in power supplies and offer design techniques to minimize their impact. I. INTRODUCTION While switchmode power supplies are well known and appreciated for their significant benefits in reductions to both physical size and internal power loss, the threat of generating electromagnetic interference (EMI) from the high frequencies inherent in their fast-changing voltage and current waveforms has always been a serious concern. As advances in power supply technology have increased switching frequencies, and allowed these supplies to be used in closer proximity to the systems they power, these concerns and the demands that designers react to them have only heightened. Thus, designing for electromagnetic compatibility (EMC) has become a requirement every bit as important as meeting a given set of power conversion performance specifications, and it is the purpose of this discussion to address some of the more important principles and techniques involved. First, note that while we have used the terms EMI and EMC interchangeably, it should be clear that one is the inverse of the other. The accepted definition of EMI is: the interference of one piece of electronic equipment on the operation of another by means of electromagnetic energy transfer. And electromagnetic compatibility (EMC) is the absence of EMI. Two things follow from this definition. The first is that EMC is a system-level consideration. While it is common to test for electromagnetic noise generation from a power supply as a stand-alone box, the ultimate standards that have to be met apply to the system as a whole with the power supply as an internal component or subsystem. And the second aspect of this definition of EMI is that it involves three elements: A generator of electromagnetic energy: (a source). Transmission of that energy between equipments: (a coupling means). A receptor circuit whose operation is negatively impacted by the transmitted energy: (a victim circuit). All three elements must be present for EMI to take place remove any one and there can be no interference. However, while shielding or separation may solve a specific interference problem by attacking the coupling or susceptibility part of the system, the preferable approach is to remove the problem at the source and that will be the thrust of this discussion. 1-1

2 II. UNDERSTANDING EMI While it may at times seem otherwise, EMI is not a black art. Although often neglected in basic circuit design education, and appearing sometimes to be quite complex in practice, the basic principles for both causing and correcting EMI are relatively simple. Fundamentally, it requires a recognition of the fields caused by rapidly changing currents and voltages. While these characteristics are quantitatively described by Maxwell s equations, we need only to know that electronic noise may be induced by coupling between circuit elements through the action of either a magnetic or an electric field. A magnetic field will cause a changing current in a conductor to induce a voltage in another according to: e M di dt where M is the mutual inductance between the source and the victim. Similarly, an electric field will cause a changing voltage on a surface to induce a current to flow in another conductor according to: i C dv dt where C is the capacitance coupling the source to the victim. These equations tell us that where we have rapidly changing currents as in the conductors in series with power switching devices we can expect to see an induced voltage across other conductors coupled by a mutual inductance. And where there is a high dv/dt as on the drain contacts of the power switching FETs any parasitic capacitance can couple an induced current into another path. While it may not be very helpful, it should probably be noted that one of the most obvious ways to reduce generated EMI would be to slow down the switching transitions, but the cost in increased switching losses typically makes this a less viable solution. One important point to keep in mind on this subject is that EMI is a very low energy phenomenon! Because it can take an extremely small amount of energy, induced at the right place in the victim, to upset system performance, noise specification limits have been established at very small values. For example, at 1 MHz, it takes only 0 nw of measured EMI power to fail FCC requirements. This could be experienced with energy coupling of just a few parts per billion. Thus an easy trap to fall into is to discount some possible noise sources as too insignificant to be worth considering. III. MEASURING EMI When we describe a potential noisegenerating system, the transmission of the noise out of the system is by either or both of two separate coupling paths: as radiated energy from the system itself by way of magnetic or electric fields (as described above), or as conducted energy flowing in either the input, output, or control lines connecting the system under evaluation to the rest-of-the-world, where these lines can then become secondary radiators. These conducting and radiating EMI noise sources are considered as separate and distinct and are typically specified separately when evaluating the external characteristics of a definable system. One helpful characteristic, however, is that the efficiency of noise coupling is frequency dependent - the higher the frequency, the greater the potential for radiated EMI, while at lower frequencies, problems are more likely to be caused by conducted noise. There seems to be universal agreement that 30 MHz is the crossover frequency between conducted and radiated EMI. Most regulating agencies throughout the world have thus established measurement standards specifying the evaluation of conducted EMI at frequencies up to 30 MHz, with a separate set of standards applicable above 30 MHz for radiated EMI. We will discuss these two types of noise sources separately, but before doing so, some additional comparative information might be helpful. 1-

3 Conducted noise is primarily driven by current but is measured as a noise voltage by using a 50-Ω current shunt. Moreover, with our discussion herein limited to power supplies, the FCC position is that only the ac input power lines are of concern, since it is here where noise currents could most readily couple to other systems through the power distribution network. While the maximum frequency of interest for conducted noise is 30 MHz, the minimum frequency limit can vary. In the United States and Canada, that limit is usually 450 khz but many international specifications place the lower limit at 150 khz. And some telecom specs require testing all the way down to 10 khz. With radiated noise specifications starting with a lower limit of 30 MHz, the upper limits can range from a few hundred MHz to 1 GHz or more. And while conducted noise can be evaluated with not much more laboratory equipment than a spectrum analyzer and a coupling device, radiated noise requires the measurement of magnetic or electric fields in free space, causing the testing to become much more complex. For this reason, radiation testing is usually performed by a separate, specialized test facility, where variables inherent in the testing environment may be very closely defined and controlled. And speaking of variables, a non-trivial decision that needs to be made right at the beginning, is which specification to use. We have already alluded to the fact that each country has its own set of specifications for EMI, but within this distinction, there are additional determinates defined by product type and usage. For example, some specs define power supplies as digital devices while others combine them with information technology specifications. System usage also defines Classes where Class A designates industrial and commercial applications, and Class B includes residential usage. Class B limits are typically more stringent under the assumptions that systems made for the home are likely to be in closer proximity, and that residential users typically have fewer options available for dealing with EMI. In the United States, the Federal Communications Commission (FCC) owns the responsibility for the control of electromagnetic interference through the Code of the Federal Register (CFR), Title 47. Within this document, Part 15 controls Information Technology Equipment (ITE), Part 18 covers Industrial, Scientific and Medical Equipment (ISM), and Part 68 regulates equipment connected to a telephone network. International EMI specifications have been led by the International Electrotechnical Commission (IEC), which has published a European Union generic standard for emissions (EN50081), and the French-led Comité International Spécial des Perturbations Radioélectriques (CISPR). This latter body has issued their specification - CISPR Publication - which is gaining world-wide acceptance and, in so doing, is applying pressure for FCC acceptance of the same standards. At the time of this writing, noteworthy differences between the FCC and CISPR specifications include, in addition to some limit value differences, a lower frequency range for CISPR conducted noise measurements, and radiation tests made at a fixed distance of 10 meters vs 3 to 30 meters for FCC testing. By extrapolating the FCC radiation limits to 10 meters (linearly proportional to 1/distance) the comparisons can be better illustrated with the [Ref. ] frequency plots shown in Figs. 1 and. Voltage - dbµv FCC CISPR Fig. 1. Conducted noise limits, (FCC Part 15 vs. CISPR ). CISPR FCC CLASS A CLASS B Frequency - MHz 1-3

4 Field Strength - dbµv/m Measuring Distance 10 m CLASS A CLASS B FCC CISPR FCC CISPR Frequency - MHz Fig.. Radiated noise limits, (FCC Part 15 vs. CISPR ). Note that the units in these specifications are given as dbµv for direct measurements of conducted noise and dbµv/m for field strength measurements of radiated noise as sensed with an antenna. These are decibel values giving the ratio between the actual voltage measurement and one microvolt. The calculation is: V dbµ V 0log10 1.0µ V and it applies to both volts and volts/meter. Finally, with all the variables we have been discussing, we have not mentioned one that you might consider quite important - the operating conditions of the equipment under test. The reason is that this raises so many other questions that it defies definition. For example, do you test at the highest input voltage where dv/dt will likely be at a peak, or at the lowest voltage, maximum load where di/dt will probably be highest? And in the power circuitry, there is one current path when the power switch is on and another when it is off, so duty cycle is likely to be a variable. As a result, in most cases the operating conditions are left to whatever the manufacturer defines as typical but suppliers should recognize this as a potential issue in correlating data. IV. CONDUCTED EMI We now will delve more specifically into the causes and design implications of each of the two major categories of EMI, focusing initially on conducted noise as measured on the power supply s input power feed lines. To observe conducted noise on a power line, a device is needed to separate the high-frequency noise signals from the input current, and that device is called a Line Impedance Stabilization Network, or LISN, and shown schematically in Fig. 3. Power Source Ground 10 µf LISN 50 µh 50 Ω 10 nf to 330 nf* * Capacitor value determined by lowest specified frequency. Power Supply Input To Spectrum Analyzer Fig. 3. A 10/40 VAC, 60 Hz LISN circuit. All measurements are made with respect to ground. This device allows the use of a spectrum analyzer to measure the noise current through a 50-Ω source impedance while isolating the measurement from any high-frequency shunting which might exist in the power distribution network. Typically, a LISN network is added to each of the input power lines and the noise signals are measured with respect to ground. Conducted noise at the power supply s input can be further sub-categorized into two separate modes of current flow: differential mode (DM) noise, as measured between the power feed and its return path; and common mode (CM) noise which is measured between each of the power lines and ground. The contributors to these two modes are inherent to the basic operation of a switching power supply. The action of the internal power switches causes rapid di/dt changes in the differential current at both the input and outputs of the power supply, as illustrated in Fig. 4. Of course, input and output filters ideally would eliminate any high frequency noise external to the power supply, but neither can do the job completely. So residual ripple and switching spikes exist as a differential mode noise source with current flow bidirectionally into one terminal and out the other. 1-4

5 INPUT NOISE OUTPUT NOISE Fig. 4. Differential mode (DM) noise current is produced by normal switching action. There are also sources of rapidly changing voltage within the power supply which can couple noise through parasitic capacitance to earth ground, some of which are shown in Fig. 5. This type of noise in the ground path, which can be seen as common mode noise on all power supply terminals, is measured with respect to ground. The paths for both DM and CM noise currents at the power supply s input are shown in very simplified form in Fig. 6, which also shows the application of two LISN devices, in series with both the power line input and its return. Note that both CM and DM modes of current are present in each LISN but, with the polarities shown, the power line LISN measures CM + DM, while the LISN on the neutral return measures CM DM. Both of these quantities are vector sums and, where necessary, there are circuit networks that can be used to separate CM [Ref. 9] and DM signals, but the specifications typically do not differentiate. The total noise at each input must be measured because, with the possibility of multiple current paths within the power supply, there is no reason to assume that the values of the CM and DM contributions at the two inputs are identical. Capacitive Currents Primary to Secondary Input Noise Output Noise Chassis Ground Chassis Ground Chassis Ground Capacitive Currents Direct to Chassis Fig. 5. Common mode (CM) noise occurs when transients from switching voltages are coupled to earth (or chassis) ground through parasitic capacitances. LINE Two LISN Circuits CM GROUND DM SMPS OUTPUTS NEUTRAL CM Spectrum Analyzer 50 Ω CM CM and DM add vectorially EMI (line) CM + DM EMI (neutral) CM - DM Fig. 6. DM and CM currents at the power supply s input. 1-5

6 V. MINIMIZING CONDUCTED DM NOISE The first line of defense against conducted noise is the use of filters, but often this is easier said than done. The practical aspects of effective filter design are reviewed in Figs. 7 and 8, which should be referred to in the following discussion. Some confusion could be created by the nomenclature used in Fig. 7. We will analyze the filter performance in terms of voltage attenuation between the V IN terminal, which is connected to 0 µh 0 µh the power source, and Vout which is the input to the power supply. In reality the filter provides current attenuation between current at the Vout terminal into the power supply, and the current at the filter s Vin terminal from the power source, as measured through a LISN 50-Ω source impedance. However, either a voltage or a current analysis will yield the same attenuation performance. 0 µh V IN V OUT V IN V OUT V IN V OUT 300 µf pf ESL 16 nh 500 pf 16 nh 16 nh 16 nh 16 nh ESR 0.0 Ω 0.08 Ω 0.08 Ω 0.08 Ω 0.08 Ω (a) Basic Ideal Filter µf µf µf µf µf (b) Actual Filter Circuit Including Parasitics (c) Paralleling Four Smaller Capacitors for Reduced ESL 5 pf V IN 0 µh V OUT V IN 0µH 1 µh V OUT 50 pf 16 nh 16 nh 16 nh 16 nh 50 pf 16 nh 16 nh 16 nh 16 nh 0.08 Ω 0.08 Ω 0.08 Ω 0.08 Ω 0.08 Ω 0.08 Ω 0.08 Ω 0.08 Ω µf µf µf µf µf µf µf µf (d) Reduced Inductor Capacitance, Single Layer Winding. Bypassed Core (e) Adding a Small Second Stage Inductor Fig. 7. DM noise minimized by a filter design that pays careful attention to component parasitics nh 500 pf 4 nh 500 pf 4 nh 50 pf 8 nh 5 pf Attenuation - db 0 db 40 db 60 db 80 db 0 µh 300 µf 0.0 Ω 300 µf (a) 0.08 Ω 1 µh (b) 0.0 Ω 16 µh (e) (c) 500 pf 0 µh (b) (c) (d) 5 pf 1 µh 8 nh 50 pf (e) 100 db 0.0 Ω 4 nh 50 pf 0 µh 10 db 100Hz 1 khz 10 khz 100 khz 1 MHz 10 MHz 100 MHz 1 GHz Frequency - Hz Fig. 8. DM filter frequency attenuation vs. circuit configuration. 1-6

7 The first point to remember is that if it is differential mode noise we are attempting to combat, the filter must connect across the differential lines. In other words, in Fig. 7(a) - which shows an ideal LC filter in the power line where V IN is the power source and V OUT is the power input connection to the power supply - the capacitor negative terminal must connect to the power return line - not ground! And the second point is that there is no such thing as an ideal filter that would yield the ideal attenuation curve shown in Fig. 8(a). The actual filter will include the effects of parasitic capacitance across the inductor, and parasitic ESL and ESR in series with the capacitor, as shown in Fig. 7(b). Using typical values for these parasitic components, the curve in Fig. 8(b) shows that now the filtering action is much less than ideal, and bottoms out with little more than 60 db of attenuation. Attacking first the capacitor, it can usually be shown that paralleling several smaller capacitors, instead of using one large one, may reduce the parasitic values and achieve some improvement such as shown in Figs. 7(c) and 8(c). Recognizing that greater attention to the inductor may also result in reduced parasitics, Fig. 9 indicates some of these considerations. Parasitic capacitance can be reduced if the design accommodates a single layer winding that achieves maximum spacing between the start and finish ends of the coil. However, capacity from winding to core must also be considered. Since the core is probably also a conductor, stray capacitance to the core can have the same effect of shunting the winding. By careful control of the winding process, the inductor s parasitic capacity can often be significantly reduced, yielding further improvement in filter performance as shown in Figs. 7(d) and 8(d). S Windings Bobbin Core Fig. 9. A single-layer winding reduces capacity but coupling to the core must still be considered. Often, a significant benefit, at minimal added cost is to add a small polishing inductance between some of the paralleled capacitors. This essentially makes the circuit a two-stage, or second-order, filter yielding a performance gain as shown in Figs. 5(e) and 6(e). Before leaving the design of this filter, its performance should also be examined from a resonance perspective. A simple L-C filter is resonant at its natural frequency: f r 1 π LC and this has the potential to introduce three additional problems: 1. A step application of input voltage could cause the capacitor voltage to ring to a value that could approach twice the input voltage, possibly damaging a following converter.. If there is a potential for high-frequency noise on the input power bus, any component of that noise at the filter s resonant frequency is amplified by the Q of the filter. 3. The effective output impedance of the filter, if undamped, rises at the resonant frequency, raising the specter of oscillations with the input impedance of a following converter. For any or all of these reasons, filter damping may be important. While there are many approaches to optimizing filter damping, a good starting point is to add a series R-C across the filter s capacitor as shown in Fig. 10. F 1-7

8 LINE SOURCE RETURN Undamped Filter L C Damping Components R D C D C L C POWER SUPPLY Fig. 10. A damping R-C network may be necessary to minimize problems caused by filter resonance. VI. MINIMIZING CM GROUND NOISE The above discussion has been with respect to optimizing a filter for DM noise, but the same considerations can apply to a filter intended to reduce CM conducted noise. As stated earlier, CM noise is largely created by parasitic capacitance to ground. A simplified example of one of the major problem sources and its potential solution begins with Fig. 11. In this example, we show a single-ended power stage with a switching FET alternating between driving a transformer primary and blocking its reset voltage of V IN. With a switching frequency of 00 khz, one might expect a FET drain voltage swing of 400 V with a rise and fall time of 100 nsec as shown in the figure. If, for example, the FET is in a TO-0 package mounted on a grounded heat sink with an insulating washer, the parasitic capacitance from drain to ground could be in the 1 3 pf range. Using the lower number, and solving for I C(dV/dt) results in a peak current of +/- 48 ma a not insignificant amount of injected ground noise. Fig. 1 illustrates how this injected current completes its path back to the power lines through the two 50-Ω LISN resistors in parallel, thereby creating a noise voltage at each LISN output. +00 VDC V 400 V 5 µs I 100 ns 0 ns +48 ma 1 pf 48 ma I RMS 9.6 ma (Typical TO-0 insulator capacitance is 1 pf, f s 00 khz) Fig. 11. A typical CM noise source is capacitive coupling of the switching FET s drain voltage waveform to a chassis-grounded heat sink. 1-8

9 PWR LISNs SMPS 1 pf V N RET 60 V RMS 600 khz 5 Ω V N V N 50 Ω 50 Ω 400 V 00 khz 1 pf 3rd harmonic eqivalent noise voltage circuit I CM Fig. 1. Current induced in chassis ground has a return path through the LISN output impedance. The solution for this problem is the insertion of a CM filter in series with the current path and its definition is most easily accomplished by using the equivalent voltage noise circuit also shown in Fig. 1. This equivalent circuit is generated by starting with the 400-V peak-topeak waveform at the FET s drain terminal. Assuming a 50% duty-cycle square wave, the rms value of this signal is 00 V at the switching frequency of 00 khz. Since 00 khz is below the FCC minimum specified frequency of 450 khz, we can ignore the fundamental and look to the third harmonic - 60 V RMS at 600 khz - as the most significant contributor to the noise spectrum. This signal yields a noise voltage across the paralleled LISN resistors of approximately 68 mv which, while seemingly a fairly small value, must be compared with the FCC noise limit of 1.0 mv for Class A products at 600 khz. (The limit for Class B is even lower at 50 µv.) To reduce 68 mv to less than 1.0 mv, we need to insert a filter that will produce an attenuation of 37 db at 600 khz. One way to accomplish this is with the addition of a series common mode inductor. Working backwards, we can calculate the required inductance from the reactive impedance we need at 600 khz as shown in Fig. 13. However, completing this analysis would show that, while the required inductance would be 419 mh, we cannot have more than 0.17 pf parasitic capacitance across the inductance. Not likely! V RMS 600 khz 1 pf (Xc.1 kω) Co < 0.17 pf! 419 mh (X L 1.58 MΩ) (N X 50T) 0.95 mv V N 5 Ω Fig. 13. Achieving 37 db attenuation with a series inductor requires an unrealisticly low parasitic capacitance. We will then try a shunt capacitor as shown in Fig. 14 to lower the impedance of the 5 Ω load to get under the 1.0 mv limit. The same calculations in this case yield a requirement for 760 nf, which could have a parasitic series inductance of 93 nh and still meet the attenuation requirement. While this at least looks viable, we run into another problem in that if the input to this power supply is ac line voltage, there are usually safety specifications that limit input line capacitors to less than 10 nf. 60 V RMS 600 khz 1 pf (X C.1 kω) 760 nf (X C 0.35 Ω) ESL < 93 nh 5 Ω 0.95 mv V N Fig. 14. Achieving 37 db attenuation with a shunt capacitor requires an unacceptably large value.

10 So we finally come to the best solution for a CM input filter, which includes both inductance and shunt capacitance, but with reasonable values for each, even considering expected parasitic values. This solution is shown in Fig. 15 and is typically implemented with two windings on a single core wound in opposition such that the flux caused by the power supply s dc input current will cancel and not contribute to core saturation. Of course, in this application the shunt capacitors are connected to ground instead of differentially. 60 V RMS 600 khz 153 mv 1 pf 4.7 nf (X C 56 Ω) Co < 66 pf 1.07 mh (X L 4.03 kω) (N X13T) 0.95 mv V N 5 Ω Fig. 15. Using both a shunt capacitor and a series inductor achieves a solution with practical values for both. A CM input filter may also have to be damped to prevent problems at resonance, but since the maximum capacitance is limited, the usual approach is to divide the required capacitance into two capacitors, and then place an appropriately sized resistor in series with one of them. Diff. Mode Fig. 16 shows a possible input filter configuration combining both DM and CM filters. In this figure, the input load power is shown as flowing from left to right, from the ac line to the input rectifiers of the power supply. The noise signal, however, is flowing from right to left, from internal sources within the supply back toward the ac line terminals, which are the external input power connections. Working from right to left, C d1 and L d1 represent the main DM filter. C c1 and L c1 ( of each) form the CM filter for ground noise, with the two windings of L c1 built onto a single core. C d works with the leakage inductance between these windings to form a second, higherfrequency DM filter element. Ln and Cn form a notch filter at the switching frequency with Rn providing both damping and some spreading of the notch width. Finally, C d3 and C c () are often used for a last cleanup, right at the terminals where a pair of LISN devices would be connected to evaluate noise performance. These last capacitive elements work against the undefined ac line impedance so their performance, while helpful, is difficult to predict. Additional components, not shown in this figure, could be damping networks, transient protectors, fuses, and other application-dependent devices. Inrush Limiter AC Line C c Cd3 L LN c1 C d C c1 C N C c Discharge R N L c1 C c1 L d1 C d1 DC Bus Final Cleanup With Line Impedance Common Mode Notch Filter for F S Differential Mode Fig. 16. Multiple filter components are combined in this example of conductive noise reduction circuitry. 1-10

11 VII. ADDITIONAL CM NOISE SOURCES Before leaving the subject of CM conducted noise, we should mention that the drain terminals of the power switches are certainly not the only place where high dv/dt signals might introduce ground noise. Heat sinks are another potential problem area, as safety requirements typically do not allow them to be charged to a high voltage potential. If the heat sink is small enough that it can be enclosed within the power supply s case, then connecting it electrically to the circuit common rather than chassis ground may be an acceptable solution. Using an insulated intervening bracket connected electrically to circuit common may allow the accommodation of larger, grounded heat sinks by shunting capacitively coupled noise to the common rail where it can more easily be attenuated. These options are shown in Fig. 17. The same approach for diverting what might become CM noise away from ground is applicable to transformers by the use of electrostatic shields between the windings, as shown in Fig. 18. In many power supply designs, the secondary-side output circuitry is ground referenced, and it therefore follows that any high voltage ac potential on the primary side, which is coupled through the transformer by parasitic CORE capacitance, can become CM noise. Properly applied, electrostatic shields can prevent this by diverting the coupled noise into the primary common bus. (As an additional hint, the shield could do its job connected to either the high voltage rail or the return. As a rule of thumb, if the power FET dv/dt is greater at turnon than at turnoff, connect the shield to the return, but if turnoff is faster, then connect it to the positive rail.) Alternative shield configurations are shown in Figs. 19 and 0. PCB Mounted Heat Sink Use of Primary Shield ALTERNATE SHIELD CONNECTION Internal Heat Sink Tied to PCB Ground (return) PCB Insulators Case at HF AC Bracket Contacting PCB Ground Chassis Grounded Heat Sink Shielding Heat Sink Bracket Fig. 17. Two heat sink arrangements that divert capacitively coupled noise to circuit common rather than chassis ground. V Unshielded Transformer Correct Fig. 18. Using an electrostatic shield in a transformer can minimize CM noise. Incorrect! 1-11

12 Shielding primary and secondary windings. Fig. 19. Alternative shield configurations. Adding a third shield for safety. PRI Core SEC Basic arrangement of PRI and SEC shields. PRI Core SEC Shielding a floating or safety grounded core from a HV primary. Fig. 0. Positioning shields for maximum effectiveness. VIII. RADIATED EMI As we leave the subject of conductive EMI and move on to radiated interference, we should first emphisize that while we treat each type of noise separately, they are not unrelated. In an electronic system, particularly a switchmode power supply, EMI energy can be transformed back and forth between conducted and radiated forms - perhaps even several times - between its generation and its measurement. If the noise energy is conducted in a wire or PCB trace, an electromagnetic field is created which gives us radiated EMI. If there is then mutual inductance or capacitive coupling to another conductor, then the radiated energy is transformed back to conducted noise, but now in a different location in the system. The point is that any conductor can become an antenna, and an antenna can both send and receive radiated signals. Testing for radiated electromagnetic compatibility is a much more complex process than for conducted noise. In the first place, because - by specification - we are looking for signals above 30 MHz, all the test instrumentation becomes more crucial. Second, the test environment must be well-controlled, which typically means using either an RF screen room to shield the test setup from any extraneous RF signals from other generators or reflections, or open-air testing in a well-defined environment. In either case, a knowledgeable operator is vital in order to obtain reliable data. The type of antenna and its distance and orientation with respect to the device under test, as well as a method to sweep all radiating angles, are all important parts of the test conditions. A schematic representation of a radiation EMI test setup is shown in Fig. 1. Power Source Test fixture on rotating turntable Antenna on variable height vertical support Antenna SMPS Spectrum Analyzer Fig. 1. Measuring radiated noise with an antenna. "Load" 1-1

13 One potential escape from this problem is a clause in the FCC requirements which states that the frequency range of EMI testing is based on the highest fundamental internally generated clock frequency, and if that frequency is less than MHz, then the maximum test frequency is 30 MHz. While this might preclude the need for radiation testing on most stand-alone power supplies, it is unlikely to be of much benefit when the power supply is combined with its load and the entire system must be evaluated for EMI. Note that in performing system-level radiation EMI tests, the input and output connections to the power supply need to be included, and it is here where high frequency conducted EMI energy might generate an RF field and contribute to the total radiated noise. For this reason, ac line cords often include a ferrite snubber and, if the actual system load is not included, the power supply should be loaded with passive resistors rather than an electronic load unless the effects of dynamic loading are an objective of the testing program. IX. COMBATING RADIATED EMI The contributors to radiated EMI can also be subdivided into two categories depending upon how the energy is generated. This energy can be from an electric field, which is generated by dv/dt on conductive surfaces, or from a magnetic field which is generated by di/dt in conductors. The nature of these fields change as the distance from the source to the point of measurement increases. At distances close to the source, the fields are determined by their cause and both electric and magnetic fields must be considered separately. This region is called the near-field. Beyond this region (in the far-field) the two fields meld together into a single electromagnetic radiation. The boundary between near-field and far-field distinctions is defined by the wavelength of the noise energy, as λ/π. When you consider that the wavelength of a 1 MHz signal is 300 meters, it is usually safe to assume that most power supply concerns can be limited to nearfield phenomena. Within the near-field region, an additional assumption which is usually valid is that if the source has high voltage and low current, the resultant field will primarily be electric, while with a high current, low voltage source, a magnetic field will predominate. An electric field is produced when switched voltages are present on surfaces such as heat sinks or magnetic cores, causing them to act as antennas. Typical locations within a power supply where this might occur are shown in Fig.. Electric fields can usually be shielded relatively easily by conductive enclosures, where the conductive material terminates the field by converting it to current. Of course, there must be a path for this current but, with the enclosure normally grounded, this current merely contributes to overall CM conducted noise energy where it can be addressed with filters as previously described. E E E LARGE AREA HIGH dv/dt ANTENNAS Fig.. Electric fields are generated by surfaces with high dv/dt acting as antennas. Magnetic field EMI energy can emanate from a power supply as either stray fields from transformers or inductors, or as magnetic fields which are created when there is a rapidly changing current flowing in a conductive loop. It is here where internal wiring layout becomes very critical as the magnetic field from a current loop is a function of the inductance that is determined by the area enclosed by the loop. Fig. 3 shows just one example where the highcurrent secondary leads from a power transformer connect to the output rectifiers. While this is a flagrant illustration of good and bad practices of handling conductors with high di/dt, these basic principles should be observed throughout the power supply. 1-13

14 Rectifier Rectifier Transformer Transformer Large Loop Area With High di/dt Wide, Closely Spaced Copper Straps Worst case! Much Better! Fig. 3. Conductors with large loops and high di/dt make excellent antennas! High di/dt Switching Loops I I H H Stray Transformer and Inductor Fields Fig. 4. Magnetic fields must be minimized by design as shielding can be difficult. Additional power supply contributors to magnetic fields are shown in Fig. 4. Magnetic fields are not as easily shielded - it takes a magnetic material to block a magnetic field and while magnetic material in sheet form exists, it is (1), very expensive when used for this purpose, and (), its magnetic properties fade very rapidly at the higher frequencies of EMI. However, shields of non-magnetic, conductive material can be used for magnetic fields, but the process is that the magnetic noise induces eddy currents to flow in the enclosure, which in turn generate a canceling magnetic field. The catch here is that there can be no interruption of these eddy currents - any gaps, joints, or holes in the shielding will allow a surprising amount of the magnetic field to escape, or leak, from the enclosure. Thus it is far better to combat the problem at its source by minimizing current loops and containing magnetic fields. In designing transformers for switchmode usage, it is well known that leakage inductance between primary and secondary windings can be detrimental to electrical performance, but it can also contribute significantly to radiated magnetic fields. Fig. 5 shows a two-winding transformer wound on what might be an EE or EI core structure. The leakage inductance generates a transverse magnetic field between the windings and, while some of this field may be captured by the core, the rest acts as a magnetic dipole radiating out into surrounding space with an intensity which decays as the cube of the distance. A change in the winding procedure to interleave the primary as shown in Fig. 6 now produces two leakage fields with opposite polarities. This provides for a significant amount of cancellation and the resultant quadrapole field falls off with the fourth power of the distance, and thereby greatly attenuates the radiant energy. 1-14

15 SEC PRI Core PRI SEC P SEC P Core P SEC P Fig. 5. The transformer leakage inductance field for a single primary and secondary is a dipole field. Another technique for reducing stray magnetic fields from a transformer is the use of a conductive flux strap (also sometimes called a belly band, flux band, or hum strap ). This copper band, illustrated in Fig. 7, provides a path for the eddy currents that result from the leakage inductance magnetic dipole. The current flowing in the flux strap then creates an opposing magnetic dipole which tends to cancel the original field at close proximity to the transformer. Fig. 6. Sandwiched windings create opposite leakage field dipoles that tend to cancel. Inductors are also potential generators of stray magnetic fields. Fig. 8 illustrates a poor inductor design with significant stray field caused by the gaps in the core which are outside the coil winding. Changing the core design so that all the gap is in the center leg, and now fully contained within the winding, reduces this source of radiated EMI. Fig. 9 shows some additional inductor designs that can create problems with stray fields. Core Coil Fig. 7. A continuous flux strap around the transformer further reduces magnetic fields. Fig. 8. Stray magnetic fields are caused when air gaps are not enclosed by the inductor winding. 1-15

16 Winding Core Magnetic fringe field around partial toroidal winding on a distributed gap core. Fig. 9. Other inductor designs with strong leakage fields. Drum and rod core fields, good antenna design; poor for EMI. X. FINAL THOUGHTS This Topic has attempted to cover the high points of EMI prevention by the use of design techniques applied within the power supply. We have described the differences between conducted and radiated noise, emphasizing that while the solution to conducted noise lies with effective filter design, radiated noise prevention is largely influenced by construction techniques. One issue not discussed is the other side of the coin - susceptibility to noise from external sources; but it turns out that in most cases, the best defense is a good offense. In other words, the action taken to reduce the generation of noise often also contributes to reduced susceptibility. Finally, there is another noise reducing technique which some have applied to switchmode power supplies. Since EMI specifications are written to evaluate noise at specific frequencies, by using some form of random modulation of the supply s switching frequency, the noise generated by the power supply is smeared or spread out instead of falling at specific harmonics of a constant fundamental. [Ref. 8] Since this can greatly reduce the average energy content at any specific frequency, compliance with FCC specifications is certainly eased, but this technique is controversial over whether it is just exploiting a loophole in the standards or truly benefiting the system s EMC. XI. ACKNOWLEDGMENT Much of the material incorporated in this presentation was derived from work by Bruce Carsten, who conducts full one-day seminars on this subject at both public conferences and through private in-house presentations. For further information, contact: Bruce Carsten Associates, Inc N.W. Sisters Place Corvallis, OR Phone: FAX: carsten@peak.org 1-16

17 XII. REFERENCES [1] Mark Montrose, Printed Circuit Board Design for EMC Compliance, Second Edition, IEEE Press, Piscataway, NJ, 000. [] Henry Ott, Noise Reduction Techniques in Electronic Systems, Second Edition, John Wiley & Sons, New York, [3] Bruce Carsten, Design Techniques for the Inherent Reduction of Power Converter EMI, Powercon 11 Proceedings, Dallas, TX, [4] Bruce Carsten, Design Tricks, Techniques, and Tribulations at High Conversion Frequencies, Second HFPC Conference Proceedings, Washington DC, [5] Bruce Carsten, H-Field Probes Spot Switchmode Supply EMI, PCIM Magazine, September 001, pp [7] Peter Bardos, Predicting the EMC Performance of High Frequency Inverters, IEEE APEC 01 Conference Proceedings, Anaheim, CA, pp [8] D.A. Stone, B. Chambers, & D. Howe, Easing EMC Problems in Switched Mode Power Converters by Random Modulation of the PWM Carrier Frequency, IEEE APEC 96 Conference Proceedings, San Jose, CA pp [9] T. Guo, D. Chen, & F. Lee, Separation of the Common-Mode and the Differential- Mode Conducted EMI Noise, HFPC 1994 Conference Proceedings, San Jose, CA, pp [10] Richard Farrington, EMI Characteristics, SynQor Application Note , SynQor Power Supplies, Hudson, MA, January, 001. [6] David Williams, A Tutorial on EMI Characterization of Switching Regulators, IEEE APEC 96 Conference Proceedings, San Jose, CA, pp

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19 Designing High-Power Factor Off-Line Power Supplies James P. Noon ABSTRACT The purpose of this paper is to provide a tutorial on power factor correction topologies and control techniques. The first part of the paper concentrates on identifying the trade-offs between various operating modes. A framework is developed to compare losses and device stresses in the CCM and CRM boost topologies. The second part provides an overview of the main design choices as well as design equations. The power stage and control circuitry design equations are explained and presented. INTRODUCTION The use of power factor correction (PFC) circuits has been widely discussed and is generally considered a market requirement for most off-line power supplies. [1,, 3] There are many reasons for this. There is a well know European requirement which is documented in IEC This specification sets limits on harmonic current for any power supply sold in the European Union (EU). While this specification is only in force in the EU, for power supply manufacturers wanting to sell into the global market, it makes sense for all their supplies to be compliant. Tables 1, and 3 show the IEC harmonic limits for various classifications of equipment. Class C is lighting equipment, Class D is personal computers and television receivers and Class A is basically everything else. There are other reasons for wanting to limit harmonic currents, these include being able to use the full rated current from the available power source. For example, if you have a typical 15-A service (single phase 10 V) and your rectifier is 98% efficient with 55% power factor (PF) the maximum load you could power is 970 W. This assumes using 100% of the rated breaker current, which is unlikely. If the PF is improved to 99% the load increases to 1746 W, an increase of almost 80%. This increase in power can be reason enough to employ PFC circuits. TABLE 1. LIMITS FOR CLASS A EQUIPMENT Harmonic Order, n Odd harmonics n 39 Even harmonics n 40 Maximum permissible harmonic current, A , 15/n , 8/n TABLE. LIMITS FOR CLASS C EQUIPMENT Harmonic Order, n n 39 (odd harmonics only) Maximum permissible harmonic current expressed as a percentage of the input current at the fundamental frequency, % 30 X power factor , 15/n -1

20 Harmonic order n n 39 (odd harmonics only) TABLE 3. LIMITS FOR CLASS D EQUIPMENT Maximum permissible harmonic current per watt, ma/w /n Maximum permissible harmonic current, A see table 1 A typical switching power supply presents a nonlinear load to the power source. The rectifier, capacitor circuit and the resulting current drawn from the line, are shown in Fig. 1. The high peak current drawn form the line is due to the small conduction angle. AC Line Line Voltage I L Line Current Fig. 1. Simplified rectifier circuit with line voltage and resulting current. Load Historically, the definition of power factor (PF) is the cosine of the angle between the voltage and current. PF cos( θ φ) (1) Where (θ-φ) is the difference in the respective phase angles. This however, is only valid for sinusoidal voltage and current waveforms, i.e. a linear source and load. A more relevant figure of merit for nonlinear systems is to look at the harmonic content of the waveforms. From Table 1 we can see that the EU specification is indeed given in terms of harmonic current. Power factor is not specified. All of our circuits though are referred to as power factor correction circuits. This is a legacy from the power system and generation part of the industry. Power factor and Total Harmonic Distortion are related mathematically though. Additionally, it s useful to keep the phase angle definition in mind. Recall that power is only delivered from components of the current and voltage waveforms that are in phase with each other. If the voltage waveform is a pure sinusoid, then it only has a component at its fundamental frequency. The current waveform, if distorted, will have components at multiple frequencies. These components do not contribute to the power delivered; they do however contribute to the RMS value of the current waveform. This increase in RMS current is primarily what we are concerned about. -

21 Total Harmonic Distortion (THD) is the ratio of harmonic current to the fundamental component. Assuming there is no dc offset, the THD is defined as: I n THD n 1 () I1 Power factor and THD are related by the following equation: 1 PF (3) 1+ THD The goal then of a PFC circuit is to reduce the harmonic content of the current waveform and keep the phase angle between the current and voltage as small as possible. In effect the circuit wants to emulate a resistive load. This paper is organized into two parts. The first part discusses the different topologies used for PFC circuits. The main focus of Part 1 is the losses in the power stage and specifically the semiconductor components. This should help the designer understand the trade0offs with the different topologies. Part provides design equations and discuss the main design considerations with the boost PFC circuit. PART I. TOPOLOGY COMPARISON A. PFC Techniques There are two classifications of PFC circuits, active and passive. Passive techniques rely on a combination of inductors and capacitors to smooth out the current waveform. The passive approach is usually less expensive than an active approach, but it is hard to optimize for universal line operation and suffers from a large, heavy inductor required to meet the THD requirements. The passive approach is usually a low power, fixed line voltage option. Active PFC circuits can be derived from all of the basic topologies. [1] There are also topologies that have been developed specifically as PFC circuits. [4, 5, 6] By far though the most popular topology used in PFC applications is the boost converter. This is for obvious reasons. The line voltage varies from zero to some peak value typically in the range of 180 V to 380 V. A buck topology would have a hard time with this input range. The Buck-boost converter has high switch voltage stress and discontinuous conduction mode (DCM) operation (which can provide good PFC in normal operation) has large current stress for the same power level. The boost converter also has a smooth input current waveform as opposed to the pulsating profile of a buck derived topology, so filtering is much easier. This is not a trivial point since any filtering that is needed on the input side of the converter adds cost and can potentially degrade the PF you are trying to correct. [7] The boost converter can operate in two modes, continuous conduction mode (CCM) and DCM. Fig. shows example inductor current profiles for the different operating modes. DCM operation has the disadvantage of much higher peak currents than CCM for the same power level. A third option called transition mode or critical conduction mode (CRM) is really just a variation of CCM. The power stage equations and transfer functions are the same as CCM. The difference is a control function, which when implemented forces the inductor current to operate just at the border of CCM and DCM. Since the line voltage is constantly changing in a PFC circuit, the operating frequency will change as well. This is due to the fact that as the line voltage varies, the time needed for the inductor current to decay back to zero will vary accordingly. -3

22 The control techniques required to implement the designs will be discussed in a later section. The question arises though, which operating mode is better. The answer in most cases is, it depends. I L I L I L (a) CCM operation (b) CRM operation (c) CCM operation Fig.. Three inductor current operating modes. (a) CCM (b) DCM I AVERAGE I PEAK I PEAK I AVERAGE I AVERAGE t t t B. Boost topology comparison The main differences between the CCM and CRM topologies relate to the amplitude of the current and the ripple profile. The current profile effects two items, power losses in the power stage components and filtering requirements. The peak current in the CRM boost is twice the amplitude in CCM operation. This leads to higher conduction losses. The peak-to-peak ripple is also twice the average current. This effects switching losses in the MOSFET as well as ac losses in the magnetics. On the other hand, the boost diode losses are much higher in CCM operation. This is due to the big reverse recovery problem. Qualitatively you can say that for low to medium power applications the CRM boost has an advantage in losses, while the filtering requirement is not so severe as to be a big disadvantage. The CCM boost is a better choice for medium to high power applications. The peak currents are significantly lower which reduces conduction losses while the lower ripple current reduces filter requirements. To better quantify this we need to take a look at the losses in the main components, which are different in the two modes of operation. For example, the gate charge, and diode turn-on losses are essentially the same in both modes of operation, so these won t be considered. CCM Losses First we will consider the losses in the CCM boost converter. In order to do this we should first define the currents in the converter (see Fig. and 3). The input current waveform follows the line voltage. If we allow the ripple in the inductor to be 0% of the peak line current, which is a typical value, then the peak inductor current (IL_pk_ccm) is given by equation (4). Pin Pin IL _ pk _ ccm (4) VAC VAC The valley of inductor current (at the crest of the line) is shown in equation (5). Pin Pin IL_valley_ccm 0.1 (5) VAC VAC (C) DRM Fig. 3. PFC inductor current profiles. -4

23 The peak and valley of inductor current vary with the line voltage. Fig. 4 shows a simplified schematic of the boost converter and an expanded view of the relevant current waveforms. I D O d if /dt t A t rr t b Reverse Recovery Current I rr i D (t) t I O L I L I D V OUT I Q C I DS t Q1 V DS t (a) CCM (b) CRM IL_pk_crm Switch Current Diode Current IL_pk_ccm IL_valley_ccm Switch Current Diode Current t Fig. 4. Simplified boost schematic with switch and diode current waveforms. The RMS switch current in the CCM boost is given by equation (6). [8] Pin 8 VAC Iq _ rms _ ccm 1 (6) VAC 3 π Vout The diode turns on at the peak of inductor current as the switch turns off. The inductor current is at the valley though when the switch turns on. The conduction loss is given by equation (7). Pq _ rms _ ccm Iq _ rms _ ccm Rdson (7) Switching loss can be broken down into the loss associated with turning the MOSFET OFF and ON, i.e. the overlap in drain voltage and current as well as the Coss loss and the reverse recovery loss of the boost diode. t Fig. 5. Illustrates the MOSFET and diode current and voltage. The energy losses associated with the MOSFET turn-on and turn-off are given in equation (8) and (9). These equations describe the energy lost in a switching cycle. They need to be averaged over the line cycle and then multiplied by the switching frequency to find the total loss, (10). Similarly the turn-on losses are summed over the line period. To get the power loss you multiply by the switching frequency, (10) and (11). The MOSFET also experiences loss due to the reverse recovery current of the diode. This loss is very dependant on 3 terms, the di/dt of the current through the diode at turn-off, the forward current of the diode (I F ), and the reverse voltage. The effect these parameters have on the diode varies with the diode type and manufacturer. The reverse voltage is fixed and equal to Vout. The currents through the diode vary as a function of line and load. To make things even more difficult, most manufacturers give limited data to calculate the recovery characteristic. So, the calculation of this loss term is an approximation. The MOSFET energy loss due to reverse recovery is given in (13). [9] -5

24 ( IL _ valley_ ccm sin(wt) ) transistor _ rise Eq _ ccm _ turnon Vout (8) ( IL _ pk _ ccm sin(wt) ) transistor _ fall Eq _ ccm _ turnoff Vout (9) n Eq _ ccm _ turnon i 1 Eq _ ccm _ turnoff _ tot i (10) n Pq _ ccm _ turnoff _ tot Eq _ ccm _ turnoff _ tot Fs (11) Pq _ ccm _ turnon _ tot Eq _ ccm _ turnon _ tot Fs (1) Irrm_ pfc sin(wt) Irrm_ pfc sin(wt) Irrm_ pfc sin(wt) Irrm_ pfc sin(wt) Err Vout + trr (13) didf 4 didf Irrm _ pfc sin(wt) Irrm_ pfc sin(wt) Err _ diode Vout trr 4 didf (14) π 00 IL _ pk _ ccm sin(i ) VFF (1 D i) 00 Pdiode _ ccm 01 i 1 (15) π 00 IL _ pk _ ccm sin(i ) VFF 00 Pdiodebrid ge _ ccm 01 i 1 (16) Where Irrm_pfc is the peak reverse recovery current taken from the manufacturers data sheet, and didf is the di/dt through the diode at turn-off. The sin (ωt) term is needed because the diode current, and therefore the reverse recovery current will vary with the line voltage. Equation (13) also must be averaged over the line cycle and then multiplied by the switching frequency to find the total power. The diode also experiences power loss during the turn-off period. This occurs during the t b period (see Fig. 5). The loss during this time is shown in equation (14). Diode conduction loss is simply the current in the diode multiplied by its average voltage, see equation (15). Lastly, the input bridge rectifiers experience loss as shown in equation (16). CRM Losses Now lets look at the losses associated with the CRM boost. Here the switching losses in the boost diode are essentially eliminated. This of course, is the principal advantage of this approach. On the other hand the conduction losses will increase. The peak inductor current in the CRM boost is: Pin IL _ pk _ crm (17) VAC Again, we can see that it is approximately twice the peak of CCM operation. The rms current through the MOSFET is shown in equation (18). [10] Iq _ rms _ crm Pin VAC 1 4 VAC 6 9 π Vout (18) -6

25 The turn-off loss due to current and voltage overlap follow the same equation as the CCM case, except that the current is higher (i.e. IL_pk_crm). The turn-on loss due to commutating the inductor current into the MOSFET is zero since the current is at zero when the MOSFET turns ON. The conduction loss also is simply I rms x R DS,on with the RMS current given above. The boost diode experiences conduction loss with the higher peak current (IL_pk_crm) as do the bridge diodes. These equations, for both the CCM and CRM cases are included in the Appendix, where a MathCad version is given. In the Appendix, the equations are modified to calculate the losses for a range of input power. Again, there are more losses in the power stage, which were not discussed here. These include the Coss loss in the MOSFET as well as gate charge loss. These losses will be the same for CCM operation as well as CRM operation so we are not considering them in the trade-off between the two modes of operation. For an excellent discussion of MOSFET switching behavior see reference. [11] We ve quantified the losses in the semiconductors that are different in the different operating modes. One area that has not been calculated is the magnetic losses. A detailed analysis of the magnetics is beyond the scope of this paper, and would be very dependant on filter requirements/specifications, magnetic materials used, etc. Some general comments can be made though to help compare specific cases. First, the inductor design will be driven by the amount of loss tolerable and size constraints. In magnetic components you can trade-off core size for loss. At some point though the core size becomes too large for the application. In comparing CRM to CCM operation, the small inductance will be traded-off to higher ripple current. On the other hand, core loss is a strong function of ac flux. Clearly, the CRM case will have much higher ac flux due to the large amount of ripple current. Loss Summary Above a couple of hundred watts, the input filter requirements for the CRM case will dominate the size of the magnetics. At much higher power levels, there is interesting work being done to interleave CRM converters. [1] This effectively reduces the ripple current and makes the filter more manageable at the expense of a more complicated control scheme. The above discussion and equations are intended to provide a framework for comparing the two methods in a particular application. Each individual application will have its own unique design objectives. The equations given in the text, and expanded in the Appendix, can be easily modified for a particular application or device choice. This hopefully will aid in making the trade-off for an individual application. Typically cost and size are key aspects of the requirements. Efficiency is usually important in that it effects the required heat sink/thermal design. The equations described above were used to plot the losses of a CCM and CRM converter. The input power was swept to see where the crossover point was. The analysis was performed using identical semiconductors. For this analysis the MOSFET used was an IRF840 while the diode was an 8ETH06 diode from International Rectifier. The device parameters were taken directly from the data sheet and can be found in the Appendix. In this case, the semiconductor losses cross each other around 300 W. If magnetic losses are accounted for this point will occur slightly below 300 W. In a boost converter one of the most difficult components to deal with is the diode. In low to medium power applications, the CRM mode can eliminate the diode issues with relatively little negative impact to the rest of the system. As the power increases, the higher currents start to tip the trade-off towards CCM operation. In CCM operation, passive snubbers and active techniques are often employed to reduce the effects of the reverse recovery current. -7

26 One interesting development to watch is the introduction of silicon carbide (SiC) devices. [16] These devices can significantly reduce the reverse recovery losses. They have a characteristic which looks capacitive. The tradeoff is they have a slightly higher forward voltage drop (VFF) than a traditional Si diode. Depending on the diode and operating point, about 0.5 V higher. PART II. BOOST CONVERTER DESIGN POWER STAGE CONSIDERATIONS We have looked at the topology trade-offs. Let s now take a look at the design issues and criteria associated with each operating mode. In terms of power stage design, the main elements are the boost inductor, the power switch, the boost diode and the output capacitor. The inductor design equations are based on the ripple current specification. The selection of switches depends on the peak and RMS current through them. Because of the relatively low switching frequency of the PFC front-ends (typically in the 100 khz or lower range), it is possible to use IGBTs with some benefits in conduction losses at high power levels. Both the power switch and the boost diode have to be rated at or above 500 V (about 0% above the boost output voltage). The boost diode should have ultrafast reverse recovery characteristics (for CCM operation). The output capacitor is generally the most expensive component in the PFC front-end. In many cases, hold-up time requirements dictate the value of this capacitor. However, the ripple current in this capacitor can be minimized by using leading edge modulation for the PFC stage while the second stage is using trailing edge modulation. [,13] A. Inductor Design CCM Typically the CCM inductor is designed with the ripple current ( i) equaling 0% of the peak current. The main point is that the ripple current is small compared to the 60-Hz component. To calculate the inductance: VAC, min D Ts L CCM (19) i Where VAC, min, is the minimum line voltage, Ts is the switching period, and D is the duty cycle at the peak of low line (remember D is constantly changing throughout the line cycle). Pin i 0. (0) VAC Vout VAC D (1) Vout CRM The inductor calculation for CRM mode is different because you are designing the inductor to start the next switching cycle at zero current. The time it takes to reach zero is dependant on the line voltage and inductance. So, the inductance will determine the frequency range the converter operates over. This is typically a key parameter. To find the inductor value we first need to find equations for the on and off times. We do this by recognizing that the peak inductor current (IL_pk_crm) is also i. Pin IL _ pk _ crm () VAC Also, using VL di/dt and solving for di at the peak of the line we get: t VAC i on (3) L -8

27 Setting these two equations equal to each other and solving for t on yields: Pin L ton (4) VAC Similarly for t off, we use the same general equations, but for t off recognize that the voltage across the inductor is Vout - Vin. t ( Vout VAC) i off (5) L Again equating the IL_pk_crm equation with the i equation and solving for t off yields: Pin L t off (6) VAC ( Vout VAC sin( ωt) ) Summing t on and t off we can find the period and therefore the frequency. After some algebra Fs is given by equation (7). ( Vout VAC sin( ωt) ) Pin Fs (7) L Vout Here we can see that even for a given rms line voltage and load, the switching frequency will vary as the instantaneus line voltage varies. It also gives a useful design equation. Since we usually will want to fix a minimum line frequency we can solve the above equation, for the inductance that satisfies that goal. The minimum frequency will occur at the peak of the line, at this point sin(ωt) will equal 1. ( Vout VAC) VAC L (8) Fsmin Vout * Pin That completes the inductance calculation for both operating modes. The design of the inductor itself is driven in both cases by the current waveforms. Reference [14] is an excellent reference for the inductor design. C. Switch Selection The main switch selection in CCM and CRM operation is driven by the amount of power dissipation allowable. The equations for calculating the RMS currents, conduction and switching loss were given above. The maximum voltage rating is the same in both cases. Choosing a device which minimizes gate charge and device capacitance is often desirable. The key is to choose a device which minimizes the sum of switching and conduction losses at a given frequency. The diode selection is based on reverse voltage, forward current, and switching speed. Again, CRM operation significantly simplifies the diode operation. A slower and therefore less costly diode can be chosen for CRM. In CCM the diode selection is critical. As discussed above, a diode with a fast recovery characteristic is important. The equations given in Part I can be used to evaluate the energy loss associated with a given diode. SiC diodes show promise but time will tell if they become commercially viable. D. Output Capacitor In addition to the capacitance value and voltage rating, the output capacitor rating is influenced by the systems hold up requirements, the maximum RMS current rating, and to a lesser extent the ESR of the capacitor. Previous papers have outlined the hold-up requirements for the output capacitor. [1,] In most cases the hold-up time is the main driver in determining the output capacitance. In CRM, at higher power levels the ESR and ripple current rating of the output capacitor operation may also have an impact. Capacitance required for a given hold-up time is given by: Pout thold up Co (9) Vout Voutmin -9

28 For the CCM case, the RMS current in the output capacitor is typically given by equation (30). Vout 16 Vout Ic _ RMS 1 Rload 3 π Vin pk (30) However, it has been shown that the proper synchronization with the nd stage dc-to-dc converter can result in a significant reduction in RSM current. [13] Fig. 6 helps illustrate the timing of the switching action between the PFC circuit and the down stream dc-to-dc converter. A simplified power stage is shown to highlight the switches. The capacitor current during a switching cycle depends on the status of the switches Q1 and Q. The relevant waveforms are shown in Fig. 6. Clearly, when the switches are synchronized to both (Q1 and Q), turn on at the same time, i.e. synchronized trailing edge modulation, the capacitor current experiences its highest ripple current. This is because while Q1 is ON, all the current available from the line being shunted to ground while the dc-to-dc converter is pulling its current out of the output capacitor. To maximize ripple current cancellation, the off time of Q1 should be synchronized with the on time of Q. A straightforward way of achieving this is to implement leading edge modulation of the PFC and training edge modulation of the dc-to-dc stage. Table 4 compares the measured RMS capacitor current for leading edge/trailing edge modulation (LEM/TEM) verses traditional trailing edge/trailing edge modulation (TEM/TEM). [15] The data shown was taken on a 00 W application. The two rows correspond to different operating points for the second stage converter, i.e. with two different duty cycles. Table 4 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about 30% at high line. Circuits to synchronize two discrete controllers can be found in reference. [15] Alternately, control ICs which combine the two controllers in one IC and provide the necessary synchronization internally are also available. The UCC38500 and UCC3851x family are good examples. In the CRM case, the capacitor current is a little more complex. Since the frequency is varying throughout the line cycle, the overlap of diode current and downstream converter current is very difficult to predict. The rms calculation for the CCM case is also a good approximation since the rms value is relatively insensitive to the higher turn-off slope. [17] If a more exact answer is desired, simulation or measurement is the best approach. Fig. 6a. Simplified representation of two-stage power supply. Q1 is the boost switch while Q is the buck derived converters switch. Fig. 6b. Current and voltage waveforms for trailing edge/trailing edge modulation/synchronization (left) vs. leading edge/trailing edge modulation/synchronization (right). -10

29 TABLE 4 EFFECTS OF SYNCHRONIZATION ON BOOST CONVERTER CURRENT Second stage duty cycle Traditional TEM/TEM V IN 85 V LEM/TEM Traditional TEM/TEM V IN 40 V LEM/TEM A A 1.04 A A A 0.93 A A A CONTROL CIRCUIT CONSIDERATIONS We have taken a look at the power stage in considerable detail. This is appropriate since the power stage design is what determines the efficiency and reliability of the converter. The power stage design also influences the overall performance of the system. However, the design is not complete, nor can the converter operate properly without proper design of the control loops. The control of the PFC circuit is usually broken down into two areas, the reference circuit for the current loop, and the control loops themselves. The reference circuit for the current loop is the multiplier. The two techniques we are considering have slightly different algorithms to control the inductor current. In both cases the boost inductor is in the input side of the converter. Since inductor current is one of the state variables of the converter, this allows us to have a control loop directly control the input current. The CCM case typically uses average current mode control (ACMC). While it is possible to control a CCM converter using peak current mode or charge control, ACMC has the advantage of directly controlling the average input current, which is the quantity we want to control in a PFC circuit. ACMC typically gives the best line current performance of the different techniques. A basic block diagram is found in Fig. 7a. LPF X V AC R IAC I AC X MULT X I MO R i R SENSE R f + C P C Z PWM + D Gate Driver Logic Fig. 7a. Basic block diagram of ACMC boost PFC. L The CRM converter typically uses a variation of hysteretic control with the lower boundary equal to zero current. The switch current is compared to the reference signal (multiplier output) directly. This control method has the advantage of being simple to implement. While not as high performance as the ACMC method, it provides very good PFC and is quite appropriate for power levels less than a few hundred watts. A basic block diagram is found in Fig. 7b. V AC R IAC I AC L Z CD S Q Q D V EA + Gate Driver Logic V REF C C Load Load X MULT X I MO + R V EA + V REF Fig. 7b. Basic block diagram of CRM boost PFC. -11

30 A. Multiplier Design Considerations The multiplier is the heart of a PFC controller. If everything else is designed and operating properly and the multiplier is set up incorrectly, the system will not achieve good PFC. This is easily seen if one considers that the output of the multiplier is the reference for the current loop. The current loop tries to force the inductor current to follow the multiplier output. If the multiplier signal is corrupted with noise or other sources of error, the current loop will force the line current to follow the corrupted signal. Fig. 7a and 7b shows a simplified representation of the key power stage and control elements of a boost converter. As shown, the input voltage waveform (converted to a current, I AC ) can be used as a reference to shape the input current waveform. The converter also needs to regulate the output voltage. The voltage error signal is combined with the I AC signal to generate a signal which has the same shape as the input current and is proportional to output power. A multiplier is used in the control circuit to generate a single control parameter (I MO ) from multiple inputs. In its most basic form, the multiplier combines the output voltage error signal (V AOUT ) generated by the voltage loop and the input voltage information represented by I AC. The output of the multiplier is a current reference signal (I MO ) that is compared (after appropriate scaling) against the actual inductor current I IN measured by the R SENSE resistor. The inner current loop ensures that the inductor current follows the commanded value accurately. The outer voltage loop regulates the output voltage, but it does so with a bandwidth less than one half the line frequency. If the voltage loop had higher bandwidth, it would interfere with the current loop and cause distortion in the line current. A closer look at the two-input multiplier reveals an inherent limitation when the input voltage (V IN ) changes. Fig. 8(a) and 8(b) show the input voltage and current waveforms for V IN of 10 Vac and 40 Vac, respectively. As shown, when V IN doubles, the input current (I IN ) has to halve in order to maintain constant power to the load. Fig. 9(a) and 9(b) show the two multiplier inputs for these conditions. The I AC input follows V IN and doubles. Since the multiplier output (I MO ) commands the input current, it has to halve, which can only be accomplished by reducing V AOUT by a factor of four. This effectively causes the voltage loop gain to vary proportional to the input voltage range squared I IN (a) V IN 10 V RMS Fig. 8a. Rectified line voltage and current. V IN 40 VAC (b) V IN 40 V Fig. 8b. Rectified line voltage and current. V IN 10 VAC I IN -1

31 I AC (a) V IN 10 V V AOUT Fig. 9a. Multiplier inputs (IAC and VAOUT) at low line and high line. I AC V AOUT In systems where higher performance is desired, the multiplier is modified to include an input voltage feedforward function (V FF ). [1] An appropriately scaled signal proportional to input voltage is added as an input to the multiplier. The inverse of the signal is squared (1/V FF ) and combined with the other input terms according to equation (31). With the addition of this term, the input voltage changes do not warrant a change in V AOUT for a given load. In fact, the voltage amplifier output becomes proportional to the output power for the normal operating range. To illustrate this, revisit the examples given in Fig. 8 and 9. Now, when V IN doubles, the new input (1/V FF ) will reduce by a factor of four, and coupled with a doubled I AC, will result in the desired value of half the original I MO without any change in V AOUT. A key advantage of this technique is constant loop gain and constant peak power over the entire input range. (b) V IN 40 V V RECT V RECT Fig. 9b. Multiplier inputs (IAC and VAOUT) at low line and high line. Many designs have a universal input voltage range of over 3:1 (85-70 VAC) causing the basic multiplier to tax the voltage error amplifier range considerably. With a 3:1 variation in line voltage the voltage loop gain must vary 9:1. This makes for a challenging design when stability, ripple voltage reduction and transient response specifications need to be met. In addition, it is often desirable to limit the power drawn from the line when the line voltage falls below the minimum specification. In order to provide protection to the supply and the source during a brown-out condition. Without input voltage information this function is difficult to implement. These challenges are often a good trade-off to the simplicity and low cost that is desired in lower power systems. Additionally we will see that there are techniques to improve the transient response of the lower bandwidth systems. IAC VFF IAC VFF Fig. 10. Input voltage feed-forward sensing schemes. IAC Now lets take a closer look at the multiplier design for the 3 input multiplier. Equation (31) is the fundamental equation that governs the multiplier operation, relating the current output of the multiplier (I MO ) to the three inputs. IAC ( VAOUT 1) IMO K (31) V FF Where: I AC Multiplier input current, proportional to instantaneous V IN V AOUT Output voltage error signal V FF Average value of rectified line voltage K Multiplier gain -13

32 The shape of the I MO current is similar to I AC and the rectified input voltage. For a given V IN, the peak of I MO is proportional to V AOUT. As already mentioned, it is important that the voltage loop has a crossover frequency significantly below the line frequency to prevent V AOUT from varying during a line cycle. In other words, during a line cycle, all inputs to the multiplier other than the I AC should ideally be constant. There are three parameters we will need to calculate or specify. First the input voltage feedforward term needs to be developed. In many ICs this voltage is derived through a resistor divider connected to the dc side of the bridge. Since this is the rectified line voltage, it needs to be filtered to remove the 10-Hz component. This can be accomplished with the use of a low pass filter. A two-stage filter was traditionally used to improve the transient response of the filter. However, in the new generation of controllers (e.g. UCC3817) this function has been simplified by mirroring the I AC current into a single-pole filter. This approach does have a slower transient response than the two-stage approach. However, the feedforward term is primarily intended to correct for the large variations in line voltage seen with universal applications. For a given power supply, the input voltage does not change instantaneously from 10 V to 40 V, so a fast transient response is really not required. This approach is shown in Fig. 10. The single pole filter approach lowers system cost with reasonable performance. Before designing the low pass filter for VFF the amount of attenuation needs to be determined. The amount of attenuation is driven by the allowable distortion budget. For a system looking to achieve 3% THD, it is typical to allow the feedforward circuit to contribute 1.5% 3rd harmonic distortion to the input waveform. [] This leaves 0.75% for the voltage loop and 0.75% for all others sources. The rectified line voltage is a 10-Hz signal. The percent of second harmonic in the waveform is 66.% of the average value. Therefore the attenuation needed is 1.5/66. or 0.0. From here it is easy to calculate the required pole frequency. A handy relationship to remember is that for a single pole roll-off (or 0 db/decade) a linear relationship exists between the gain and frequency (see Fig. 11). The desired gain at 10 Hz is 0.0, the gain at the pole frequency is approximately 1. Since we know 3 out of 4 variables, the pole frequency can be found: A 0.0 f P 10.6Hz (3) 1 f 1 A 1 f Frequency A 1 f 1 A f Fig. 11. V FF single pole filter characteristics. The filter is implemented with a parallel R/C circuit. The resistor is calculated to ensure the voltage on V FF stays within its dynamic range over the full line. At low line (85 V RMS ) we want the multiplier to start entering the power-limiting region (see Fig. 13). [1] In the UCC3817 and UCC38500 control ICs the multiplier starts limiting current when V FF 1.4 V. Therefore the resistor is chosen so that at low line the voltage at the multiplier input is equal to 1.4V. If at high line the peak I AC is 500 ua then the dc current through the RMS resistor will be I AC divided by (due to the internal current mirror) times 0.9. The 0.9 term is the conversion factor for RMS to dc for a full wave rectified signal. This gives a resistor value of 5 kω. The capacitor required to give a pole frequency of.6 Hz is approximately. µf. A -14

33 Completing the multiplier set up is determining the IMO resistor. The typical approach [15], for ICs which incorporate a powerlimiting characteristic, is to design for maximum power at minimum line. Fig. 13 shows the product of V FF and I MO-PK (a quantity representative of input power since V FF and I MO-PK are proportional to V IN-RMS and I IN(PK/RMS), respectively) as a function of V FF (again, proportional to V IN-RMS ) for a fixed value of V AOUT. For this discussion, the curve can be viewed as representing the maximum V AOUT (full load) condition. There are two distinct regions of operation. The first region, labeled constant power region, is the area where the multiplier operates over nominal line range. Referring to Equation (1) and rearranging terms, it can be seen that the I MO-PK V FF term will be constant over the V IN range for a given V AOUT. This is because I AC-PK and V FF vary proportionally. The second region, labeled power limiting region, is important for protecting the converter under line dropout or brownout situations. The multiplier output is limited in this region so that the input current is contained and the power stage components are protected from overheating at low line operation. In this region, the output power requirements are not met and the output voltage starts dropping. [] The key is to pick a multiplier-terminating resistor so that the multiplier can command sufficient current from the line to satisfy the load. The worst case, or maximum current required is at low line voltage, with maximum load. Again, the typical approach is to use the fundamental multiplier equation and plug in the appropriate conditions. Solving (31) (with I AC 500 ua, V FF 1.4 V and V AOUT 5 V) gives an I MO 360 µa. The voltage required at the I MO pin is the voltage which when developed across the R sense resistor will translate into the required line current to support the load. For a 50 W converter, (low line I INpk is 4.4 A) and a 0.5 Ω sense resistor, this translates to: IINpk RSense RIMO 3kΩ (33) IMO There is, of course, a wrinkle in this design procedure. This assumes that the IC multiplier will supply exactly the desired current for the given inputs. In other words, the multiplier behaves exactly according to equation (31). In reality the multiplier has a tolerance associated with it. In order to ensure that the converter will be able to supply the required power, the calculations should be checked at high line and low line using the minimum multiplier current. In most cases a larger R IMO will be required. Again refering to Fig. 13, the effects of these variations in multiplier current can be seen. The upper deviation is normally not a cause for concern because supporting higher power at higher line voltages will not cause additional thermal stress on the system (since the input current is still less than it is at low line, full load). Once the minimum multiplier resistor is found, the input power should be calculated over the corners of multiplier operation. The main issue to be analyzed is the maximum power the converter is now able to draw from the line. Keep in mind that in parts that allow the upper range of multiplier current the voltage amplifier will still regulate the output so that only the required current will be supplied to the load. This simply means that in a fault condition, the load can increase up to the new level. The power supply has a handle to limit this potential problem though. Peak current limit will limit the input current on a cycle-by-cycle basis. This will prevent the power stage from experiencing excessive thermal problems. The choice of power devices and thermal design should take this into account. Fig. 1 shows the peak multiplier output current (I MO-PK ) verses V AOUT for a given line voltage (V IN and V FF ). The instantaneous I MO will vary between 0 and I MO-PK during a line cycle. Any multiplier non-idealities in the middle portion of the curve can be compensated by adjusting V AOUT through the outer loop. For example, if I MO is not adequate at a given condition, V O will drop, V AOUT will increase and I MO will be adjusted. -15

34 I MO-PK Residual Current 1.0 V Variation During a Line Cycle 5.5 V Fig. 1. Peak multiplier output current. I MO-PK * V FF (α Pin) Power Limiting Region Low Line Constant Power Region High Line V FF Fixed Variations from ideal V AOUT V FF (α V IN ) Fig. 13. Multiplier power profile, as a function of line for a fixed V AOUT. At low power operation, V AOUT approaches the lower end of its operating range (1 V) and commands zero I MO at no load. If there is residual (non-zero) I MO at this point, some power will be delivered to the load. In the extreme case, this can lead to overvoltage on the output and trigger the OVP (overvoltage protection) circuit in the system. The consequences of reaching an overvoltage condition include higher stress on the devices (output cap, diode and FET) as well as controller biasing (Vcc) problems. During the OVP condition, switching is stopped and the selfbias circuit used in many systems (a winding off the boost inductor) loses its energy source. The controller Vcc can fall below the UVLO (undervoltage lockout) turn-off threshold during this condition and lead to a hiccup operation mode. To prevent this effect, the residual I MO should be minimized. In addition, an alternate path to limit switching can be provided. Once V AOUT falls below a set threshold (e.g V), it can be interpreted as a zero power command and a direct signal to the output to stop switching can be generated. This zero power detect (ZPD) technique, incorporated in the new generation PFC controllers, helps prevent an overvoltage condition. Another benefit of the ZPD technique is that it also compensates for input offset voltage in the current error amplifier. It can be shown that positive current amplifier input offset voltage can also result in power delivery under no load conditions (same effect as described above). Some controllers intentionally skew the offset in the opposite direction to negate this effect. However, that results in distortion near every zero crossing (due to the artificial offset). With the ZPD technique, the current amplifier can be designed for near-zero offset with assurance that the low power mode will be adequately handled. The two input multiplier is fairly easy and straightforward to set up. The multiplier output is terminated within the IC, so there is now need to calculate a R IMO. Additionally there is no V FF to set up. The line input circuit needs to be configured to provide the correct voltage over the line range. This is accomplished by a simple voltage divider off the rectified line with the main criteria being that the voltage stays within the input voltage specification of the IC over the full line range. The only other input is the voltage amplifier, which we will discuss in the next section. B. Control Loop Design Considerations The design of the voltage and current loops has a large impact on system performance. Both loops can directly contribute to line current distortion. Several good references exist which go into detail on the theory as well as the details of control loop design. [1,,8,18] Designing the current loop is usually the first step after the power stage has been designed. The main job of the current loop is to force the inductor current to follow the multiplier reference current. Keep in mind that the reference current is not simply a 10-Hz waveform. A full-wave rectified waveform is rich in harmonics. This waveform has a high dv/dt around the zero crossings of the line. A current loop bandwidth of around 10 khz, for a line frequency of 50 Hz to 60 Hz, is usually adequate. The CRM topology really doesn t require a current loop design. The control law is simple hysteretic control (with the lower boundary set to zero), so there is no compensation to be designed. -16

35 The only thing that needs calculating is the current sense resistor. This is fairly straightforward. You simply ensure that the peak current produces a voltage which, when compared against the peak multiplier signal, is sufficient to produce maximum power. Average Current Mode Control The ACMC converter does have an inner current loop, which needs compensation. In order to properly compensate the loop a model of the converter is needed. A small signal model of the converter based on the PWM switch model is shown in Fig. 14. [18] I L L + - D 1 V O D Fig. 14a. Exact model of boost PFC using PWM switch model. I L Fig. 14b. Simplified model. L + - d I Ld D 1 V O D Fig. 14a shows the exact model, while Fig. 14b shows the simplified model if we assume the output capacitor is large and the switching frequency ripple is small. This is a reasonable approximation for realistic circuit designs. d I Ld C R The transfer function for the circuit in Fig. 14a is shown below. s 1+ V R G (s) out SENSE ωz id R ( 1 D) s s 1+ + ωo Q ωo 1 D ωz, ωo R C LC Q R 1 ( D) C L (34) The R sense term isn t seen directly from the figure but is included here since it relates the actual inductor current to the signal seen at the IC. This equation is plotted in Fig. 15 for high line and low line. At higher frequencies the plot converges to the simplified model shown in Fig. 14b. The simplified model is easier to use and is adequate to design the current loop. The exact model is shown to explain what is seen if one measures the loop. Magnitude - db Exact, Low Line 0 log( Gidexact( Si) )) Loop Gain 0 log( Ti ( Si) )) Error Amp (( Av( Si) ) 0 log Exact, High Line 0 log( ( Gidexact ( Si) )) Simplified Gid(s) 0 log ( Gid ( Si ))) k 10 k 100 k f - Frequency - Hz Fig. 15a. Magnitude of the current loop, eqn 34,35 and E/A transfer function. -17

36 Phase - degrees Loop Gain 180 arg(ti(si )) π Fig. 15b. Phase plots. Phase at High Line 180 arg(gidexact(si )) π Phase at Low Line 180 arg(gidexact(si )) π Simplified Model Phase 180 arg(gid(si )) π k 10 k 100 k f - Frequency - Hz The simplified current loop transfer function is given in equation (35). This has a single pole response at the usual frequencies of interest. It is typically compensated with a two pole, single zero error amplifier as shown in Fig. 16. The zero is placed to achieve the desired phase margin and the high frequency pole is placed to filter switching noise. [18] Vout R G SENSE id(s) (35) s L VSE where V SE is the oscillator voltage peak to peak. A step by step design procedure is given below. First calculate the gain of the power stage at the desired crossover frequency (f c ): V R G (s) out SENSE id x (36) π fc L VSE Set the midband gain (A v ) of the current loop error amplifier to be 1/x. The resistors Rf and Ri set the midband gain. 1 1 G f EA Av (37) Gid(s) x Ri The zero of the compensation network (f z ) is placed at the crossover frequency. 1 fz fc Cz (38) π Rf fc The compensator pole is placed between ½ f s (switching frequency) and f s to attenuate noise, see equation (39). 1 fp Cz Cp π Rf Cz C + p (39) 1 1 Cp π Rf Cp π Rf fp A V R f R i C P + C Z R f Z f P f 1+ sr C A f Z V sri(cp + CZ)(1 + srf CP CZ) Fig. 16. Current loop error amplifier. R f R i CAOUT -18

37 C. Voltage Loop Design There are some trade-offs inherent in the voltage loop design that are particular to PFC applications. The fundamental requirement of power balance, on the line frequency time scale, requires that the voltage loop s bandwidth must be less than the line frequency (actually less than 1/ the line frequency). If not, the voltage loop will distort the line current in order to regulate the output voltage. This creates a trade-off between power factor and transient response. Since the loop bandwidth is low to begin with, it is normally advised to avoid integral compensation due to the further reduction in transient response that the relatively large feedback capacitor will cause. The large feedback capacitor required for integral compensation will limit the slew rate of the error amplifier. This is especially troublesome at start up when the poor transient response can cause a large overvoltage condition. Another issue is that the dc regulation of the output voltage is proportional to the loop gain. With the voltage loop gain set relatively low (with proportional gain), the output voltage will vary widely with line and load. Since the load of a PFC circuit is typically another converter, dc regulation may not an issue, and start up transient response can be more of a concern (due to the voltage stress on the output capacitors). However, in some applications where the downstream converter is optimized for a narrow input voltage range or when maximum hold up time is required, dc regulation is more of an issue. Additionally, some PFC controllers employ a transconductance type amplifier. This is often done so that multiple functions, such as over voltage detection, can be incorporated on one IC pin. The traditional voltage type error amplifier precludes this since in a closed loop system the Vsense pin is not proportional to Vout. A transconductance amplifier s sense pin gives a true measure of output voltage whether the loop is in regulation or not. However, transconductance amplifiers are compensated by connecting an impedance between the amplifier s output and ground. Usually the amplifier s output current capability is insufficient to drive a resistive load unless the desired dc gain is very high. This implies capacitive loading and hence integral gain. In both cases then (transconductance amplifier or needing tighter dc regulation) integral compensation can be used. The gm amplifier configuration is shown in Fig. 17. V OUT V REF + C1 R C 1+ SRC1 A V gm S(C1 + C)(1 + SRC1C) Fig. 17. gm amplifier configuration. Integral compensation will provide zero dc error. However, since the power stage has a single pole roll-off and the integrator adds another 90 degrees of phase shift at low frequency, a zero is needed before the loop crossover frequency. Since a zero in the compensation network becomes a pole in the closed loop gain, this zero will become the dominant pole in the system and placing this zero as high as possible in frequency will improve the transient response. Since the loop has such poor bandwidth, any improvement is welcome. The model of the power stage with the current loop closed is shown in Fig. 18. For the case where the load is a dc-to-dc converter, the load is considered a constant power load. Therefore it has a negative small signal resistance associated with it. The negative resistance is equal an opposite in sign to the dc resistance and the two cancel each other. The gain of the power stage is given by equation (40). [] (s) G PS Pin (40) ( s Cout) Vout Vaout -19

38 jv C + V O r O C R L Fig. 18. Small signal model of outer voltage loop. For constant power loads, r o -R L. The gain for the CRM converter would be essentially the same. However, in some cases the control circuit uses a multiplier without the feedforward term. The loop gain is then a function of input voltage and is shown in equation (41). [] G PS (s) k1 VAC (41) ( s Cout) Vout Rsense kcrm where k 1 is the multiplier gain, including the input voltage divider and k crm is a factor of for the case where the power stage is operating in CRM mode. This factor accounts for the fact that the peak of the input current is actually twice the average value. The main design criteria for the voltage loop is usually reduction of the 10-Hz ripple component being fed back to the multiplier. [] This is due to the fact that the ripple at the output of the voltage error amplifier is a major contributor to 3rd order harmonics in the line current. However, in some cases some increased 3rd order harmonic distortion can be tolerated and traded-off for improvements in transient response. There are several options for designing the voltage loop compensation [13]. When using integral compensation, trade-offs can be made between 10 Hz attenuation and transient response improvements. You can trade off response using similar techniques as typically used when designing traditional voltage loops, with the added specification being 3rd order harmonic reduction. - Besides compensation methods to speed up transient response, the amplifier itself can be modified to improve the response. In systems which use a transconductance amplifier is is especially useful. There is a trade-off in designing the transconductance (gm) amplifier. For a simple gm amplifier the output current is related to the gm of the amplifier. More drive current helps slew the feedback capacitor. However, as the current is increased, the gm increases. For a given pole frequency, the higher gm tends to cause a larger capacitor to be required. This defeats the advantage of higher current capability. The trick is to design the amplifier with the appropriate amount of small signal gain (gm) while increasing the transient current capability of the amplifier. Once the Vsense pin exceeds a threshold, it is a good indication that there is a transient condition and the loop needs to respond to force the output back into regulation. At this point the amplifier increases the drive current which causes the voltage on the feedback capacitors to slew. This amplifier output current characteristic is shown in Fig. 19a and Fig. 19b. Fig. 19a shows the small signal gain of the amplifier. Fig. 19b, shows the increased current capability as the error signal is increased. The advantage is that the amplifier is able to slew the compensation components quickly, and therefore can respond during start-up or a transient, before the output voltage overshoots excessively. This technique is implemented in some newer PFC controllers such as the UCC3851x, and UCC38050 family of controllers. Returning to the compensation procedure, if we use the traditional approach to compensate the loop we first need to calculate the output voltage ripple. [] Equation (4) gives the peak ripple on the boost capacitor. Pin vopk (4) ( π fripple Cout) Vout -0

39 Recall from the multiplier section that we allow a 0.75% 3 rd harmonic distortion contribution from the voltage amplifier. This distortion will be generated by 1.5% of the 10 Hz ripple feed back into the multiplier []. From this you can calculate the attenuation required and therefore the error amplifier gain at 10 Hz. If we assume the ripple voltage is 4 V, 1.5% is 60 mv. Therefore the amplifier gain (G VEA ) at 10 Hz is 60 mv/4 V or or 36 db. The gain of the power stage is shown in equation (43). (s) G PS Pin (43) ( s Cout) Vout Vaout One approach to closing the loop is to use an error amplifier with the same configuration as we used in the current loop. In this case we calculate where to place the second pole of the error amplifier by placing it at the loop gain cross-over frequency. In other words we know the loop gain response after the zero crossing is a double pole, and we know the desired gain at 10 Hz, we can therefore calculate the frequency where we will cross 0 db. fpole 10Hz GPS(10) GVEA(10) (44) In order to maintain adequate phase margin, the zero is placed well below the pole frequency. If it is placed a full decade below, the voltage loop will have about 45 degrees of phase margin. For example, if we assume a transconductance amplifier with a gm 100µS, and we know the desired gain of the error amplifier at 10 Hz, we can calculate the required compensation network. Gvea gm Zout (45) where Gvea is the voltage amplifiers gain. We know the attenuation we need at 10 Hz (in this case 0.015). In a transconductance configuration, the output voltage divider contributes to the attenuation also, so the error amplifier gain is: G10 Hz Gvea 10 Hz (46) Vdivider Zout is the impedance of the compensation network at 10 Hz. A good approximation is: 1 C π 10 Zout (47) A Bode plot of an example is shown in Fig. 0. Iout Vsense Fig. 19a. Small signal gain (transconductance) of the amplifier. Iout Vsense Fig. 19b. Large signal gain, showing increased current capability

40 CONCLUSION/SUMMARY Several of the more important design considerations for PFC converters have been presented. One of the first choices a power supply designer most make is which topology to use for a given application. A framework for comparing the CCM boost with the CRM boost converter has been presented. The main trade-off in the comparison is lower losses due to no reverse recovery in the boost diode vs. higher ripple and peak currents in the devices. This trade-off usually favors the CRM technique at power levels below a few hundred watts. Above that range the higher currents and the increased filter requirements for the CRM topology make the CCM technique more attractive. We have also reviewed the main design considerations for the power stage and control circuit design. General guidelines have been presented. Magnitude - db Error Amp x Voltage Divider Loop Gain Error Amplifier Power Stage Gain k f - Frequency - Hz Fig. 0. Bode plots for outer voltage loop design. -

41 REFERENCES [1] L. H. Dixon, High Power Factor Preregulators for Off-Line Power Supplies, Unitrode Power Supply Design Seminar Manual SEM600, 1988 [] L. H. Dixon, Optimizing the Design of High Power Factor Switching Preregulator, Unitrode Power Supply Design Seminar Manual SEM700, 1990 [3] T.S. Key; Jih-Sheng Lai, IEEE and international harmonic standards impact on power electronic equipment design, Industrial Electronics, Control and Instrumentation, 1997 [4] M. Madigan, et.al, Integrated High Quality Rectifier-Regulators, PESC 9 [5] Qiao; K. Smedley. A Topology Survey of Single-Stage Power Factor Corrector with a Boost Type Input-Current-Shaper, APEC 000. [6] Uan-Zo-li.; Jindong Zhang; F.C. Lee; J.P. Noon. Study and design considerations of a voltage-source single-stage PFC converter, Industry Applications Conference, 000. Volume 4, 00 [7] V. Vlatkovic, D. Borojevic, and F.C. Lee, Input Filter Design for Power Factor Correction Circuits, International Conference on Industrial Electronics, Control and Instrumentation, November 1993 [8] R.W. Erickson; D. Maksimovic, Fundamentals of Power Electronics, nd Ed. (Kluwer, 001) [9] Y. Khersonsky, M. Robinson, D. Gutierrez. New Fast Recovery Diode Technology Cuts Circuit Losses, Improves Reliability [10] D.S. Chen, J.S. Lai, Design Consideration for Power Factor Correction Boost Operating at the Boundary of Continuous Conduction Mode and Discontinuous Conduction Mode, IEEE APEC 1993 [11] L. Balogh, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas Instruments Power Supply Design Seminar 001, SEM-1400 [1] J. Zhang, et al. Evaluation of Input Current in the Critical Mode Boost PFC Converter for Distributed Power Systems, IEEE APEC 001 [13] J.P. Noon, D.Dalal, Practical design issues for PFC circuits, IEEE APEC [14] L. Dixon, Unitrode Magnetics Design Handbook, MAG 100A. Texas Instruments [15] UCC3817 data sheet, Texas Instruments Power Supply Control Products. [16] H. Kapels, et al. SiC Schottky Diodes: Ready to Blast OFF, Power Electronics Technology, January 00 [17] Carsten, Simplified Calculation of Magnetic and Electrical Losses in Unity Power Factor Boost Preregulators, Published by Micrometals Inc. [18] Zhou and M.M. Jovanovic, Design Trade- Offs in Continuous Current-Mode Controlled Boost Power Factor Correction Circuit, High Frequency Power Conversion Conference May 199-3

42 APPENDIX This worksheet calculates the relevant currents and voltages as well as losses in PFC boost topologies. Constant output voltage and continuos conduction mode (CCM) and critical conduction mode (CRM) operation is assumed. Constants: p : 10 1 nano : 10 9 u : 10 6 m: 10 3 k: 10 3 MEG: 10 6 j: 1 i : y : x: Fs : 100 k Vout : 385 VAC_min: 85 VAC: 10 Pout Pout : 00 η : 0.95 Pin : Iload : η Pout Vout Pin_var allows input power to be varied over a range to compare losses. Pin_var x : Pin ( x + 1) j: VAC: Vin i : VAC π sin i 00-4

43 Boost converter duty cycle Vout Vin i D i : Vout Average boost inductor current in CCM. IAC i : Vin i Pin VAC A. Calculate currents in the CCM boost RMS switch current Iq_rms_ccm : Pin VAC π VAC Vout Iq_rms_ccm RMS switch current varying as a function of input power. Iq_rms_ccm_var x : Pin_var x VAC π VAC Vout Peak inductor current IL_pk_ccm : Pin VAC Pin VAC Let delta i in CCM inductor be 0% of peak current at low line. IL_ripple : 0. Pin VAC Pk current is Iin avg + 1/ delta i Peak inductor current as a function of input power IL_pk_ccm_var x : Pin_var x VAC 0.1 Pin_var x + VAC Inductor current valley IL_valley_ccm : Pin VAC 0.1 Pin VAC IL_valley_ccm.33 IL_valley_ccm_var x : Pin_var x VAC 0.1 Pin_var x VAC -5

44 Peak diode current is equal to the peak inductor current. Idiode_pk_ccm : IL_pk_ccm B. Calculate currents in the CRM boost converter: IL_pk_crm: Pin VAC IL_pk_crm 4.96 Peak current in CRM is twice the CCM current, neglecting the ripple current for CCM. IL_pk_crm_var x : Pin_var x VAC IL_pk_crm_var x : Pin_var x VAC Iq_rms_crm : VAC IL_pk_crm 9 π Vout Iq_rms_crm Iq_rms_crm_var x : 6 4 VAC IL_pk_crm_var x 9 π Vout Idiode_pk_crm : IL_pk_crm C. Calculate loss components. Calculate diode related losses: Assume di/dt at turn off is 100A/us. For the purpose of calculation use the 8ETH06 IR diode as reference. Also assume IRF840 for MOSFET VFF: 0.6 trr : 50 nano Qrr : 10 nano Irrm: 4.8 didf : Rdson 0.85 u : transistor_rise : 75 nano transistor_fall : 75 nano π Irrm_pfc i : Irrm sin i 00-6

45 Loss in MOSFET due to reverse recovery current from boost diode. Only valid for CCM operation. Prr_ccm_var : i 00 i i 0 i Vout 0 i 0 Vout Vout Vout Irrm_pfc i Irrm_pfc i didf 1.5Irrm_pfc i Irrm_pfc i didf Vout ( Irrm_pfc) i Irrm_pfc i didf (.5Irrm_pfc) i Irrm_pfc i didf ( 3Irrm_pfc) i Irrm_pfc i didf Prr_ccm_var Irrm_pfc i + 4 ( 1.5Irrm_pfc) i + 4 ( Irrm_pfc) i + 4 Irrm_pfc i trr didf Irrm_pfc i trr didf Irrm_pfc i trr didf.5irrm_pfc i + 4 ( 3Irrm_pfc) i + 4 Fs Irrm_pfc i trr didf Irrm_pfc i trr didf Fs Fs Fs Fs -7

46 Losses in MOSFET due to turn-off overlap of voltage and current: Pq_ccm_turnoff_var : i 00 i 00 0 i 00 0 i i 0 Vout Vout Vout Vout Vout π IL_pk_ccm_var 0 sin i π IL_pk_ccm_var 1 sin i π IL_pk_ccm_var sin i π IL_pk_ccm_var 3 sin i π IL_pk_ccm_var 4 sin i transistor_fall ( ) transistor_fall ( ) transistor_fall ( ) transistor_fall ( ) transistor_fall ( ) Fs Fs Fs Fs Fs -8

47 Losses in MOSFET due to turn-on overlap of voltage and current: Pq_ccm_turnon_var : i 00 i 0 00 i 00 Vout 0 i 00 0 i Vout Vout Vout Vout π IL_valley_ccm_var 0 sin i π IL_valley_ccm_var 1 sin i π IL_valley_ccm_var sin i π IL_valley_ccm_var 3 sin i π IL_valley_ccm_var 4 sin i transistor_rise ( ) transistor_rise ( ) transistor_rise ( ) transistor_rise ( ) transistor_rise ( ) Fs Fs Fs Fs Fs Conduction losses in the MOSFET: Pq_ccm_rms_var : ( Iq_rms_ccm_var 0 ) Rdson ( Iq_rms_ccm_var 1 ) Rdson ( Iq_rms_ccm_var ) Rdson ( Iq_rms_ccm_var 3 ) Rdson ( ) Rdson Iq_rms_ccm_var 4-9

48 Diode conduction losses: Pdiode_ccm_var : i 00 i 00 0 i 00 0 i i 0 π IL_pk_ccm_var 0 sin i π IL_pk_ccm_var 1 sin i π IL_pk_ccm_var sin i π IL_pk_ccm_var 3 sin i π IL_pk_ccm_var 4 sin i ( ) VFF 1 D i ( ) VFF 1 D i ( ) VFF 1 D i ( ) VFF 1 D i ( ) VFF 1 D i -30

49 Diode bridge conduction losses: Pdiodebridge_ccm_var : i 00 i 00 0 i 00 0 i 00 0 i π IL_pk_ccm_var 0 sin i π IL_pk_ccm_var 1 sin i π IL_pk_ccm_var sin i π IL_pk_ccm_var 3 sin i π IL_pk_ccm_var 4 sin i VFF ( ) VFF ( ) VFF ( ) VFF ( ) VFF ( ) P1 : Prr_ccm_var + Pq_ccm_turnoff_var + Pq_ccm_turnon_var P : Pq_ccm_rms_var + Pdiode_ccm_var + Pdiodebridge_ccm_var P_loss_semi_ccm_var : P1 + P P_loss_semi_ccm_var

50 Calculate losses in the CRM boost. Let the average Fs for CRM operation be 80kHz. Fs_crm : 80 k Losses in MOSFET due to turn-off overlap of voltage and current: Pq_crm_turnoff_var : i 00 i 00 0 i 00 0 i 00 0 i Vout Vout Vout Vout Vout π IL_pk_crm_var 0 sin i π IL_pk_crm_var 1 sin i π IL_pk_crm_var sin i π IL_pk_crm_var 3 sin i π IL_pk_crm_var 4 sin i transistor_fall ( ) transistor_fall ( ) transistor_fall ( ) transistor_fall ( ) transistor_fall ( ) Fs_crm Fs_crm Fs_crm Fs_crm Fs_crm MOSFET conduction losses: Pq_crm_rms_var : ( Iq_rms_crm_var 0 ) Rdson ( Iq_rms_crm_var 1 ) Rdson ( Iq_rms_crm_var ) Rdson ( Iq_rms_crm_var 3 ) Rdson ( ) Rdson Iq_rms_crm_var 4-3

51 Diode conduction losses: Pdiode_crm_var : i 00 i 00 0 i 00 0 i i 0 π IL_pk_crm_var 0 sin i π IL_pk_crm_var 1 sin i π IL_pk_crm_var sin i π IL_pk_crm_var 3 sin i π IL_pk_crm_var 4 sin i ( ) VFF 1 D i ( ) VFF 1 D i ( ) VFF 1 D i ( ) VFF 1 D i ( ) VFF 1 D i -33

52 Bridge diode conduction losses: Pdiodebridge_crm_var : i 00 i 00 0 i 00 0 i 00 0 i π IL_pk_crm_var 0 sin i π IL_pk_crm_var 1 sin i π IL_pk_crm_var sin i π IL_pk_crm_var 3 sin i π IL_pk_crm_var 4 sin i VFF ( ) VFF ( ) VFF ( ) VFF ( ) VFF ( ) Total semiconductor losses in CRM: P3 : Pq_crm_turnoff_var + Pq_crm_rms_var P4 : Pdiode_crm_var + Pdiodebridge_crm_var P_loss_semi_crm_var : P3 + P4 for Fs_crm 80kHz P_loss_semi_crm_var P_loss_semi_ccm_var

53 This plot compares the semiconductor losses for CCM vs. CRM as a function of input power P_loss_semi_ccm_var Loss - W P_loss_semi_ccm_var Pin_var x Efficiency comparison of CCM vs. CRM as a function of input power Pin _ varx (P _ loss _ semi _ ccm _ var) x 100 Pin _ varx 94 Efficiency - % Pin _ varx (P _ loss Pin _ varx _ semi _ crm _ var) x Pin_var -35

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55 Achieving High-Efficiency with a Multi-Output CCM Flyback Supply Using Self-Driven Synchronous Rectifiers Robert Kollman ABSTRACT Broadband access devices are placing high efficiency and low cost requirements on low power, isolated converters. The discontinuous flyback converters has been the traditional choice at these power levels but continuous mode operation is quickly becoming favored as it allows the use of self driven synchronous rectifiers. This paper addresses some of the challenges to CCM operation and their solutions. In particular, the paper discusses the rationale for the selection of the topology. It then provides calculation of circuit stresses and magnetic requirements of the power stage. It also provides analysis and compensation of the power stage with its moving right half plane zero. Finally, measurements of circuit operation are presented to validate the theoretical circuit analysis. I. INTRODUCTION High speed internet connections are replacing the traditional telephone connection at customer premise. Voice data can easily be sent over these high speed connections whether it is digital subscriber line (DSL) or cable. However, adding this voice capability has more consequences than just using up some of the available bandwidth because the telephone needs to work even though the power to the customer s premise has been interrupted. In both cable modems and DSLs, two approaches have been implemented; battery back-up at the customer premise or power down the cable/twisted pair. Each approach has it advantages and disadvantages. Battery back-up requires a rather large and expensive battery that is mounted in a controlled environment such as a garage. This requires that the broadband access provider have access to the customer premise for installation and maintenance, which further adds to system cost. In the line powered approach, power is conditioned at a central location and fed down the wire to the customer premise. Since no battery is required, the customer premise equipment can be located outside and access is much easier for the provider. The customer may even be able to handle the installation. However, the provider wants to serve as many customers as possible from a single location so long lengths of wire are used. In the DSL application, this wire can have as much as 1000 ohms of resistance so a relatively high voltage source is required which safety and insulation concerns limit to around 00 V. Adding the fact that the load consumes nearly 10 watts of power further constrains the power supply requirements. Maximum power transfer and system stability both set the minimum usable voltage to one half the source voltage so, in the worst case, only 100 V is available at the customer premise. 100 volts across 1000 ohms of line resistance and 100 volts at the CPE limits the available power to 10 watts so very high power supply efficiencies are required. A similar situation exists in the cable modem systems but is complicated by the use of AC power distribution so power factor becomes an issue. 3-1

56 TABLE 1. MANY BROADBAND ACCESS DEVICES REQUIRE LOW COST AND HIGH EFFICIENCY Input Voltage Cable Modem 40 Vrms to 90 Vrms Quasi-square wave, 60 Hz or 50 VDC to 150 VDC Outputs 5. V at 0.6 A, 3.3 V at 0.8 A, 1.8 V at 0.3 A, 1.5 V at 0. A, -4 V at 0.1 A, -7 V at 0.1 A BNID DSL Modem 100 VDC to 00 VDC 5 V at 0.03 A, 3.3 V at 1.8 A, +/-1 at 05 A, -4 V at 0.1 A, -7 V at 0.1 A Low Voltage Power (W) 6.6 W 7.3 W Minimum Efficiency 85% 85% Isolation 1500 VAC 500 VDC Cost Target ($) <$10 <$10 Table 1 presents a summary set of specifications for the customer premise power for these types of systems. Both systems run from a relative high voltage that can have a widely varying source impedance and voltage depending on the distance from the central office or remote terminal and the load demand. In each system, there are a number of output voltages loosely falling into two categories, power for the low voltage electronics and power for the phone. Generating the low voltages efficiently will be the topic of this paper; however, the final power supply will need to address the phone loads also. The power for the low voltage is around 7 watts in both cases and that pushes the efficiency requirement due input power limitations. The peak phone power pushes the output power above 10 watts. The situation is not as bad as it first looks though as the 4 V load does not occur simultaneous with the 7 V. In both cases, the provider is willing to pay for an efficient power supply as this enables him to serve more customers from a single location and limits the power conditioning he has to provide there. Both systems require input to output isolation and both are extremely cost competitive. II. TOPOLOGY While the requirements are for a multiple converter, this paper will concentrate on providing the 3.3 volt output only. At these power levels, the flyback topology is very attractive due to its low parts count and good cross regulation of multiple outputs. Synchronous rectification is needed to meet the efficiency goals as a Schottky diode with a 0.45-V forward voltage used on a 3.3-V ouput drop would limit efficiency to 88% just considering the rectification process. Additional circuit losses would probably drop efficiency to the low 80 percent range. At this power level, discontinuous conduction mode (DCM) of operation looks attractive, however, DCM creates an issue in the drive of the synchronous rectifiers. Fig. 1 illustrates the problem. The flyback works by storing energy in the primary of the power transformer while Q1, the primary switch, is on. Current builds in the primary inductance and once an appropriate amount of energy is stored, Q1 turns off. Then the voltage on the transformer reverses and energy is delivered to the secondary through the synchronous rectifier, Q. Generating the timing of drive for Q1 is not an issue as it is determined by the amount of energy that should be stored in the transformer. The issue is generating the drive waveform for the synchronous rectifier. Turn on can be controlled by the change in polarity on the power transformer, however, turn off can not be controlled in this manner. There are three operational states to this circuit, two of which are not controlled by the control circuits. The primary FET on time is controlled but the synchronous rectifier conduction time and the time when both FET s are off are not controlled. In the non synchronous flyback, once the current has decayed in the transformer secondary magnetizing inductance, the voltage collapses toward zero. However, if a FET was used in place of the diode and its gate was driven from the transformer, the FET would have no turn off command. The secondary current would still decay to zero, gate drive would still be present and then the current would reverse. So a circuit is 3-

57 required to detect the current reversal and turn the FET off. An interesting side note is that one can achieve zero voltage switching of both FETs with this approach. The timing would require a delay from the turn off of the primary switch before turning on the secondary switch on the first transition. During the second transition, the secondary circuit would have to generate an appropriate amount of reverse current in the transformer before turning off the synchronous rectifier. This energy could then drive the drain of the primary FET to ground prior to its turn on. The advantages of this mode of operation is zero voltage switching of both FETs. The disadvantages are a relatively complicated control and drive circuit and variable frequency operation. Input Power Iprimary Isecondary Desired SR Gate Drive 4 T1 Q Increasing Load C1 Output Q SR Control Light Load Heavy Load Fig. 1. DCM flyback synchronous rectifiers control needs to sense zero current. Due to circuit simplicity and low cost, the continuous conduction mode (CCM) flyback is an alternative topology. It is particularly effective for multiple outputs as it improves cross regulation. CCM also reduces circuit stresses significantly. As shown in Fig., current waveforms are trapezoidal rather than triangular. This means that for the same amount of output power, RMS currents are 15% less which means reduced conduction losses (30%) in the power semiconductors and reduced (as much as 50%) filtering requirements in both input and output capacitors. In addition, switching losses could be substantially reduced as peak currents are reduced by a factor of two. However, this is complicated by the fact that a transformer designed for continuous operation will have more leakage inductance than one designed for discontinuous. This inductance must be discharged each switching interval and could lead to significant losses. Gate drive timing for synchronous rectifiers is simpler because there are two states rather than the three of the discontinuous mode. In fact, the synchronous rectifier can be driven directly from the power transformer. In Fig., Q4, the primary switch is turned on and an incremental amount of energy is added to the power transformer. Q4 is then turned off and the transformer voltage reverses and energy is delivered to the secondary through Q3. When Q4 turns on again, the cycle is repeated. The turn off of Q4 and turn on of Q3 are made with a low voltage present, so they can be termed zero voltage switching. However, the other transition is not as benign as Q4 is turned on with the full input voltage plus the reflected output voltage across it. In addition, it incurs a loss mechanism similar to reverse recovery in an output rectifier, the transformer voltage must collapse to a point to turn the synchronous rectifier off before the synchronous rectifier is disconnected from the circuit. This causes a high current to flow for a brief period in both the rectifier and main switch and leads to switching losses in both of them. 3-3

58 Input Power T 4 Q Q3 C Output current and both transitions could be made with zero switching losses. However, this requires a separate driver with a current sense circuit rather than using the transformer, but results in zero voltage switching and the elimination of the shoot thru current during the turn on of the primary FET. T 7 8 Q3 Output Increasing Load 4 9 C Iprimary Input Power Q4 Isecondary Desired SR Gate Drive Light or Heavy Load Iprimary Increasing Load Fig.. The CCM flyback can use self driven rectifiers to improve efficiency. The other significant disadvantage of this approach, is the control characteristics are not as straight forward as the DCM approach. Even with current mode control, this circuit has a right half plane (RHP) zero. In the frequency domain, this RHP zero adds a phase lag to the control characteristics but increases the gain of the circuit. Typical rules of thumb state the highest useable loop crossover frequency is limited to one third the value of the RHP zero. The expression for the location of the RHP zero in a continuous mode flyback is given by: RHPZ R 1 ( 1 D) π L D where R l is the load resistance, L is the secondary reflected transformer magnetizing inductance and D is the duty factor. The inductance can be minimized to move the RHP. The resulting waveforms are shown in Fig. 3. Rather than having a shallow slope on the current waveform, the slope is similar to the discontinuous flyback. The inductance can even be reduced to the point that the primary switch turns on with reverse 3-4 Isecondary Desired SR Gate Drive Light or Heavy Load Fig. 3. The synchronous CCM flyback remains continuous regardless of loading. Reducing the primary inductances, as shown in Table, increases the RHP zero location and can result in higher crossover frequencies. This table presents options for the primary inductance of the DSL power supply (refer to Table 1) based on the ratio between the peak-to-peak ripple in the current waveform to its average DC value. The inductance choices start with a relatively high inductance which might be typically chosen for the continuous mode of operation and then progress in octave steps. In this table, the inductance is varied to the point that the waveforms become those of a discontinuous flyback. The RHP zero moves from a low of 5 khz to over 50 khz. With the rule of thumb for crossover frequencies being one third the RHP

59 zero, the crossover frequency can be increased from under khz to well over 10 khz with the appropriate choice of inductor. The table also presents the output filter requirements as the inductance is varied. It is interesting to note that the increased ripple current does not significantly impact the value of the output capacitor until the levels of ripple current are quite high. This is due to the fact that the capacitor current does not change polarity during the 1-D state until the ratio of AC to DC current goes above 1.5 to 1. However, the maximum ESR decreases due to the higher ripple current present in the output capacitor. III. CIRCUIT STRESSES AND MAGNETIC DEFINITION A. Specifying the Transformer A CCM flyback design starts with a determination of the transformer requirements. The first task is picking turns ratios; this is accomplished by realizing that the volt seconds during the switch on time must equal the volt seconds during the off time. Neglecting the switch drops the expression is: V in D V o ( 1 D) N Switch drops can be added to the above expression to make them more accurate. Making the assumption of 45% maximum duty factor and solving at the minimum input voltage of 100 volts for the turns ratio yields: N D N 0.45 Vin ( 1 D) Vo 100 ( ) 3. 3 N 4 The maximum peak-to-peak ripple current occurs with maximum volt seconds applied to the transformer. This occurs when the output rectifier must conduct for the longest time. Primary inductance can be determined based on the minimum output power by first determining minimum duty at maximum input voltage by the expression: D Vo N Vin + Vo N D D 0.8 TABLE. REDUCING PRIMARY INDUCTANCE MOVES RHP ZERO TO HIGHER FREQUENCIES Primary Inductance (mh) Ratio Peak-to-Peak Ripple to Max Idc RHP Zero (khz) Required Capacitance ( F) Maximum ESR

60 With the minimum duty factor determined at high line, the maximum ripple current can be calculated by equating the input power to the product of duty factor times input voltage times the peak-to-peak ripple current divided by two or: Pmin I D Vin P I min D Vin 0.4 I,I Again this expression can be refined to include switch drops and power supply efficiency. Once the ripple current has been calculated and an operating frequency selected, the primary inductance is simply calculated. Operating frequency was picked as 166 khz because this represented a good trade between size and efficiency and it reduced the number of harmonics in the DSL operating frequencies. (6) Solving for primary inductance at 166 khz yields: I e L t t L e I D L Vinmax f I D L Vinmax f I 0.8 L , L 0.07 H This is used as the starting value of Table and was reduced to move the RHP zero out and to provide zero voltage switching at lighter loads. Table 3 presents a sample specification for the transformer. It identifies mode of operation and operating frequency. It also specifies a variation in the operating frequency as all control ICs are not perfect and a 30% variation over temperature and tolerances is not uncommon. The spec does not calculate detail RMS currents or exact turns ratio giving the magnetics designer some latitude in volts per turn selection. It also includes some physical requirements including maximum temperature rise and ambient temperature. TABLE 3. EXAMPLE TRANSFORMER SPECIFICATION Mode Continuous flyback Operating Frequency 150 khz to 00 khz Maximum Duty Factor 45% Input Voltage 100 VDC to 00 VDC Output V at.3 A, assume 0.1 V diode drop Output (Secondary Bias and Gate Drive) 5 V at 0.07 peak, A average Output 3 (Primary Bias) Pri referenced bias winding, 10 V at 0.01 A Approximate Turns Ratio, Primary to 3.3 V 4 to 1 Minimum Primary Inductance 6 mh Leakage Inductance Primary to Shorted Output µh Peak Current 0.11 A Maximum Height 0.75 inches Preferred Mounting SMT Maximum Ambient Temperature 85 o C Maximum Temperature Rise 45 o C, 1500 V isolation Safety Agency Requirements CSA, UL, etc. 3-6

61 B. Select the Primary FET The second step in the power stage design is selecting the primary switch. The voltage on the FET is equal to the maximum input voltage plus the reflected output voltage plus some margin for leakage inductance energy ringing with parasitic capacitances. At low line, the volt seconds on the transformer must balance so the reflected transformer voltage is determined by equating the on time and off time volt-second product or: ( 1 - D) D Vinmin Vreflected f f D Vreflected Vinmin (1 - D) 0.45 V reflected 100 (1-0.45) V reflected 8 V Some margin needs to be allowed for spiking during turn off. So with a 100 to 00 V input range and a 8 V stress, a 400 V FET should provide ample margin for the spiking. The next step is to determine the FET resistance which is an iterative process of selection, P-Spice analysis, and laboratory thermal measurements. A good starting point is to determine an allowable voltage drop during the conduction time and pick a part. This power supply requirement is extremely efficiency conscious so that the FET selection needs to trade switching losses versus conduction losses. If the assumption is made that the allowable efficiency loss is %, the optimal loss occurs when switching and conduction losses are equal. 1% conduction loss means the switch drop is 1% of the minimum input voltage or 1 V. One first needs to calculate the DC input current at low line which is: I dc V P max in(min) η 3.3V.3A I dc 100V 0.85 I dc A 3-7 Then solve for peak current using duty factor at low line and assuming a rectangular current wave form. Then the needed maximum FET resistance is calculated assuming 1-V switch drop. I I dc pk D I pk 0.45 I pk 0.A R fet 1 I R fet 5 This value of on-resistance for 400 V FETs is higher than commonly available so a slightly lower resistance part was chosen as the starting point. This part had an on resistance (R ds ) of 3.6 ohms, a total gate charge (Q g ) of 1 nc, gate to drain gate charge (Qgd) of 6.5 nc and an output capacitance (C oss ) of 34 pf. Conduction loss at low line is calculated as: pk P condloss Irms Rds P condloss D Ipk Rds Pcondloss P condloss Next, the available gate drive current is estimated from a typical controller (UCC809) data sheet using the fall time spec to discharge a 1 nf capacitor in 18 ns. V ig C T gate fall ig ig 0.667

62 This gate drive current is then used to calculate the turn off losses recognizing the fact that the FET conducts until the gate to drain charge is depleted. This turn off time (T to ) can be calculated using the gate drain capacitance divided by the drive current. The FET turns off with peak current and charges toward input voltage plus the reflected load voltage (or twice the input voltage in this case). The FET conducts during this period until the drain voltage quits increasing, at which time the current is ramped down rapidly. The switching loss per turn off cycle can be approximated by: Vin(min) Eto Tto Ipk Multiply this energy by the switching frequency to calculate loss and substituting to determine turn off time yields: P Ptoffloss P toffloss V T I in min to pk f Q ig gd I V pk in(min) f toffloss P toffloss 0.03 W A second switching loss occurs when the FET turns on. The FET output capacitance must be discharged and results in loss. Calculating the loss in the output capacitance is complicated by the fact that it is a combination of two non-linear capacitances. One can make a few simplifications to get to a first order solution of the loss. The first assumption is that the drain to source charge is significantly larger than the drain to gate charge. The second assumption is that the drain to source capacitance has the following relationship of a p- n junction: C jo C oss ( V ) 0. 5 Coss where V Coss is the voltage at which C oss is specified. With a little manipulation and the simplifying assumption of the FET off voltage equaling twice the low line input voltage, a closed form solution can be developed for this energy loss term as follows, first by determining energy loss (E) per cycle and then multiplying by switching frequency (f): Vin min E 0 0 E E PCossloss 3 3 V in min C VdV C V jo 0.5 VdV ( ) 1. 5 C jo V in min P Cossloss 170pF E f 1.5 ( 100V) 166kHz P Cossloss W This loss is particularly hard to measure as it is all internal to the FET, however, it s measurement can be combined with the turn off loss measurement. Energy delivered into the FET during turn-off is either dissipated in the channel or stored as drain to source charge. Without zero voltage switching of the FET, this stored energy is dissipated at turn on. So the measured turn off loss in reality is turn off loss plus C oss loss. The last significant loss mechanism is the reverse recovery-like loss characteristics of the synchronous rectifier. Estimates could be made based on its turn off times of the synchronous rectifiers but they would be grossly in error as circuit parasitics will, to a large point, determine these losses. The lab is probably the best place to evaluate these losses. 3-8

63 C. Select the Secondary FET The selection of the secondary FET involves calculation of gate-to-source and drain-to-source voltage stresses and then the determination of allowable on-resistance. The drain to source voltage is determined by the output voltage plus the reflected maximum input voltage or in this case, 3.3 volts plus 00 volts divided by 4 to one which equals 1 volts. A 40 volt was selected to provide significant voltage margin, however, a 0 volt device probably could have been made to work with better efficiency. The driving of the synchronous rectifier from the transformer requires a judicious selection of turns ratios and FET threshold and gate to source voltage rating. The FET must be fully enhanced for good efficiency but it must not be overstressed at maximum input voltage. A logic level device was picked for the rectifier. The transformer turns ratios were picked to provide approximately 3 volts of drive to enhance the synchronous rectifier. This sets the ratio between drive voltage and output voltage as 1-to-1. The maximum gate to source stress during the secondary off time can be calculated based on the turns ratio. With a 4-to-1 turns ratio and a 00 volt input, gate to source stress is 8.3 volts with almost 4 volts margin over a 1 volt gate to source rating. The final step involves determining the allowable FET on resistance. A good starting point is allowing a 0.1 volt drop on the rectifier during conduction. This contributes about a 3% reduction in efficiency while not overburdening the cost of the power supply. At this drop, 5-10 amp output currents can be accommodate without the need for heatsinks or specially cooling. The worst case peak current in the rectifier occurs at low line and can be related to the output current and duty factor as: I I o Rect -pk 1 - D.3 IRect -pk 0.55 I Rect -pk 4.A Allowing a 0.1 volt drop in the rectifier fixes the rectifier on resistance to 10 mohms. R Re ct I 0.1 Re ct pk R Rect 0.03 D. Designing the Output Filter The simplest filter is a capacitor and determining its specifications is fairly straight forward from circuit stresses and power supply requirements. The current waveform in the capacitor is mostly rectangular in shape with the full load current being drawn from the capacitors during the primary switch on time and sufficient charge to replenish the capacitors being deposited during the off time. The needed capacitor value can be determined from the maximum load current and maximum on time. The change in charge (I o D/f) and the maximum ripple voltage specification (V ripple 0.03 V) determines the needed capacitance by the formula: C I o D f V ripple 0.45 C.3A 166kHz 0.03V C 10 µf ESR is the second needed specification for the capacitor bank. This is calculated by realizing the total change in current results in a ripple voltage that is proportional to the ESR. Making the assumption that the current waveform is rectangular in shape allows the peak-to-peak current (I pp ) to be calculated as the average output current divided by (1-D). The required ESR is then obtained from the ripple requirement. I I o pp 1 D I pp

64 R esr V ripple I pp R esr 7x10-3 The two components of output ripple add in quadature so the total peak-to-peak ripple is the sum of the two. When picking a capacitor based on these calculations, a trade off will be needed to allocate ripple contributions of the two elements. This set of requirements for capacitors is typical of high performance capacitors used in laptop and servers and is much too expensive for commodity applications. A less expensive but more complicated filter is required to be cost competitive. A two stage filter as shown in Fig. 4 is definitely attractive. In this approach, the input capacitor C16 is selected by its ripple current rating and a significant voltage ripple of 300 mv to 500 mv is present. This relatively small amount of capacitance on the filter input is desirable to move the interactions with the remaining output filter components to as high of a frequency as possible. However, it was found in the modelling and later verified in the lab, that the high Q of the ceramic capacitor and its peaking effect with the output inductor caused an unacceptable current loop response. A larger aluminum electrolytic capacitor was therefore added for damping. Inductor L1 and capacitor C17 provide the final filter with approximately 0 db of attenuation at the switching frequency. C17 is chosen based on several constraints. It should be large enough that it is not significantly impacted by the addition of load capacitance. It also provides damping of the output filter so that a lossy (and cheap) capacitor is desirable. If it were high quality, two very high Q circuits would be formed leading to high output impedances and undesirable control characteristics. Transformer Output C16 µf 6.3 V + C µf L1 3.3 µh V V OUT C µf Fig. 4. Two-stage filter is less expensive than single section. The design process of the filter is to pick first an input capacitor based on ripple current which is calculated by: I I Cout Cout D 1 D I Cout.1A 0.5 I o.3 The next step involves the calculation of the ripple voltage based on the chosen ceramic capacitor to determine the ripple present on the filter s first stage. This is used for two things, to check that the damping capacitor ripple current is within its specification and to determine the remainder of filter. With the input ripple amplitude and the output ripple specification, the required attenuation can be calculated. The inductor value can then be determined based on required attenuation. As a final step, the filter response needs to be simulated to check for unacceptable peaking and suitable attenuation which will be discussed in the following paragraphs. 3-10

65 IV. CONTROL Closing the loop around the power stage is a three step process. The first step models the power stage, the second step adds isolation between the primary and the secondary, and the third step involves the overall loop compensation. As discussed earlier, judicious choice of the primary inductance and the use of synchronous rectification can move the RHP zero of the control to a relatively high frequency. For instance, in this example, with a primary inductance of the power transformer of 6 mh, the lowest frequency of the RHP zero is around 10 khz. To understand the loop analysis, a simple MathCad model of the power stage and modulator is used as shown in Fig. 5. For a more accurate model of the power stage and current control loop, refer to the Appendix 1. In the first step in this simplified modeling, the gain of the power stage or the current sense voltage to output current transfer characteristic is calculated by: K K Io Vsense ( ) K 7 ( 1 ) D N Ri 4 The next step adds the frequency dependent components to the power train. The RHP zero is calculated per the earlier expression and it is added to the current source expression as shown in Fig. 5. Next the output filter and load are added to finalize the simplified power train model. Two filters are considered, a simple, high quality capacitor design as shown in Figure 5 and the more complex two stage filter approach of Fig. 4. VCONTROL Iout K* (1-iw/wRHP) Vout C1 0 F R Fig. 5. Simplified power stage model. R1 9 Fig. 6 presents the results the results of the modeling efforts for a simple capacitive output filter. The output capacitor used is 0 µf with 7 milliohms of ESR and an output load resistance of ohms. This particular combination of capacitance and very low ESR may be difficult to find and will likely be expensive to implement. The DC gain remains flat to around 300 Hz where the output capacitor begins to shunt the load resistance. This pole is easily calculated from the combination of load resistance and output capacitor. The next inflection point is a zero that is determined by the ESR of the output capacitor and its capacitance around 100 khz. There is also a second zero around 4 khz, but this is due to the RHPZ and results in increasing gain and decreasing phase. Closing the gain around this system could be simply done with an integrator with a zero at 300 Hz and a gain of approximately 10 db at 8 khz. Gain - db 0-30 Gain 0-30 Phase - Degree -100 Phase k 10 k 100 k 1M f - Frequency - Hz Fig. 6. Modulator/power stage gain with simple filter.

66 Fig. 7 presents the more complicated modulator/power stage Bode response of the two stage filter of Fig. 4. DC gain is equal to the previous example; however, the design will be much more of a challenge to cross at a similar frequency. The control characteristic has a pole determined by the load resistance and the sum of the two output capacitors or: Pole1 1 ( C17 C19) π Rload + 1 Pole1 π ( 470uF + 470uF) Pole1 83 The gain falls until the impedance reaches the ESR zero of the electrolytic output capacitor at: 1 Zero1 π C16 ESRC16 1 Zero1 π 470uF 0.3 Zero1 1.1x10 3 Above 10 khz, two effects are evident, the first being the RHP zero previously discussed and the second caused by the resonance of the output inductor and the high quality ceramic capacitor. If the filter had no loss such as the electrolytic capacitor ESR, the magnitude of the peaking would make the design very bandwidth limited. However, by taking advantage of the inherent damping of the aluminum electrolytic, the amount of peaking can be controlled so a reasonable control bandwidth can be achieved. At high frequencies, we see a total of 70 of phase shift in the circuit; 90 from the ceramic capacitor, 90 from the L-R filter formed by the output inductor and the electrolytic capacitor ESR and 90 from the RHP zero. Gain - db Phase Gain k 10 k 100 k 1M f - Frequency - Hz Fig. 7. Reduced cost two section filter uses inexpensive aluminum electrolytic and ceramic capacitors. With the modulator/filter gain well in hand, the next step adds the error amplifier and isolating opto-coupler as shown in Fig. 8. This circuit uses a shunt regulator to compare the output voltage to a reference and to generate an error voltage. The difference between the error voltage and the output voltage generate a current in the opto-coupler that is used to set the peak current in the primary power switch. If the output voltage goes too high, the error amplifier output goes low to throttle back primary current. REF 4 3 R8 U4 H11A817 VOUT 1 R0 R3 U6 1 TLV431 8 C C0 R R6 Phase - Degree Fig. 8. This optocoupler connection yields a loop within a loop. 3-1

67 What is not very obvious in Fig. 8 is that there are two feedback paths, one through the error amplifier and another through the opto. If the output of the error amplifier were fixed and the output voltage went high, the current in the opto would build to throttle back the primary current just like the error amplifier loop. Therefore, the fixed error amplifier voltage acts as a reference to the inner control loop. This concept is shown in the simplified schematic of Fig. 9. So in reality, there are two loops to compensate: the opto inner loop and then the outer error amplifier loop; and one loop you don t compensate: the current loop. REF 4 U5 H11A817 1 VOUT R4 The strategy for compensating the inner loop is to provide some DC gain and then start rolling it off with a pole at 000 Hz to provide ample phase and gain margin. For the sake of simplicity, the following assumes that there are no gain variations in the opto and that it has sufficient bandwidth to not enter into the gain expressions. The final circuit design should review these simplifying assumptions. Fig. 10 shows the total open loop gain from adding an opto gain of 1.3 to the modulator/power stage gain of Fig. 7. This inner loop will have a cross over frequency of khz with ample phase and gain margins. Component count is relatively low since adding a pole to the network just requires a capacitor in parallel with the output of the optocoupler Gain R9 From error amp output which acts as a reference for the inner loop. Gain - db Phase Phase - Degree Simplified inner loop equivalent circuit VOUT k 10 k 100 k 1M f - Frequency - Hz Control Input R4 Current is proportional to I R4 C LOAD1 R ESR R LOAD Fig. 9. In the first loop, opto current is set by the output minus a reference. Fig. 10. Inner loop open loop gain. The next step closes the outer error amplifier loop. First the closed loop response of the inner loop is calculated as shown in Fig. 11. At low frequencies the gain is about 1 as would be expected due to the large gain in the open loop response. At frequencies approaching the cross over, the gain begins to fall. Since the inner loop had good phase margin, no peaking is evident. As in the open loop, at the high frequencies, the control loop exhibits a minus one slope and 70 of phase shift due to the second order filter poles and the RHP zero. 3-13

68 Gain - db Phase k 10 k 100 k 1M f - Frequency - Hz Gain Fig. 11. Inner loop closed loop gain With the benign control characteristics of the inner loop, the outer loop compensation is straight forward. The strategy is to use an integrator with a zero at near the desired cross over frequency. Fig. 1 provides the overall loop response. Cross over frequency of the outer loop is around 3 khz with about 45 of phase margin. Gain margin is about 8 db. Overall, the result is good in that the design has closed the loop around a RHP zero and a two section filter with a good bandwidth and text book stability Phase - Degree The proceeding analysis was accomplished using a mathematics tool rather than a circuit simulator such as P-Spice. The circuit of Fig. 13 can be used to perform the same analysis. There are two main subcircuits: a very simple equivalent for the TLV431 shut regulator and a very simplified power stage. In the left block, a voltage controlled current source with a gain of 1 is used to simulate the gain of the 431. Since this model is to develop an AC analysis of the control functions, the references and dividers are neglected. These could be added as well as frequency characteristics of the 431 and opto. The voltage feedback around the 431 turns its output characteristics from a current source to a voltage source. This signal is used to drive a current controlled current source and resistor which simulate the opto, modulator and power stage. The inner loop is obvious from this simplified circuit in that the current in R1, which is the opto current, is set by the difference between the output of the error amplifier and the output of the power supply. More detail can be added to this simple circuit to add the second order effects. First, the gain block, F1, can be devolved into a current controlled current source that simulates the opto and a current controlled current source that simulates the modulator/ power stage. Doing so will allow the insertion of the pole in the control characteristics of the inner loop. Gain - db Gain Phase Phase - Degree k 10 k 100 k 1M f - Frequency - Hz Fig. 1. Outer loop open loop gain shows good stability. 3-14

69 va V1 + 1 Vac 0 Vdc Simplified TL431 R4 C3 C R1 F1 C1 R5 G1 + vb F R R3 G Simplified Power Stage Model Fig.13. The second loop is formed with the TL431 driving the inner voltage loop. While not a portion of the actual circuit, the AC source, V1, plays an important role in the simulation. It can be used to measure the loop response of the outer loop by injecting a signal and measuring the return signal. Loop gain and phase can then be readily calculated from the ratios of Vout to Va. A similar method can be used with the inner loop. The error amplifier can be replaced with a fixed voltage connected between Vb and ground. The injection source would be placed between Vout and R1. The inner loop gain can then be measured as Vout divided by the injected voltage (on R1 side of the injection source). V. EXPERIMENTAL RESULTS Fig. 14 presents the schematic of the converter. This schematic includes the power stage, feedback circuits, controller and startup circuits. The power stage is the continuous flyback discussed in detail in the preceding sections A UCC809 controls the primary FET switch Q4 which drives power transformer T. This control IC was chosen for its simple features and low cost. It does not have the error amplifier and reference that many control ICs have but do not need for isolated power supplies and eliminating these subcircuits provides a cost savings. The transformer includes windings for primary energy storage (10 to 9), primary bias (8 to 7), secondary output power (3 to 5) and 3-15 secondary synchronous rectifier drive ( to 3). Q1 acts as the rectifier in the transformer secondary and drives the two section output filter provided by C16, L1, and C17. Output regulation is achieved by comparing the reference within U6 to the output voltage and feeding it back to the primary controller through the optocoupler. Compensation of the inner loop is accomplished with the parallel combination of R19 and C who provide a pole around 5 khz. The outer loop compensation` uses U6 as an operational amplifier with integrator response up until the zero introduced by the series combination of C0 and R. When power is first applied to the circuit comparator U3: A is used to provide an undervoltage function by holding down the softstart pin of the UCC809 controller. Once sufficient voltage is present on the input, D14 forward biases and the comparator releases the soft start pin. Q3 is used to provide start up voltage for the control IC but is disabled once the converter is up and running. The bias developed from the bootstrap winding reverse biases the base emitter junction shutting off current flow from the input and thus saving power that would otherwise be wasted with bleeder resistors. A small transformer is provided to couple an optional sync signal from the secondary back to the primary circuit.

70 Fig. 14. Prototype converter uses a UCC809 current mode controller. 3-16

71 Fig. 15 through 0 present some of the converter waveforms during full load operation at 100-V input. These waveforms provide good insight into the actual switching losses. Fig. 15 presents the primary switch drain to source voltage and source current waveforms. The voltage shows the continuous mode of operation with switching between the input voltage plus reflected load voltage to ground. The current waveform also demonstrates the continuous mode of operation with a significant current flow at turn on and a relatively sharp rate of rise of current during the on time. Also, a high current pulse is evident at device turn-on. This current has three parts; capacitive discharge of the power transformer plus board capacitance, gate drive current, and shoot through type losses from the synchronous rectifier. At these low power levels, the capacitive discharge term can be quite significant and resulted in a loss of several percent efficiency in one of the early prototypes of this supply. The excess capacitance was both in the power transformer and the multilayer PWB. A later design minimized the PWB capacitance by separating high voltage traces and minimizing the use of ground planes near these runs. Fig. 16 shows the very rapid turn on of the power switch at 10 ns per division. The drain voltage is collapsed in 0 ns and the high current spike in the source has almost disappeared in the same time frame. Fig. 17 shows the primary FET source current with no drain voltage present. It accounts for nearly 5% of the high current leading edge spike. The remainder is split between the capacitance and rectifier losses. V DS (100 V/Div.) I S (0.5 A/Div.) t - Time - 10 ns/dv Fig. 16. Low switching losses as synchronous FET is turned off. I S (0.5 A/Div.) V DS (100 V/Div.) I S (0.5 A/Div.) t - Time - 1 s/div Fig. 15. Power switch current and voltage waveforms. t - Time - 10 ns/div Fig. 17. Significant portion of source current is gate drive. 3-17

72 To further evaluate losses in the rectifier, secondary waveforms were measured. Fig. 18 presents the transformer output voltage during a switching period. The lower magnitude trace is the voltage that is rectified to provide the output power while the larger trace is the gate voltage to the secondary FET. Its gate-to-source voltage is simply the difference between the two traces. The output FET is enhanced with about 5 V of gateto-source voltage during conduction and reversed biased with about 5 V of negative drive. V G (5 V/Div.) V S (5 V/Div.) V G (5 V/Div.) V S (5 V/Div.) t - Time - 1 s Fig. 18. Synchronous FET voltage waveforms. Fig. 19 and 0 present expansions of the transformer voltage waveforms. Fig. 19 shows the turn off of the synchronous rectifier at 0 ns per division. Before the gate voltage reaches zero, the synchronous FET remains turned on and connects the 3.3-V transformer winding to the output voltage. When the primary FET turns on, the gate drive waveform collapses to zero volts in about 50 ns at which time the synchronous FET turns off. Then, the power winding on the transformer collapses and the voltage reverses. During the time when the synchronous is turning off, leakage inductance is the main limiter of current flow in the power transformer, however, based on the primary current waveforms, this is not a significant loss due to the short shoot through times and limited amount of current. t - Time - 0 ms/div Fig. 19. Synchronous FET is turned off in 50 nanoseconds. Fig. 0 shows the transformer waveforms at turn on. This is a much more docile edge. Gate and drain voltage rise gradually and turn on of the synchronous FET is accomplished smoothly. These traces do not show the high frequency content that occurs at turn off where the primary FET and synchronous rectifiers are trying to push currents in opposite directions. V S (5 V/Div.) V G (5 V/Div.) t - Time - 0 ms/div Fig. 0. The synchronous FET is turned on quickly and smoothly. 3-18

73 Fig. 1 presents efficiency of the converter versus output current and input voltage. At 100 input voltage, this 3.3 V, 7 watt output power supply reaches almost 90% efficiency and losses are dominated by losses associated with high currents. At the higher input voltages, efficiency is somewhat degraded due to switching losses from the active components as well as losses due to circuit parasitic capacitances. In this particular application, efficiency was critical at the low input voltages so the degradation at the higher voltages was acceptable. To gauge the effectiveness of the synchronous rectifier, a Schottky was substituted and it resulted in about a 4% efficiency loss. Efficiency - % V IN 00 V IN I OUT - Output Current - A Fig. 1. Efficiency is high for this low power, offline design. TABLE 4. LOSS BUDGET SUMMARY SHOWS GOOD CORRELATION WITH EFFICIENCY MEASUREMENTS Loss Element 100 V Loss 00 V Loss T Leakage Q4 Turn On T Capacitance Q1 Conduction Q4 Coss Q4 Conduction Q4 Turn Off R17 Conduction U T Core Q1 Gate C19 Conduction T Conduction R11, R7, Total Measured Loss Difference Table 4 presents a detail accounting of the various losses within the power supply. With an output of just 6.6 watts of power, every milliwatt of loss is important in maximizing efficiency. 75% of the loss is in just 4 elements and they represent the key to further efficiency improvements. The transformer has the biggest effect on overall efficiency in two areas, the first is the losses as the leakage inductance is discharged each switching interval. The second is in its interwinding capacitance that is also discharged each switching interval. While the leakage inductance of the transformer was only 80 µh referred to the primary, this amount to 0.5 watts of dissipation. And with the capacitance of the transformer of 50 pf, this introduced about 0.16 watts of the total loss. Unfortunately, reducing one of these parasitic elements usually increases the other if the core size and primary inductance is maintainted. If cost were not an aspect in the design of the power supply, an increase in core size might allow a reduction in both of these loss elements. The other alternative is one that we eluded to earlier. The power supply can be run with even less 3-19

74 primary inductance on the transformer which can lead to both reduced leakage and reduced capacitance. The next element to address to improve the efficiency is the turn on loss of the primary FET. Since this is a self driven design, there is some turn-on losses caused by the secondary FET shorting the transformer. A better drive circuit could reduce this loss by turning the secondary FET off prior to primary turn on. This could be done with an additional drive transformer and delay circuits or could be accomplished with an adaptive circuit. The last significant loss element is the conduction loss of the secondary FET. This can be improved with a lower resistance part with additional cost. So with additional cost, this design can be pushed over 90% efficiency, however, the design was implemented with the lower cost components and circuitry due to high cost pressures. Fig. through 4 present various loop measurements and they show good correlation with the analysis presented. Fig. is the open loop gain from the input of the opto to the output of the power supply open loop. To make this measurement, the opto was disconnected from the output and its anode was connected to a lab supply through a 750 ohm resistor while grounding the cathode. The opto was then driven with a signal source, and the transfer function from the opto to the output voltage was measured. Fig. 3 shows the closed loop response of the opto. It was made by connecting the opto through a 750 ohm resistor to the power supply output and then measuring the response from the opto input to the power supply output. Fig. 4 shows overall gain of the outer control loop. It was made by connecting the TLV431A and its compensation components to the opto input and then injecting an AC signal between the power supply output and the TLV431 circuit input. All measurements were made with a Venable Network Analysis System. Gain - db Gain f - Frequency - Hz Phase Hz 100 Hz 1 khz 10 khz 100 khz Fig.. Opto voltage to output voltage response (corresponds to Fig. 10). Gain - db Phase Gain Hz 100 Hz 1 khz 10 khz 100 khz f - Frequency - Hz Fig. 3. Closed inner loop transfer (corresponds to Fig. 11). Phase - Degree Phase - Degree 3-0

75 Gain - db Gain f - Frequency - Hz Phase 10 Hz 100 Hz 1 khz 10 khz 100 khz Fig. 4. Overall loop open loop response (corresponds to Fig. 1). VI. SUMMARY The design procedure for a low power continuous flyback converter with synchronous rectifiers has been presented. The design was based on the requirements of low cost and high efficiency as required by line powered DSL and cable modem customer premise equipment. Circuit stress calculations and magnetic requirements definitions have been outlined. Control loop analysis of a nested loop and a two section filter has been presented. Finally, all calculations have been verified with lab results from a prototype converter. Phase - Degree VII. REFERENCES [1] Dinwoodie, Lisa; Design Review, Isolated 50 Watt Flyback Converter Using the UCC3809 Primary Side Controller, Unitrode Application Note U-165, Texas Instruments Power Supply Control Products Data Book [] Jovanovic, Zhang; Lee; Design Considerations and Performance Evaluations of Synchronous Rectification in Flyback Converters, in IEEE Transactions on Power Electronics, Volume 13, Number 3, May 1998 [3] Ridley, Ray; Designers Series, Part V, Current-Mode Control Modeling, in Switching Power Magazine, 001 [4] Vatche, Vorperian; Simplified Analysis of PWM Converters Using Model of PWM Switch Part 1: Continuous Conduction Mode, IEEE trans. on Aerospace and Electronic Systems, Volume 6, Number 3, May [5] Ridley, Ray; A New Small-Signal Model For Current Mode Control, Ph. D. Dissertation, Virginia Polytechnic Institute and State University, Blacksburg, VA, November [6] Betten, John; Day, Michael, Optimizing the Switching Frequency of ADSL Power Supplies, in Communications System Design, June

76 APPENDIX. DERIVATION OF CURRENT LOOP CONTROL CHARACTERISTICS The flyback converter can be modeled as a buck boost converter when the primary circuit is reflected to the secondary side as shown in Fig. 1. To do so requires reflecting input voltage and transformer magnetizing inductance through the transformer turns ratio. Vi N 1 R ESR C V O R Vi R ESR V O L R C Fig. 1. The flyback can be simplified to a buck-boost converter for analysis. The next step in the process is to add the simplified average PWM switch model developed by Vorperian and the model extension to current mode developed by Ridley Engineering. Fig. shows the small signal equivalent circuit for the current mode controlled flyback converter. This figure shows the power stage, as well as the gain blocks for the current loop within the power stage. Fm, the modulator gain, is calculated as: Fm Vin L 1 Fs + ExtRamp where Fs is the switching frequency and ExtRamp is the value of externally added ramp. He(s) models the instability of the current loop as the duty factor approaches 50%. Ridley Engineering has numerous references on the He(s) term, if a person wants to include the complexity of this term in their analysis. Finally, Ri models the conversion of the inductor current to a sense voltage. 3-

77 Vap d^ D a Icd^ + p V O R ESR VI L c Fm d^ C R Ri He(s) Fig.. Vorperian buck-boost equivalent model. Using the small signal model of Fig., the open loop control to output transfer can be derived to be the following. This is the transfer function that would characterize voltage mode control. The transfer function shows an ESR zero (ωz1), a right half plane zero (ωz), and double pole at ωo. Gv(s) s z1 1+ vˆo(s) Kv ω dˆ(s) 1+ ω s 1 ωz s + ωo s oq 1 ωz1 ResrC ωz Kv ( D) R 1 DL Vi ( 1 D) 1 D ωo LC Q ( 1 ) Also, using the small signal model of Fig., the open loop control to inductor current transfer function is derived to be the following. This transfer function is needed to complete the control to output transfer function for current mode control. D R L / C 3-3

78 î (s) Gi(s) dˆ(s) s 1+ p Ki ω s s 1+ + ωoq ωo 1+ D ωp RC Ki Vo RD 1 ( 1+ D) ( D) ^ vc Σ Fm d^ Gv(s) vo ^ Ri He(s) Gi(s) Fig. 3. Control loop block diagram showing current loop. With these two gain blocks calculated, one can use the block diagram of Fig. 3 to calculate or simulate the gain from the control to output voltage transfer function. The solution with the current loop closed is: Vˆ o FmGV(s) Vˆ c 1+ FmGI(s)RiHe(s) From the transfer function expression, it can be observed that when the current loop has large gain, the double poles of the open loop control to output transfer function, Gv(s), and the open loop control to inductor current transfer function, Gi(s), almost cancel and results in the following approximate transfer function. T(s) Vˆ o Vˆ c s s 1+ 1 z1 z K ω ω s 1+ ωp By making the assumption that current loop has high gain at DC, K can be simply calculated as: ViR K ( Vi + Vo)Ri Note that in practice the current sense resistor will need to be reflected back through the transformer turns ratio. 3-4

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80 Transformer and Inductor Design for Optimum Circuit Performance Lloyd H. Dixon ABSTRACT The energy absorbed and released by transformer leakage inductances during each switching period usually ends up as loss, thus impairing switching power supply efficiency. Even when much of this energy is recycled and recovered through the use of resonant or active clamping techniques, leakage inductance remains as the main factor in cross-regulation errors among multiple outputs, a problem that cannot be eliminated or reduced with a single control loop. This topic discusses how proper thinking about the causes and effects of leakage inductance can result in optimized transformer design with minimum parasitic inductances and ac winding losses, as well as establishing the winding hierarchy to reduce cross-regulation errors. Also discussed are ways to use reluctance modeling and duality principles to develop the transformer equivalent electrical circuit model which provides provide the best visibility of the effects of parasitic inductances. Examples are presented of forward and flyback transformer applications with multiple outputs. I. INTRODUCTION This topic builds upon and applies the procedures presented in the TI/Unitrode Magnetics Design Handbook, presented to attendees of the 001 Power Supply Design Seminar. To obtain a copy of the Magnetics Design Handbook, see Reference [1]. The word transformer is often used in this paper to refer generically to both transformers and inductors. The process for transformer design and optimization could consist of the following steps: 1. Perform a tentative transformer design, on paper, based on the predefined requirements of the circuit application.. Develop the electrical equivalent circuit model based on the physical structure and dimensions of the tentative transformer design. Each element of the physically-based circuit model will correlate with a specific physical region or element of the transformer. 3. Simulate circuit operation in the time domain, using the transformer model operated in its circuit application. Based on the understanding gained from observed effects, make appropriate modifications to the transformer circuit model to obtain improved performance. Even without computer simulation, common-sense evaluation of the physically-based transformer model in its circuit application can provide great insight into ways to manipulate the transformer structure to obtain improved circuit performance. 4. Implement the desired improvements, using the simple relationships between elements of the circuit model (such as leakage inductance) with the underlying physical parameters and dimensions of the transformer structure. 5. Before committing to the planned approach, the designer can explore alternative circuit topologies or operating frequencies, using simulation. 6. The final step is to build a physical prototype of the refined paper design, and evaluate the prototype device in the circuit application. II. HYPOTHETICAL RESISTIVE SOURCE Imagine a power distribution hub with a pair of input terminals internally connected to three pairs of output terminals. Each output pair is intended to deliver power to a high-power load. Resistances of the conductors between the terminals are significant, resulting in power loss, 4-1

81 poor load regulation and impaired crossregulation. Assuming the circuit configuration within the distribution hub cannot be changed, but circuit values can be changed, losses can be minimized and cross regulation improved by: 1. Reducing resistances as much as possible.. Selecting the loads attached to each pair of terminals in the most intelligent manner. In order to achieve this goal, a knowledge of the circuit diagram is essential. In this example, the terminals are connected in a series string as shown in Fig. 1. INPUT A R R R B C D Fig. 1. Resistive source. The resistance of the conductors between terminal pairs is defined by the following relationship: l R σ A Where A and l are the conductor crosssection area and length, and σ is the conductivity. If the distance between terminal pairs is fixed, conductor length cannot be reduced, but resistances can be minimized by increasing conductor area and by using a material with high conductivity, such as silver or copper. Taking note of the circuit configuration in Fig. 1, it is obvious that to minimize power loss within the hub, the highest current load should be connected to the B terminals, closest to the input, with progressively smaller loads connected to the C and D terminal pairs. But in order to minimize cross regulation errors, the load with the greatest current change should be connected to the B terminals. (If the load with the greatest current does not also have the greatest change, then these goals conflict and a judicious decision must be made.) It will be shown that transformer design optimization can follow this same logical pattern. With knowledge of the electrical equivalent circuit and its relationship to the underlying physical parameters of the transformer, parasitic inductances can be minimized and winding sequences arranged for optimum results. III. TRANSFORMER IN-CIRCUIT PERFORMANCE A. The Effects of Leakage Inductance Transformer leakage inductances are usually the main factor in poor load regulation and poor cross regulation with multiple outputs. Leakage inductances usually have a much greater effect than all circuit resistances combined: series resistance of transformers and filter inductors, rectifier dynamic resistance, switch R DSON, and circuit wiring. Leakage inductance also seriously impairs power supply efficiency when leakage inductance energy is dumped into dissipative snubbers or clamps. [] How does an ideal lossless inductor, with zero resistance, affect DC load regulation, and cause losses? In a linear circuit application, an ideal inductor has no effect on load regulation or cross-regulation. But in a switching power supply, currents in the windings are switched and discontinuous. Leakage inductance is a circuit representation of energy stored physically between the windings of the transformer. When the primary-side power switch turns on, energy must be provided to the leakage inductance field between the windings in order for the transfer of current between windings to take place. When the primary switch turns off, the discharge of this energy results in a large reversal of voltage which appears across the switch. This voltage must be suitably clamped to avoid damaging the switch. The leakage inductance energy is thus dumped into the clamp, resulting in loss. The time required to provide and remove energy from the leakage inductance field causes a delay in the current transition between primary and secondary. The transition time is directly proportional to load current. It effectively reduces the pulse width on the secondary side as a function of load current, thus impairing load regulation. 4-

82 It is worth pointing out again that leakage inductance is usually the main cause of poor load regulation. Likewise, with multiple outputs, leakage inductance between secondary windings is the main cause of poor cross regulation. A L L D1 D B I OUT Fig.. Forward converter circuit model. I D V A V B I D1 Fig. a. Waveforms. Fig. shows the effect of leakage inductance between primary and secondary in a forward converter with a single output. The leakage inductance could be referred either to the primary or the secondary it is shown here in series with the secondary. Before the primary side power switch is turned on, the output filter inductor current (which is essentially constant during the switching transition) flows through the freewheeling diode D, and the current through the series leakage inductance and D1 is zero. When the switch is turned on, current through the leakage inductance L L cannot change instantaneously, but rises at a rate: V L A in / di dt L V nl L (1) 4-3 Where n is the primary/secondary turns ratio. This rate of current rise determines the transition time for the current to transfer completely from the shunt freewheeling diode to the leakage inductance and to the primary side. During this entire transition, the freewheeling diode remains in the forward direction, conducting an everdecreasing current. This causes the voltage at the input of the filter inductor to remain at zero throughout the transition. Thus, the leading edge of the voltage pulse applied to the output filter inductor is delayed by an amount equal to the transition time, which reduces the average voltage delivered to the output. The turn-on transition delay and the resulting reduction in output voltage are directly proportional to the load current flowing through the filter inductor: t D I V out L L secondary () When the power switch turns off, current through the leakage inductance falls at a rate: Vclamp n di dt LL (3) However, at the very beginning of the turn off transition, the initial reduction of current through the leakage inductance forces the remainder of the output filter inductor current through the freewheeling diode. The freewheeling diode immediately conducts, and the voltage at the input of the filter inductor is forced to zero without any transition delay. Thus, there is a turn-on delay, but no turn-off delay the leakage inductance causes a reduction of the pulse width applied to the filter inductor input. The turn-on transition time and corresponding pulse width reduction is proportional to load current. If the duty cycle of the power switch is not changed, the output voltage will drop by an amount proportional to load current. The leakage inductance behaves like a lossless series resistance. However, during the turn off transition, all of the energy stored in the leakage inductance is delivered into the clamp. With a dissipative clamp, this becomes power loss. Thus, loss does not occur in the inductor, but it causes loss by dumping its energy into the

83 clamp. Even with a non-dissipative clamp, the leakage inductance causes power to be diverted away from the output. The control loop, sensing the output voltage reduction, increases the duty cycle to provide eventual correction, depending upon the control loop response time. However, the pulse width reduction caused by the turn-on transition reduces the available duty cycle range. In a forward converter, for example, the duty cycle of the voltage waveform applied to the transformer primary is often limited to 50 percent, in order to allow time for transformer core reset. The turn on transition time will then reduce the maximum duty cycle of the pulse applied to the filter inductor input to something less than 50 percent. Peak current values must be correspondingly increased. To obtain the desired averaged output voltage with a shorter pulse width, a higher peak secondary voltage is required. This is achieved by an adjustment of the transformer turns ratio. B. Multiple Secondary Windings When there are more than two windings in the transformer, a more serious situation occurs. Fig. 3 shows a simplified equivalent circuit of a forward converter with two outputs, using a transformer with two secondaries. In order to simplify the equivalent circuit, the assumption is made that the two secondaries have equal number of turns. By eliminating the turns ratio between the secondaries, the two secondaries in the equivalent circuit can be directly interconnected, except for the leakage inductance intervening between the actual windings. (Later, a normalization process will be discussed which enables secondaries with different numbers of turns to be treated in a similar manner.) In Fig. 3, leakage inductance values appear in their proper locations in the equivalent circuit. To further simplify the equivalent circuit, the output filters and loads have been replaced by equivalent constant-current loads. L P1 represents the leakage inductance energy existing in the field between the primary and adjacent secondary #1. L 1 represents the additional leakage inductance energy between secondaries 1 and. Leakage inductance between the secondaries causes cross-regulation or tracking errors between the outputs that cannot be corrected by the control loop. If the loop is closed on output #1, it will be well regulated, but increased load on output # will cause its voltage to decline. Conversely, if the loop is closed on output #, it will be well regulated, but an increase in load on output # will cause the voltage on output #1 to rise. Fig. 3a shows the resulting waveforms. (The validity of the model and resulting waveshapes can be observed in an actual power supply at the filter inductor inputs. A L P1 B B' D1A D1B L 1 I O1 Fig 3. Two-output equivalent circuit. Fig. 3a. Waveforms. C DA DB Before the primary-side power switch turns on, free-wheeling diodes D1 B and D B are conducting output currents I O1 and I O. When the power switch turns on, voltage is applied across L P1, initiating current transition t 1, just as in the previous example of Fig.. Current through D1 A I O 4-4

84 increases, while D1 B current decreases. Since D1 A and D1 B are both conducting throughout transition time t 1, voltages V B and V B are essentially zero. Therefore, the voltage across L 1 is zero, so that current through L 1 and D A remain at zero throughout t 1. At the end of t 1, when the current through L P1 and D1 A has risen to output current I O1, current through D1 B reaches zero. This permits the voltage at B and B to rise, applying voltage to L 1. This begins the second transition, t. During t, D A and D B are both conducting, and V C remains at zero. Note that transition time t is a function of V A across L P1 and L 1 in series. IO ( LP1+ L1) t VA (4) During t, voltage at B and B cannot rise to equal V A, because B is at the mid-point of inductive divider L P1 and L 1. Thus, full voltage is not applied to Output 1 filter inductor (at point B) until the end of both transitions. As shown in Fig. 3a, the larger-hatched area shows the volt-seconds per switching period that is subtracted from the input pulse applied to Output 1. The smaller hatched area shows the additional volt-seconds per switching period subtracted from Output, which represents crossregulation error. Computer simulation using the equivalent circuit model can provide detailed information regarding circuit performance. However, valuable insight can be gained just by a simple understanding of how the equivalent circuit functions: The equivalent circuit shows that Output 1 load current results in energy stored only in L P1. A change in Output 1 current does not affect cross-regulation, because L 1 is not involved. But Output current results in stored energy in both L P1 and L 1, and affects Output 1 regulation and cross-regulation. This holds true even if the number of turns in the secondary windings are not equal. The highest power load always translates into the greatest Ampere-turns. Therefore, to minimize the total energy stored in the leakage inductances (which usually ends up as loss), the highest power load (greatest Ampere-turns) should always be the closest coupled to the primary, in this case secondary #1. But if it is more important to achieve good cross regulation, then the load with the greatest power variation should be closest to the primary. If secondary # has a constant load, there will be no dynamic cross-regulation error between outputs 1 and, even if the load on secondary #1 has large variation, but if the location of the secondaries is interchanged, there will then be significant cross regulation error. Thus it can be seen that it is not only important to design the transformer with minimum leakage inductance values, the sequence of the windings is also very important, depending upon whether the goal is to achieve minimum loss or minimum cross-regulation error. IV. MODELING THE TRANSFORMER As discussed earlier, a proper electrical equivalent circuit model of a transformer (or inductor) permits circuit simulation of power supply performance, revealing problems and performance limitations attributable to the transformer. In addition, if the electrical parameters of the model can be directly correlated with the physical structure, then simulation results or simple common-sense circuit evaluation can show how to modify the transformer structure to improve circuit performance. The traditional "black box" method for defining the transformer electrical model involves measuring the impedance of each winding, with other windings open and shortcircuited. This method assumes no knowledge of the internal transformer structure, not even the turns ratio. (Much like the blind men attempting to define an elephant by feeling different parts of its anatomy.) Actually, if the measurements are sufficiently accurate, this method can result in a model which will produce the correct simulation results. However, it is unlikely that the electrical parameters of such a model will directly correlate with physical properties of the transformer. Thus a model derived in this manner will provide little 4-5

85 insight, and probably much confusion, regarding transformer improvement. This is because there are an infinite number of possible circuit models for a specific transformer, all of which are electrically equivalent. Each of these theoretically possible models has different impedance values and correspondingly different turns ratios, and each will produce the same, presumably correct, simulation results. However, only one of these possible models has electrical parameters which correlate directly with physical parameters of the transformer structure. In this physically-based model, the turns ratios are the same as the actual transformer turns ratios. All of the other electrically equivalent models are abstractions. [3] The Thevenin equivalent circuit of a "black box" circuit source is another example of an abstraction that provides proper results with circuit analysis, but provides little insight into the inner workings of the "black box" which would be necessary if it was desired to improve or modify the source circuitry. The traditional "black box" method for defining the transformer model assumes a symmetrical bilateral coupling coefficient between each pair of windings, i.e.: k1 k1 k. This assumption (which is as reasonable any other if the inner workings are not known) results in a model consisting of a symmetrical tee or pi network, coupled with an ideal transformer whose turns ratio is unlikely to equal the actual transformer turns ratio. This is because in the actual transformer, the flux coupling coefficient k1 is unlikely to equal k1, and the corresponding network is therefore unlikely to be symmetrical. However, If the actual turns ratio is known, the physically-based model could then be derived from measured impedance values by using the actual transformer turns ratios in the calculations. But with high frequency SMPS transformers, it is often difficult to achieve sufficiently accurate measurements. For example, it is difficult to distinguish the short-circuit impedance of a one or two turn secondary from the inductance of the external leads. Even if the measurements are sufficiently accurate, any method based on measurement obviously requires building a prototype transformer in order to obtain the required values. Fig. 4. Four randomly located windings. The author prefers to develop the electrical equivalent circuit model from simple calculations based upon the physical parameters of the transformer, rather than by impedance measurements. This method, which will be discussed in a later section, permits simulation to be accomplished in the early phase of transformer design, using values calculated from the physical parameters of a proposed design, thus not requiring prototype construction and measurement. Another serious problem is that in a transformer with more than two windings, the abstract theoretical model becomes much more complex. In Fig. 4, for example, with four windings arranged as shown and with no magnetic core, each winding cross-couples directly and independently to every other winding. The resulting complex and confusing equivalent circuit is usually the result of the "black box" measurement method which assumes no knowledge of the actual physical structure. Fortunately, in most transformer structures with either helical or planar windings, the physically-based circuit model is quite simple. For example, in the helical transformer structure shown in cross-section in Fig. 5, flux lines cannot independently link primary winding P to secondary without also linking to 1, and flux linking P to 3 must also link to 1 and. The circuit model for this configuration is shown in Fig. 5a. All windings are normalized to one turn, in order to eliminate the complexity introduced by turns ratios. (Each winding X would then be connected to its external circuit through an ideal dc-dc transformer with 1:N X turns ratio.) 4-6

86 The three series inductors are leakage inductances, correlating directly with energy stored in the three regions between windings P 1, 1, and 3. The two shunt inductors are magnetizing inductances, representing the core center leg and the combined outer legs, respectively. Magnetizing inductance represents energy stored in the core, and is shared, or mutual, with all windings. If the magnetizing inductances are much greater than the leakage inductance values (which is usually the case), they can be combined into a single mutual inductance, located across the terminals of any winding (usually the primary as shown in Fig. 5b) without significantly affecting simulation results. 3 1 P P 1 3 Fig. 5. Four concentric helical windings. L L1 L L L L3 P L M1 1 L M 3 V. DEFINING THE CIRCUIT MODEL A. Based on Physical Parameters/Dimensions The first step in defining the electrical circuit model of transformer without making electrical measurements is to define the magnetic equivalent circuit, often called a reluctance diagram. [4] Reluctance, in a magnetic circuit, is the counterpart of resistance in an electrical circuit. When an electrical force (voltage) is applied, current flow is determined by circuit resistance. When a magnetic force (Ampere-turns) is applied to a magnetic element (such as a section of the core, or an air gap), the amount of flux is determined by the reluctance of that magnetic element. However, there the similarity ends resistance is a power dissipating element, whereas reluctance is an energy storage element. B. The Reluctance Diagram Fig. 6 is the reluctance diagram of the transformer structure shown in Fig. 5. Reluctance values can be defined for each element of the transformer structure, according to the length, cross-section area, and permeability of that element, in the SI system of units: R l A-T/Weber (5) µ A Where length and area are expressed in meters, and permeability µ equals: 7 µ µ 0µ 4 π 10 µ (6) r µ 0 4π 10-7 (permeability of free space) µ r relative permeability r Fig 5a. Electrical equivalent circuit model. L L1 L L L L3 ΦP - + N P I P Φ1 - + N 1 I 1 Φ - + N I Φ3 - + N 3 I 3 R C R P1 R 1 R 3 R O P L M 1 3 RELUCTANCE VALUES x 10 6 Fig. 5b. Modified electrical model. 4-7 Fig. 6. Reluctance diagram.

87 The transformer of Fig. 5 has 4 helical windings arranged concentrically around the centerleg of a ferrite magnetic core. Voltage applied to primary winding P causes the flux to change at a precise rate determined by Faraday's Law: dφ E (7) dt N Thus the total change in flux within the winding is precisely determined by the applied Volts/turn, integrated over time. Most of this flux passes through the low reluctance outer legs to complete its closed-loop path. Thus, the changing flux links to all of the other windings which will then (according to Faraday's Law) have the same induced Volts/turn as the primary. The core has a small but finite reluctance, thus requiring a small magnetic force to push the flux dictated by Faraday s Law through the core. F Φ R N I (8) Magnetic force equates directly with Ampereturns in the SI system of units. Thus a small magnetizing current, I m, is required in the primary. Because the reluctance of the outer legs is not zero, and the reluctance of the regions between each of the windings is not infinite, a small amount of the flux generated by the primary will flow through the regions between the windings. This is called leakage flux, one of the components of the leakage inductance field between the windings. Leakage inductance energy is not coupled to all windings only to those windings linked by the flux lines. When loads are applied to the secondaries, the resulting secondary Ampere-turns are offset by equal and opposite Ampere-turns in the primary. Thus, along the flux path through the core which encompasses all windings, the magnetic force created by these load-related currents cancels. The magnetic force through the core and its associated magnetizing current are not changed by load current. There is one place where the forces associated with load current do not cancel that is between the windings. In those locations, the load related currents result in P m greatly increased leakage inductance energy between the windings. All of the effects discussed above can be observed and evaluated with the reluctance diagram of Fig. 6. C. Creating the Reluctance Diagram The reluctance diagram is created by calculating the reluctance of each significant element in the transformer structure. Each winding appears in the reluctance diagram as a source. The reluctance diagram should be no more complex than necessary each element of the reluctance diagram becomes an element in the electrical equivalent circuit. Using equation (5) to calculate the reluctance of the centerleg, the ferrite cross-section area and centerleg length are available from the core datasheet. (Dimensions must be converted to meters for use in the SI system.) Absolute permeability, µ 0, equals 4π Relative permeability, µ r, for ferrite (typically 3000) is also available from the datasheet. With an E-E core, centerleg flux divides into two equal portions through the outer legs encircling the windings. The two outer legs can be considered as a single reluctance element with an area twice that of one leg, in order to simplify the reluctance diagram. In a flyback transformer or filter inductor, an air gap would appear as a separate reluctance in the physical location where it occurs, usually in series with the center leg reluctance. The air gap reluctance has great importance in an inductor or flyback transformer, because this is where the required energy is stored. The reluctance of each of the three regions between the windings is of key importance the fields in these regions translate into leakage inductance. Relative permeability equals 1.0 in these non-magnetic regions between the windings as well as in the copper conductors. Just as the windings are cylindrical in form, the leakage inductance field regions between the windings are also cylindrical. The length of these cylindrical fields is the distance across the window in the core. (Where the windings emerge from the core, the leakage inductance field must stretch and bend to reach the core, so the length 4-8

88 of the field in these regions is somewhat greater, increasing the reluctance by 5 or 10 percent.) The cross-section area of these cylindrical regions equals the cylindrical wall thickness multiplied by the circumference. The wall thickness corresponds to the separation between adjacent windings, plus approximately one-third of the thickness of the windings themselves. (The field extends into the windings.) The mean length per turn (MLT) taken from the core datasheet can be used as the circumference of these cylindrical regions. The regions between the primary and the core center leg and between secondary 3 and the outer legs are simply high reluctances in parallel with the low reluctance ferrite, and can be neglected. Bear in mind that in this process, super accuracy is not very important. The object is to obtain an understanding in order to achieve improvement. One additional consideration: Magnetic force is circulatory in nature, distributed around each winding whose Ampere-turns create the force, in the same manner that a paddle-wheel operating horizontally in a liquid provides a distributed force which would cause the liquid to circulate. (Mathematically, this would be described as curl.) The circulatory force results in a closed circulatory path for the resulting flux. However, in the reluctance diagram, the magnetic forces associated with each winding are inserted as discrete elements in locations that result in the same circulatory pattern as the actual distributed force. This requires using a little judgment. D. The Electrical Equivalent Circuit C. Cherry, in a 1949 paper, showed that the electrical equivalent circuit is the topological dual of the reluctance model. This is described in more detail in the referenced Magnetics Design Handbook. [4] Through this simple process, the reluctance diagram of Fig. 6 is transformed into the electrical equivalent circuit of Fig. 5a and 5b. In the duality process as described by Cherry, and demonstrated in Fig. 7a and 7b for a simple inductor, each node in the reluctance diagram becomes a loop, or mesh, in the electrical equivalent circuit, while each loop in the reluctance diagram becomes an electrical node. Fig. 7a. Inductor reluctance diagram. Fig. 7b. Electrical dual. As shown in Fig. 7a, a node is placed at the center of each loop in the reluctance diagram. (Topologically, the entire outside of the circuit is also considered to be a loop.) Dash lines are drawn from node to node through each intervening element. The dash lines represent the electrical equivalent circuit. All of the series elements in the reluctance diagram become parallel elements in the electrical dual, and all the parallel elements are in series in the dual. Circuit elements are also transformed. Ampere-turns representing magnetic force in the reluctance diagram are converted into terminal pairs in the electrical equivalent circuit. Reluctances become their reciprocals permeances. Permeance is actually inductance as seen through a 1-turn winding: P 1 µ A R l (9) 4-9

89 When the electrical equivalent circuit has been established, as in Fig. 7b, all of the actual permeance values are quantified using equation (9), based on the length, area, and permeability of the physical region from which each permeance is derived. The simple equation (9) not only enables quantification of these parasitic elements in the equivalent circuit, it points the way to improve the design to minimize their effects. Inductance, when referred to any winding, equals permeance times the number of turns in the referenced winding squared: N µ N A LN N P R l (10) Note that equation (10) is the inductance formula expressed in the SI system of units. Dimensions are in meters, and µ µ 0 µ r. All of the permeances in the equivalent circuit of Fig. 7b can thus be converted into inductance values as seen from the perspective of the winding terminals, by multiplying by N. But in a transformer with multiple windings with different numbers of turns, such as in Fig. 5, this approach becomes very messy and complex because each permeance element takes on different inductance values when seen through different windings with different turns. The transformer equivalent circuit is much simpler and easier to understand if all values are normalized by reference to the same number of turns. It is best if all values are normalized as if all windings had one turn. Transformers function on the basis of Ampere-turns and Volt-seconds per turn this is unchanged by normalization. The transformer magnetic fields and their stored energy are the same whether a winding has 10 turns carrying Amperes or 1 turn carrying 0 Amps.) Also, with 1-turn windings, the permeance values obtained through the duality process do not require further conversion permeances are in fact inductance values as seen through hypothetical one-turn windings. The transformer equivalent circuit remains simple, as shown in Fig. 5b, because all of the elements are on the same basis, and can therefore remain directly connected to each other without intervening turns ratios. This provides better insight and less confusion regarding their relative significance, and best visibility regarding the path to improvement. With all of the windings normalized to one turn, the transformer equivalent circuit cannot be directly connected to the external circuitry. When it is desired to simulate operation in the actual circuit, each terminal pair must be connected to its external circuit through an ideal dc transformer with 1:N x turns ratio, where N x is the actual number of turns of that winding. For example, in the transformer equivalent circuit of Fig. 5b, inductance values are normalized to 1 turn. To connect this equivalent circuit to its external circuit, the primary terminal pair P would be connected through a 1:8 turn ideal transformer, corresponding to the actual number of primary turns. Terminal pairs 1 and would each connect through 1:14 turn ideal transformers. Terminal pair 3 can be directly connected to the external circuit since it actually has 1 turn. The ideal transformers do nothing more than translate the current, voltage and impedances from the normalized transformer equivalent circuit to their actual values in the external environment. The normalized equivalent circuit of the transformer thus contains the non-ideal elements, properly related to each other. Currents in each normalized 1-turn winding are proportional to load power. The highest power load translates into the highest current because with all windings 1-turn, the voltages are equal. This makes it more obvious that: To minimize loss and other leakage inductance effects, the highest power winding should be closest coupled to the primary, and the winding hierarchy should progress from the greatest to the least power. The winding with the greatest power change translates into the greatest current change and greatest Ampere-turn change. For best crossregulation, this winding with the greatest power change should be closest coupled to the primary. The winding hierarchy should progress from greatest power change to least power change. 4-10

90 VI. CIRCUIT SIMULATION A. Transformer Design Benefits Computer simulation of power supply performance is widely used, and is of tremendous benefit in power supply design. Simulation that focuses on the magnetic elements of the power supply can serve as the basis for improved transformer design, and also reveal unexpected problems. With a proper transformer equivalent circuit model, simulation can have the following benefits: 1. Quantify losses from energy stored in leakage and magnetizing inductances, which ends up dumped into snubbers or clamps.. Observe limitations on duty cycle due to Volt-second delays caused by leakage inductance. This may result in failure to achieve required output voltage at low line. 3. Measure cross-regulation problems and evaluate winding hierarchy in this regard. 4. Perform Fourier analysis of current waveforms to help deal more effectively with eddy current losses in the transformer windings. 5. Evaluate modified transformer designs. 6. Discover unexpected problems. B. Using the Model with Simulation Software Using the transformer equivalent circuit normalized to single turn windings, it is necessary to use ideal transformer models with 1:N x turns ratio at each set of terminals to properly translate voltages and currents for compatibility with the circuitry external to the transformer. Ideal transformer models are available with most simulation software packages. Although the currents within the normalized equivalent circuit differ from the currents in the actual windings, this is not a problem. The Ampere-turns are the same, and that is what determines the magnetic force. Leakage inductance energy is a function of ampere-turns and permeance, not turns. When implementing the transformer equivalent circuit in the simulation software net listing, it is best to use discrete inductors to model the leakage inductances and mutual 4-11 inductances. Avoid using the coupled inductor model, which unfortunately assumes a symmetrical bilateral coupling coefficient k1 k1, and usually puts the leakage inductance is in the wrong place. The effects of transformer parasitic inductances can be observed by simulation only in the time domain. This is because leakage inductances and mutual inductances store and release their energy within the span of each switching period. Operating a switching power supply in the time domain with closed loop can be difficult. A great deal of time can be wasted attempting to solve convergence problems related to the steep leading edges encountered in switching supplies. It is much easier to operate open loop in the time domain. Evaluating the closed loop is a separate problem best handled in the frequency domain. However, run times can be very long in the time domain, because time intervals are very short. And if the run is started with zero initial conditions, it can take forever to reach equilibrium operation, especially with control loop open. To avoid this problem, establish initial conditions for power switch pulse width, inductor currents and capacitor voltages that are estimated close to equilibrium values. It may be necessary to make two or three short runs to refine these initial estimates. This can take a lot less time than fighting convergence problems. Don't worry too much about absolute accuracy - look at differential changes. For example, suppose that in checking DC cross regulation error between two outputs, one load is changed. With closed loop operation, the regulated output voltage would remain constant, but the other output would change. With open loop operation, both output voltages will probably change, but that is not important. The differential voltage change is the important concern. C. Minimizing Leakage Inductance The problems associated with leakage inductance are obviously reduced by minimizing the leakage inductance value (although some resonant converter topologies make beneficial use of leakage inductance.) In a conventional

91 transformer structure with concentric helical windings, the leakage inductance field between any two windings has the form of a thick walled cylinder. The shaded area in Fig. 8 shows the cross-section of the leakage inductance field between the primary and secondary 1. Similar cylindrical leakage inductance fields will occur between secondaries 1 and, and between and 3. SHORT LONG INTERLEAVED 3 1 P P 1 3 Fig. 8. Leakage inductance field. The inductance formula of equation (10) shows what can be done to minimize leakage inductance. For A and l in equation (10), use the area and length of the cylindrically shaped leakage inductance field between adjacent windings. Perhaps the best way of minimizing leakage inductance is to increase the length of the field. The same magnetic force (same Ampere-turns) is spread over a greater distance, resulting in lower field intensity, H, thus lower flux density, B, and much lower energy density. This is accomplished by selecting a core with a long narrow window. Thus, the length of the windings (winding breadth) is maximized, while the thickness of the windings and the number of layers is minimized. This has the additional very significant advantage of minimizing AC winding losses. Fig. 9. Reducing leakage L and losses. Ferrite cores designed for high frequency power applications have long narrow windows. Pot cores and PQ cores, although well shielded, are an example of the other extreme, resulting in high leakage inductance. Interleaving the windings has the same beneficial result as doubling the winding length. Interleaving effectively uses twice the winding length that would fit the available window, then folds the combined lengthened windings in half to fit the available space. Thus the leakage inductance field is also doubled and folded, as shown in Fig. 9. The disadvantage of increasing the length or interleaving the windings is that capacitance between the windings is increased. The cross-section area of the cylindrical leakage inductance field is equal to the separation between the windings multiplied by the field circumference -- the mean length per turn of the windings. The cross-section area of the cylindrical leakage inductance field is minimized by minimizing the separation between the windings. Actually, the field penetrates into the windings, as shown in Fig. 8. Accuracy of the calculation is improved by assuming the field thickness equals the separation between the windings plus 1/3 of the thickness of each winding. Ideally, if the windings are wound together (multifilar), leakage inductance is virtually eliminated. However, dielectric isolation requirements or the use of copper foil windings often dictate a separation between the windings. 4-1

92 Even if the physical separation is reduced to zero, the field thickness still includes the penetration into each winding. The only way to significantly reduce the circumference of the windings would be to use a core with a smaller diameter centerleg, but this would increase flux density, core losses, and perhaps saturate the core Reducing the number of turns has a powerful effect on minimizing leakage inductance, but it also reduces shunt mutual inductance with a corresponding increase in magnetizing current and related losses. Also, reducing the number of turns increases flux swing in accordance with Faraday's Law. This may result in an unacceptable increase in core losses, or core saturation. Any or all of the steps above should be taken, up to the point where adverse effects become undesirable. The design approach that will follow attempts to do just that. Another important point to remember is that windings should conform to each other as much as possible. Windings should have the same length, placed one over the other. Do not place windings side-by-side along the core centerpost. This results in huge leakage inductance values. VII. DESIGN STRATEGY The generalized recommendations in this section will be subsequently illustrated with specific application examples. A. Designing a Transformer or Inductor for a Specific Application The circuit designer must first specify the electrical requirements of the application before the magnetic device design can begin. B. Core Selection The first step in the design process is to tentatively select a core. this involves selecting the core material, core shape and size. [7] At the frequencies involved in most switching power supply applications (>100 khz), ferrite is the almost universal choice because it generally has lower losses than other available materials. High frequency losses in ferrites are mostly caused by eddy currents in the core. Ferrite materials with the highest resistivity have the lowest high frequency core loss, but these materials also have lower permeability, resulting in greater magnetizing current and smaller mutual inductance. Select a core family with a long, narrow winding window. Maximizing the winding breadth minimizes the leakage inductance, minimizes the number of layers in each winding, and minimizes eddy current losses in the windings. Many good choices are possible in the E-E, low profile, and planar families Avoid pot cores and PQ cores, which have short, stubby windows. The next step in core selection is to tentatively determine the appropriate core size. Experience can be very helpful in making this decision. Area product formulae are also useful in making an approximation of core size. At the conclusion of the design process (on paper), if the calculated temperature rise or calculated losses are too great, repeat the process using the next larger core size. Likewise, if losses and temperature rise are well below the design limits, repeat the design with the next smaller size. C. Core Utilization A core can be said to be fully utilized in a given application if it is operated at times at maximum flux density (determined by core loss or core saturation) and at other times, at maximum current density in the windings (determined by winding loss). Above 50 khz, in applications where large flux swings are encountered, flux density is usually limited by core loss. (In transformers used in buck derived topologies such as forward converter, half bridge, and bridge, and in flyback transformers operated in the discontinuous mode.) But in filter inductors and flyback transformers operated in the continuous mode, flux swings are usually small, resulting in small core losses. Flux density is more likely to be limited by core saturation. The author recommends a design approach which operates the core near its flux density limit, determined either by core loss or by saturation. By pushing flux density to its limit, the windings will have minimum turns, minimizing leakage inductance and minimizing 4-13

93 winding loss. Because core sizes come in discrete steps, it is most likely that the best choice will be somewhat oversize and thus the winding window may not be fully utilized. This is beneficial because it makes it easier to design the windings to achieve low ac loss. D. Saturation or Loss Limited? For a transformer -- changes in flux density, B, are determined solely by the Volt-seconds per turn applied to the windings (Faraday's Law). In a transformer application, use the manufacturer s core loss data to determine the B that can be sustained for normal operation. (As a rough guide, core loss of 100 mw/cm 3 is a good initial goal for a transformer operated with natural convection cooling.) Then calculate worst-case B MAX with maximum Volt-seconds under start-up or transient overload conditions, to determine whether flux density remains within the saturation limit under these abnormal conditions. According to Faraday s Law: B B MAX NORMAL max Volt-seconds normal Volt-seconds (11) Magnetizing current in a transformer is unrelated to load. It is in addition to load related currents in the windings, and is usually much smaller. Magnetizing current can be determined from calculated flux density applied to the ferrite non-linear B-H characteristic shown on the core manufacturer s data sheet. But for an inductor or flyback transformer all of the current is magnetizing current, and current established by the external circuit, rather than Volt-seconds/turn, determines the points of operation along the B-H characteristic. In order to store the necessary energy in inductors and flyback transformers, non-magnetic gaps are used in series with the core. The gap characteristic is perfectly linear, and it dominates and linearizes the overall characteristic. Thus, although B is always determined strictly by Faraday's Law, the linearized B-H characteristic results in flux density being also linearly related to Ampereturns in the windings, so that: B I max max B I MAX MAX (1) Since worst case I and max. peak shortcircuit current I MAX are known circuit parameters, the above relationship makes it easy to determine whether flux density is limited by loss ( B max ), or by saturation (B MAX ). E. Determine the Loss Limit Losses may be limited either indirectly by a temperature rise limit, or by a direct loss limit imposed by efficiency considerations, whichever is smaller. Divide the temperature rise limit by the thermal resistance to calculate the temperature rise loss limit. Thermal resistance, R T, for natural convection cooling is often stated on the manufacturers data sheet. Otherwise, thermal resistance can be crudely calculated from the following relationship: 36 RT AW (13) where A W is the winding window area in cm. F. Winding Losses Design of the transformer windings to achieve acceptable AC losses can be both difficult and tedious. Computer software is available which can ease this task. A self written spreadsheet program can prove helpful. A detailed discussion of ac winding losses, skin and proximity effects, is beyond the scope of this topic see references [5] and [6]. However, some important points to remember When the number of turns in a winding exceeds the available breadth, then the winding must be built up in multiple layers, one on top of the other. However, AC winding losses increase exponentially with the number of layers, unless the conductor thickness is much less than the skin depth at the operating frequency. It is vitally important to minimize the number of layers in each winding. The layers can be minimized by: 1. Minimize the number of turns in the windings by operating the core close to the flux density limit. 4-14

94 . Use a core shape with a long, narrow window. Greater winding breadth reduces the number of layers required to accommodate a given number of turns. 3. Interleave the windings. Interleaving essentially doubles the winding breadth, then folds the windings to fit the available space. This creates two winding sections, with half the total number of layers in each section. Calculate the high frequency current skin depth (penetration depth, D PEN ) at the transformer operating frequency. D PEN equals 0.4 mm at 100 khz in copper at 100ºC, and varies inversely with the square root of frequency. Remember that! Thus, at any frequency: D PEN 100kHz mm (14) f D PEN equals 0.1 mm at 400 khz,.06 mm at 1.6 MHz, etc. AC resistance curves such as in Fig. 10 and reference [5] demonstrate clearly the problem that occurs with multiple layers, requiring conductor thickness to be much less than D PEN. However, a single layer winding which happens to be at the outside or the very inside of a group of windings can be of any thickness without any problem. This is because the magnetic field within the winding structure terminates on these layers at the inner and outer extremities. If these layers are much thicker than D PEN, the AC resistance will not benefit, but the DC resistance will be less. When AC losses would otherwise be excessive because conductor thickness is too great, Litz wire is often used. Litz wire consists of many strands of fine wire interwoven in a unique way. (Simply twisting a bundle of fine wires won't do.) But a single layer of Litz wire must be considered as many layers of fine wires. For example, a Litz wire with 5 strands is roughly equivalent to a square array of 15 by 15 fine wires (15 is the square root of 5), and a single layer of this Litz wire must be considered 15 layers of the fine wire when entering the AC resistance curves. It is necessary to evaluate the current waveforms in each winding to determine the average DC and RMS AC current values. Using the calculated value of DC resistance and the AC resistance multiplying factor, F R, obtained from the AC resistance curves, power loss in the winding can be calculated: W DC DC + AC DC R P I R I R F (15) Don t make the conductors any bigger than they need to be. If there is some space available within the winding window, resist the temptation to fill it with copper this can actually make it more difficult to reduce AC losses. Fig. 10. AC resistance R AC /R DC. 4-15

95 VIII. FLYBACK TRANSFORMER DESIGN EXAMPLE A. Application Parameters: Operating Mode: Continuous Inductor Current (CCM) Frequency: 50 khz Input Voltage: 100 to 00 VDC Max. Duty Cycle: 0.45 V) Output 1: A Output : A Primary Inductance: 5 mh Max. Ambient Temp: 85 C Max. Temp. Rise: 40 C Max. Loss: 0.5 W Calculated Values (see Fig. 11 and Appendix) Turns Ratio N N P/N S: 4 Min. Duty Cycle D MIN: 0.9 (@00 V) Max Input Power: 8.83 W (@ 90% efficiency) Max. Primary peak I PK: 0.14 A (@ 100 V) Max I PRI:.046 A (@ 00 V) Max RMS Primary I FL : 0.13 A (@ 100 V) Max DC Primary I INdc:.088 A (@ 100 V) Max rms AC Primary I INac:.098 A (@ 100 V) I I INdc I INpavg Secondary A-T Fig. 11. Primary current waveform. B. Define Core Material In the continuous inductor current mode (CCM), the AC flux component is relatively small, so that the flux density swing is usually limited by saturation rather than core loss. Magnetics Type P material is chosen for this application because it has higher saturation flux density and higher permeability than K material. Lower loss K material would be the better choice for discontinuous mode operation, which has a much greater flux swing. C. Determine the Maximum Flux Density With continuous mode operation, start with the assumption that flux density is saturation limited. For P material at 15ºC, a B SAT limit of 0.3 Tesla (3000 Gauss) is assumed. With a gapped core, flux density is linearly related to current, so that equation (1) is used, solving for B max : BMAX Bmax Imax (16) I MAX 0.3 Bmax Tesla 0.14 Divide B max by to convert from peak-peak to peak (core loss data is based upon peak ac values). Entering the manufacturer s core loss curves at.03t (30 Gauss) and 50 khz, core loss is 16 mw/cm 3. This is far below the 100 mw/cm 3 target for core loss limited operation, demonstrating that in this application, the core will definitely be saturation limited and core loss will be very small. D. Define the Core Size and Configuration Initial determination of core size can be based on the area product formula (Magnetics Design Handbook, page 5-6). Since the flux swing will be limited by saturation, not by core loss, equation (a) from the Handbook is used: LISCpk IFL AP cm 4 (17) BmaxK1 The value of K1 for a flyback transformer with primary and secondary isolation is AP.01 cm Referring to the core catalog, low profile core set 4110-EC with Area Product.065 is tentatively chosen. Important measurements are: Overall Core Dimensions:.0 x.0 x cm Winding Window Area, A W: 0.38 cm Window Width / Height: / 0.35 cm Mean Length per Turn MLT: 3.0 cm Core Area, A E: cm Core Path Length, l E: 4.61 cm Core Volume, V E: 0.79 cm 4-16

96 Fig. 1. Core set 4110-EC. E. Determine the Loss Limit From equation (13), thermal resistance can be estimated: RT 95 ºC/Watt AW 0.38 Dividing the temperature rise limit, 40ºC, by 95ºC/Watt results in a temperature rise loss limit of 0.4 Watts. Since this is greater than the absolute loss limit of 0.5 W, the 0.5 W limit will apply, and temperature rise will be less than the 40ºC rise allowed in the specification. F. Calculate the Number of Primary Turns, N P Since flux density is saturation limited in this application, B max and corresponding max. peak current are used in equation (18) to calculate the minimum number of primary turns capable of achieving the required inductance value and push core operation to its flux density limit. LI 3 pk N P min 10 t (18) B 4 max A e Calculate the minimum turns for the 3.3V secondary, and round up to nearest integer. Then recalculate primary turns: N S N P turns N 4 N N N turns P S Ag 4 l g µ 0N 10 L l g 4π cm This formula neglects the fringing field adjacent to the centerleg gap. In this application, the gap length is so small compared to the dimensions of the centerleg that the effect of the fringing field is minimal. Gap correction formulae can reduce inaccuracy due to fringing field. [8] Using the uncorrected gap length calculated above, if the measured inductance is too large, increase the gap length slightly by trial and error. Do not change the number of turns. H. Define the Primary Winding Primary Turns, N P : 16 turns Turns Ratio (3.3V), N : 4 Secondary Turns (3.3V), N S1: 9 turns Primary llngth N P x MLT 16 x cm Using wire tables (Reference [10]), AWG3 (0. mm) wire is selected for the primary. Primary Winding AWG3 : 4 layers, 54 turns/layer, 16 t Primary Resistance :.007 Ω/cm x Ohms AWG3 Insulated Diameter : 0.4 mm Primary Breadth / Height : 13mm / 0.96mm Skin 50kHz, D PEN : 0.15mm (equation 14) Referring to the procedure discussed in Reference [5], pages R-8 to 9, the effective layer thickness equals the conductor diameter multiplied by 0.75, taking into account the conductors are round and spaced apart by the amount of insulation on the wires. Thus, the effective layer thickness equals 0. mm x mm. Entering the AC resistance curves, Fig. 10: Layer Thickness/D PEN, Q 0.15/ AC Resistance Factor, F R :.5 (4 layers) AC Resistance Factor, F R : 1.3 ( layers - interleaved) G. Calculate the Gap Length, l g The inductance formula, equation (10), is inverted and solved for the air gap length that will satisfy the inductance requirement using the number of turns previously calculated (the 10 4 term modifies SI units to centimeters and micro- Henries): 4-17

97 With the DC and AC currents defined, equation (15) is used to calculate the winding loss, for 4 and for layers. Interleaving divides the windings into two sections, with primary layers on each side of the secondaries, thus reducing F R and AC loss substantially. Non-interleaved: P W W Interleaved: P W W I. Define the 3.3 Volt Secondary Winding Calculated Values (see Appendix): Max DC Secondary I DC: 1.5 A (@ 100 V) Max rms AC Secondary I AC: 1.35 A (@ 100 V) Secondary Turns (3.3 V), N S1: 9 turns Secondary Length N S1 x MLT 9 x cm Litz wire consisting of 75 strands AWG40 is selected for the 3.3 V secondary, with 9 turns wound in a single layer. Turns are spaced apart to span 13 mm, conforming to the primary breadth. DC resistance is Ω/cm. Secondary Resistance : Ω/cm x Ω Insulated Diameter : 0.89 mm Secondary Breadth / Height : 13 mm / 0.89 mm AWG 40 Diameter:.08 mm Skin 50 khz, D PEN : 0.15 mm (equation 14) The effective layer thickness equals the AWG40 diameter multiplied by 0.75, taking into account the round conductors spaced apart by the amount of insulation on the wires. Thus, the effective layer thickness is.08 mm x mm. The single layer of Litz wire with 75 strands of AWG40 is equivalent to 8.66 layers, 8.66 strands wide ( ). Interleaving halves the effective layers to Entering the AC resistance curves, Fig. 10: Layer Thickness/D PEN, Q.06 / AC Resistance Factor, F R : 1. (8.66 layers) AC Resistance Factor, F R : 1.05 (4.33 layers - interleaved) With the DC and AC currents defined, equation (15) is used to calculate the winding loss, for non-interleaved and for interleaved construction: Non-interleaved: P W W Interleaved: P W W J. Define the 5 Volt Secondary Winding Calculated Values (see Appendix): Max DC Secondary I DC: 0.6 A (@100 V) Max rms AC Secondary I AC: 0.54 A (@100 V) Secondary Turns (5 V), N S: 14 turns Secondary Length N S1 x MLT 14 x cm With 9 turns delivering 3.4 V (including synchronous rectifier drop), 14 turns produces 5.9 V. A Schottky rectifier should be used to reduce the output to a nominal 5 V. Litz wire consisting of 30 strands AWG40 is selected for the 5-V secondary, with 14 turns wound in a single layer. Turns are spaced apart to span 13mm, conforming to the primary breadth. DC resistance is Ω/cm. Secondary Resistance : Ω/cm x Ω Insulated Diameter : 0.56 mm Secondary Breadth / Height : 13 mm / 0.56mm AWG 40 diameter:.08 mm Skin 50kHz, D PEN : 0.15 mm (equation 14) The effective layer thickness equals the AWG40 diameter multiplied by 0.75, taking into account the round conductors spaced apart by the amount of insulation on the wires. Thus, the effective layer thickness is.08 mm x mm. The 30 strands of AWG40 are equivalent to 5.5 layers, 5.5 strands wide (5.5 30). Interleaving halves the effective layers to.75. Entering the AC resistance curves, Fig. 10. Layer Thickness/D PEN, Q.06 / AC Resistance Factor, F R : 1.1 (5.5 layers) AC Resistance Factor, F R : 1.0 (.75 layers - interleaved) 4-18 Equation (15) is used to calculate the winding loss, for non-interleaved and for interleaved construction:

98 Non-interleaved: P W W Interleaved: P W W K. Total winding losses Non-interleaved: W Interleaved: W Interleaving is not necessary to achieve loss goal, but can reduce loss by.056 W and reduce leakage inductance, at the expense of additional inter-winding capacitance. Total winding Height.41 mm mm, out of an available 3.5 mm. An additional layers of 1mil mylar insulation is placed between primary and secondaries,.05 mm total for non-interleaved, 0.1 mm total for interleaved windings. L. Total Losses Core loss equals 16 mw/cm 3 times core volume of 0.79 cm 3 equals 1.5 mw. Thus, total loss equals: Non-interleaved: P T W Interleaved: P W T M. The Equivalent Circuit Model Fig. 13 shows the non-interleaved winding structure through the window on one side of the core (not to scale). The corresponding reluctance model and electrical equivalent circuit are shown in Figs. 13a and 13b. From equation (5), reluctance l/µa. Convert all dimensions to meters! For the cylindrical regions between P and S1, and between S1 and S, Areas include 1/3 the thickness of adjacent windings (plus insulation between P and S1), multiplied by mean length per turn (MLT 3 cm). The length of these cylindrical regions equals the breadth of the winding window cm. Reluctance P-S1: / / A P 1 ( ) m l P1 7 5 R µ A 4π Reluctance S1-S: / / A P 1 ( ) m R π Reluctance of Centerleg Gap l g R GAP µ A 7 4 e 4π Reluctances of the two outer legs are paralleled, and can be combined into a single reluctance. One half of the total ferrite path length is assigned to the combined outer legs, the other half to the centerleg, making these reluctances equal. Relative permeability of the ferrite equals Reluctance of Ferrite Centerleg and Outer Legs 0 6 ( ) le R L µµ A 4π r e Permeance values in Fig. 13b are the reciprocal of the reluctance values in Fig. 13a. Permeance values equal inductance that would be seen through a 1 turn winding, and should be multiplied by N to obtain inductance value seen through a winding of N turns. For example, referred to the 16 turn primary, P GAP µh x 16 becomes 5 mh, and leakage inductance P P µh x 16 becomes 79 µh

99 IX. TRANSFORMER DESIGN EXAMPLE 1 P A. Application Parameters: Operating Mode: Forward Converter, 50 W Frequency: 50 khz Input Voltage: 100 to 00 VDC Max. Duty Cycle: 0.45 (@100 V) Output 1: A Output : 10 A Max. Ambient Temp: 85 C Max. Temp. Rise: 40 C Max. Loss:.5 W Fig. 13. Flyback transformer structure. - + N P I P R CL 0.36 R GAP 9.3 ΦP Φ1 - + N 1 I 1 R P1 590 Φ - + N I R RELUCTANCE VALUES x 10 6 Fig. 13a. Reluctance model. VP P GAP P P1 P P CL.8 V P 1 OL.8 PERMEANCE VALUES x 10-6 Fig. 13b. Equivalent circuit model. R OL 0.36 V B. Calculated Values (see Appendix): Turns Ratio N N P/N S: 1 C. Define Core Material In the continuous current mode, the AC flux component is relatively large, so that the flux density swing is usually limited by core loss rather than saturation. Magnetics Type K material is chosen for this application because it has lower loss than P material, although it has lower saturation flux density and lower permeability. D. Determine Maximum Flux Density Start with the assumption that flux density is core loss limited. Refer to the core manufacturer s loss curves for the K material. Since the transformer will be used with natural convection cooling, the curve is entered at 100 mw/cm 3 and 50 khz. The corresponding flux density is 700 Gauss, or.07 Tesla. The flux density axis on the core loss curves is based upon peak ac values, so multiply by to convert from peak to B (peak-to-peak). Thus B 0.14 Tesla The turns ratio is established so that under normal operating conditions, maximum duty cycle, D MAX, occurs only at low V IN 100 V. However, under abnormal operating conditions, such as during startup or with transient overload, the control circuit may call for D MAX when the V IN may be simultaneously at maximum 00 V. Thus, the Volt-second pulses and corresponding B applied to the primary for a few cycles will be greater than normal. From equation (11), solving for B MAX : 4-0

100 00 V B MAX 0.14 T 0.8 Tesla 100 V Since this is less than the B SAT limit of 0.3 T (3000 Gauss) for K material, core operation is loss limited. E. Define Core Size and Configuration Initial approximation of core size can be based on the area product formula (Magnetics Design Handbook, page 4-8: The value of K for a forward converter is.014. PO AP K B ft 4 3 (19) " cm 4 50 AP Referring to the Magnetics core catalog, from the ETD family, the smallest core set EC with AP 1.1 is tentatively chosen. Overall Core Dimensions: 3.4 x 3.4 x 1.08 cm Core Area, A E: 0.98 cm Core Path Length, l E: 7.91 cm Core Volume, V E: 7.80 cm Winding Window Area, A W : 1.83 cm Bobbin Winding Area, A W : 1.3 cm Winding Area Width/Height:.15 / 0.6 cm Mean Length per Turn, MLT: 6.1 cm Fig EC core set. Determine Loss Limit From equation (13), thermal resistance can be estimated: RT 19.6 ºC/Watt AW 1.83 Dividing the temperature rise limit, 40 ºC, by 19.6ºC/Watt results in a temperature rise limited loss of.04 W. Since this is less than the absolute loss limit of.5 W, the.04 W temperature rise limit will apply. One Watt will be allocated to core loss, 1 W to winding loss. F. Recalculate Loss Limited Flux Swing? With 1 W allocated to core loss divided by core volume of 7.8 cm 3, core loss of 18 mw/cm 3 is permissible. This would allow a slightly greater flux swing, but bring the worst case startup condition closer to saturation. Retaining the original 100 mw/cm 3 limit times 7.8 cm 3 core volume, core loss will be 0.78 W. G. Calculate Max Volt-seconds/Turn Faraday s Law: dφ E dt N max Vdt AE B N 13.7 Volt-µ sec/turn H. Calculate Secondary Turns Because the number of turns must be an integral number, the winding with the fewest turns poses the greatest difficulty. For example, if the minimum number of secondary turns dictated by max. Volt-seconds per turn equals 1.4, then turns must actually be used. This will make the winding bulkier than optimum, perhaps necessitating a larger core size. Secondary Volt-µsec: V V O OT ( ) / f + V-µs Minimum secondary turns: N 13.6V-µs S min 0.99 turns 13.7V-µs/turn ( ) 4-1

101 This is indeed fortunate! With a 1-turn secondary, flux swing will be only 1% less than the previously determined maximum. This will make it unnecessary to recalculate core loss. But a 1-turn secondary for the 3.4 (3.3) V output results in 6.8 V from a turn winding for the 5-V output. This will require a post-regulator. Cross-regulation problems are thereby eliminated. But a linear post-regulator will dissipate an unacceptable 17 W at 10 A, a 7% loss of efficiency. So a switching post-regulator must be used at little cost by independent PWM control of the synchronous rectifiers in the 5-V output. There are 3 alternatives to resolving this issue: 1. Use 1 turn for 3.3 V, turns for 5 V, with switched post-regulation as above.. Go to turns for the 3.3-V output, 3 turns for the 5-V output. 3.4 Vx3/ 5.1 V, allowing for a 0.1-V synchronous rectifier drop. There is probably room for the bulkier windings, because the core selected was significantly oversize, but cross-regulation becomes critical, and leakage inductance will be 4 times greater ( turns ), causing 4 times greater loss in snubbers or clamps. Flux swing will be much less, reducing core loss. 3. Use 1 turn for the 3.3-V output and 1½ turns for the 5-V output. Fractional turns require additional windings on the core, otherwise leakage inductance is totally unacceptable. See Reference [11]. Cross regulation becomes critical. Because synchronous rectifiers will be used for both outputs, independent PWM of the 5-V output using Option 1, although it adds complexity, has the benefits of efficiency, regulation, and much lower leakage inductance, I. Define Primary Turns With a 1:1 turns ratio, the primary will have 1 turns. J. Define Primary Turns Calculated Values (see Appendix): Max DC Primary I INdc:.8A (@100V) Max AC Primary I INac: 3.37A (@100V) Primary Turns, N P : 1 turns Primary Length N P x MLT 1 x cm 4- The primary is interleaved with 6 turns inside the secondaries, and 6 turns on the outside. The primary winding consists of 3 paralleled Litz wires, each with 100 strands AWG40. The three Litz wires are wound side-by-side in a single layer across the width of the bobbin. Six turns times 3 wires equals 18 Litz wires across the bobbin. Turns are spaced apart to span 0 mm, within the bobbin 1.5 mm winding breadth. DC resistance is.00045/ Ω/cm. Primary Resistance : Ω/cm x Ω Insulated Diameter : 1.01 mm Primary Breadth / Height : 0 mm / 1.01 mm x AWG 40 Diameter:.08 mm Skin 50 khz, D PEN : 0.15 mm (equation 14) The effective layer thickness equals the AWG40 diameter multiplied by 0.75, taking into account the round conductors spaced apart by the amount of insulation on the wires. Thus, the effective layer thickness is.08mm x mm. The single layer of Litz wire with 100 strands of AWG40 is equivalent to 10 layers, 10 strands wide (10 x ). Entering the AC resistance curves, Fig. 10: Layer Thickness/D PEN, Q.06 / AC Resistance Factor, F R : 1.5 (10 layers) With the DC and AC currents defined, equation (15) is used to calculate the winding loss: P W P K. Define the 3.3 Volt Secondary Winding Calculated Values (see Appendix): Max DC Secondary 1 I 1dc: 60 A (@100 V) Max AC Secondary 1 I 1ac: 7 A (@100 V) Secondary turns (3.3 V), N S1: 1 turn Secondary length N S1 x MLT 1 x cm Solid copper strip, 1.5 mm thick by cm wide, conforming to the primary breadth. DC resistance is 5.75 x 10-6 Ω/cm. Secondary Resistance : 5.75x10-6 Ω/cm x x 10-6 Ω Thickness : 1.5 mm Secondary Breadth / Height : 0 mm / 1.5 mm Skin 50kHz, D PEN : 0.15 mm (equation 14)

102 The effective layer thickness equals the 1.5 mm thickness of the strip. One turn equals 1 layer. Interleaving halves the effective layers to ½ layer. Entering the AC resistance curves, Fig.10: Layer Thickness/D PEN, Q 1.5 / AC Resistance Factor, F R : 4.5 (1/ layer - interleaved) With DC and AC currents defined, equation (15) is used to calculate the winding loss, for interleaved construction: ( ) 6 P S W This is a difficult situation. The layer thickness results in a DC loss component of only 0.15 W. The AC current, confined to the surfaces, results in a loss of W. Without interleaving, only one surface of the copper strip would conduct AC current, doubling the AC loss. A thicker strip would reduce the already small DC loss, but not improve the AC loss. L. Define the 5 Volt Secondary Winding Calculated Values (see Appendix): Max DC Secondary I dc: 10 A (@100 V) Max AC Secondary I ac: 1.1 A (@100 V) Secondary Turns (6.8 V), N S: turns Secondary Length N S x MLT x cm Solid copper strip, turns, 0.3 mm thick by cm width, conforming to the primary breadth. DC resistance is 9 x 10-6 Ω/cm. Secondary resistance : 9x10-6 Ω/cm x Ω Thickness : 0.3 mm Secondary Breadth / Height : 0 mm / 0.6 mm Skin 50 khz, D PEN : 0.15 mm (equation 14) The effective layer thickness equals the 0.3 mm thickness of the strip. Two turns equals layers. Interleaving halves the effective layers to 1 layer. Entering the AC resistance curves, Fig. 10: Layer Thickness/D PEN, Q 0.3 / AC Resistance Factor, F R :.0 (1 layer - interleaved) With the DC and AC currents defined, equation (15) is used to calculate the winding loss, for non-interleaved and for interleaved construction: ( ) P S W Total winding losses: P Watts W M. Total Losses Core loss equals 0.78 Watts. Thus, total loss equals: PT PW + PC W This is less than the specified.5 Watt absolute limit, but greater than the.04 Watt temperature rise limit. With R T 19.6 ºC/W, temperature rise of 41ºC results, slightly exceeding the 40ºC limit. This is an acceptable result, especially considering the uncertainty of the R T value. N. Total winding Height: 1.01( ) mm The available height is 6.1 mm. An additional layers of 1mil mylar insulation is placed between primary and secondaries, and one layer between each of the secondary layers, for a total of 0.15 mm additional. O. The Equivalent Circuit Model Fig. 15 shows the interleaved winding structure through the window on one side of the core (not to scale). The corresponding reluctance model and electrical equivalent circuit are shown in Figs. 15a and 15b. From equation (5), reluctance l/µa. Convert all dimensions to meters! For the cylindrical regions between P1 and S1, between S1 and S, and between S and P: Areas include 1/3 the thickness of adjacent windings (or to one skin depth in thick 3.3 A copper strip) plus insulation between windings, multiplied by mean length per turn (MLT6.1 cm). The length of these cylindrical regions equals the breadth of the winding window.15 cm. 4-3

103 Reluctance P1-S1: 1.01/ / A P 1 ( ) m l P R µ A 4π Reluctance S1-S: A 0.15 / / ( ) m R π Reluctance S-P: A 0.6 / / P ( ) m P R π Reluctances of the two outer legs are paralleled, and can be combined. One half of the total core path length is assigned to the combined outer legs, the other half to the centerleg, making these reluctances equal. Ferrite µr Reluctance of Ferrite Centerleg and Outer Legs 0 ( 7.91 ) 10 le R L µµ A 4π r e R OL R CL Permeance values in Fig. 15b are the reciprocal of the reluctance values in Fig. 15a. Permeance values equal the inductance that would be seen through a 1 turn winding. Permeance multiplied by N gives the inductance value seen through a winding of N turns. For example, referred to the 1 turn primary, leakage inductance P P µh x 1 becomes 0. µh. For simulation in an external circuit, S1 is directly connected since it is 1 turn. Use a 1: ideal transformer to connect -turn S. Use 1:6 transformers to connect each of the two primaries, with the external side of these transformers connected in series to achieve the actual 1 turns. 6 P S S1 P1 Fig. 15. Interleaved transformer structure. ΦP1 - + N P1 I P1 R CL ΦS1 - + N S1 I S1 R P1 643 ΦS N S I S R 1 N P I P R P RELUCTANCE VALUES x 10 6 Fig. 15a. Reluctance model. V P1 P CL 9.3 P P1 P 1 P P ΦP R OL V P OL S1 V S V P 9.3 PERMEANCE VALUES x 10-6 Fig. 15b. Equivalent circuit model. 4-4

104 X. REFERENCES [1] Unitrode/TI Magnetics Design Handbook, TI Literature No. SLUP13 [] L.H. Dixon, The Effects of Leakage Inductance on Switching Power Supply Performance, Unitrode/TI Magnetics Design Handbook, 000, Topic R4, TI Literature No. SLUP13 [3] L. H. Dixon, The k Transformer Model, an Inappropriate Abstraction, Unitrode/TI Seminar Manual SEM-1400, 001, pp 3-1, TI Literature No. SLUP133 [4] L.H. Dixon, Deriving the Equivalent Electrical Circuit from the Magnetic Device Physical Properties, Unitrode/TI Magnetics Design Handbook, 000, Topic R3, TI Literature No. SLUP13 [5] L.H. Dixon, Eddy Current Losses in Transformer and Circuit Wiring, Unitrode/TI Magnetics Design Handbook, 000, Topic R, TI Literature No. SLUP13 [6] L.H. Dixon, Section 3 -- Windings, Unitrode/TI Magnetics Design Handbook, 000, Topic 3, TI Literature No. SLUP13 [7] L.H. Dixon, Section Magnetic Core Characteristics, Unitrode/TI Magnetics Design Handbook, 000, Topic 3, TI Literature No. SLUP13 [8] L.H. Dixon, Section 5 Inductor and Flyback Transformer Design, Unitrode/TI Magnetics Design Handbook, 000, Topic 3, TI Literature No. SLUP13 [9] L.H. Dixon, Section 4 Power Transformer Design, Unitrode/TI Magnetics Design Handbook, 000, Topic 3, TI Literature No. SLUP13 [10] L.H. Dixon, Winding Data, Unitrode/TI Magnetics Design Handbook, 000, Topic R7, TI Literature No. SLUP13 [11] L.H. Dixon, How to Design a Transformer with Fractional Turns, Unitrode/TI Magnetics Design Handbook, 000, Topic R6, TI Literature No. SLUP13 The Unitrode/TI Magnetics Design Handbook and other materials referenced above are available on the web site: power.ti.com Click: Support/Training/Seminar Materials Request free printed copies from: Texas Instruments 50 Phillippe Cote Street Manchester, NH Attn: Marketing Communications (603)

105 APPENDIX A Although not strictly a part of the magnetic design, certain electrical parameters necessary for the design must be calculated: I. FLYBACK TRANSFORMER, CONTINUOUS MODE V IN, V OUT, Turns Ratio N N P /N S, and duty cycle D are inter-related as follows. D is maximum at low V IN, and minimum at high V IN. (V O is increased by a 0.1-V synchronous rectifier drop.) N P VIN D N S V (1 D) O 4 D VO 3.4 MIN ( ) VIN V ( O ) N Primary current waveform: I I INpavg Secondary A-T I INdc Maximum primary current occurs at low V IN. First, calculate the DC component: I INdc The primary current pulse average value: P IN V 100 IN Amps I I INdc.088 INpavg A D 0.45 Maximum total RMS primary current: The AC component: ( INdc ) ( ) 1 1 I I D A FL ( ) 1 INac FL INdc I I I.098 Amps Maximum primary I occurs at high V IN, low D; minimum I at low V IN, high D. t ON D/f VIN D VIN D Imax.046 Amps Imin.036 LP f K LP f K Maximum instantaneous peak current, I pk, occurs at low V IN : Amps I pk I I INpavg A 4-6

106 A. Calculate currents in 3.3-V secondary: DC output current, I DC 1.5 Amps Maximum total RMS secondary current: The AC component: I FL 1 DC ( ) 1 I 1.5 / (1 D) A ( ) 1 AC FL DC I I I 1.35 Amps B. Calculate currents in 5-V secondary: DC output current, I DC 0.6 Amps Maximum total RMS secondary current: The AC component: I FL 1 DC ( ) 1 I 0.6 / (1 D) A ( ) 1 AC FL DC I I I 0.54 Amps APPENDIX B I. FORWARD CONVERTER V IN, V OUT, Turns Ratio N N P /N S, and duty cycle D are inter-related as follows. D is maximum at low V IN, and minimum at high V IN. (V O is increased by 0.1V synchronous rectifier drop.) this calculated value is the maximum turns ratio, limited by D MAX. VIN mindmax N MAX 13.3 VO 3.4 A turns ratio of 13:1 will result in D at low V IN a little less than the specified D max. However, because the 3.3 V secondary will be quite thick, the winding structure must be interleaved, by dividing the primary into two equal sections, 6 turns each, so that N 1. Recalculating D max with N 1, Dmax A. Calculate Primary Currents: Once the turns ratios and D max have been established, DC and AC currents in the windings can be calculated. Maximum primary current occurs at low V IN. First, calculate the DC component. Assuming 90% efficiency, power input is 50/.9 78 Watts: 4-7

107 I INdc Maximum total RMS primary current: P IN 78.8 V 100 IN Amps The AC component: I FL 1 1 INdc I D A ( ) 1 INac FL INdc I I I 3.37 Amps B. Calculate currents in 3.3V secondary: Maximum total RMS primary current: I 1dc 60 Amps The AC component: I 1FL 1 1 1dc I D Amps ( ) 1 1ac 1FL 1dc 7 I I I Amps C. Calculate currents in 5V secondary: Maximum total RMS primary current: I dc 10 Amps The AC component: I FL 1 1 dc I D A ( ) 1 ac FL dc I I I 1.1 Amps 4-8

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109 Under the Hood of Low-Voltage DC/DC Converters Brian Lynch and Kurt Hesse ABSTRACT With the evolutionary decrease of DSP core and I/O power supply voltage levels, comes the need for efficient power conversion from existing bus voltages to newer and lower, voltages. At the same time, DC/DC converters are continuing their own evolutionary trend towards smaller size and lower cost. Caught in the middle are the circuit designers who have little experience in development of DC/DC converters, yet must incorporate them in their own systems. This topic provides a guide for engineers to follow in designing a point of use DC/DC converter. Technical challenges encountered designing for low voltage operation, and tradeoffs of different component types are presented to allow designers to make choices based on their own particular circuit or system needs. Using an example design, concepts are reviewed with attention made to underlying principals and practical ramifications. I. INTRODUCTION Converting one low voltage to a lower voltage provides a number of challenges to power supply design, some of which are unique. For an equivalent system power level, low voltage implies higher currents, therefore higher conduction loss and lower tolerance for voltage deviation. As a benefit, low voltage also implies lower switching loss than that found in a high voltage counterpart. In this paper, a background discussion of basic buck converter operation creates a foundation for detailed explanation of converter operation and component selection issues. From this, the designer should be able to decide which fundamental design philosophy should be followed, whether it is to optimize for circuit performance, component cost, or power density. The interdependencies of parameters within a DC/DC converter are also discussed, allowing a designer to understand and trade off conflicting design goals. For example, if fast transient response or high power density is paramount, then a high operating frequency is in order. Conversely, if high efficiency is the most important parameter to achieve, then a low switching frequency may be the best choice. Another fundamental issue is the method of construction and the level of manufacturing for the converter. Surface mount technology, used extensively for electronics construction, continues an ever-evolving trend towards smaller component packages. While this makes it easier to meet power density goals, it also becomes more difficult to maintain good thermal design. Small packages reduce printed circuit board parasitics, however they also may require some sort of heat sinking to keep temperatures low and reliability high. II. TOPOLOGY OVERVIEW A. Synchronous Buck Converter Operation A buck converter operates by applying a pulse width modulated (PWM) waveform to an L-C filter. The filter then averages the PWM waveform, resulting in a DC output voltage. A variation on a simple buck replaces the "catch" diode with a controlled switch, or Synchronous Rectifier (SR). See Fig. 1. A synchronous rectifier generally has lower losses than a conventional or Schottky diode, and so its use is quite popular in low voltage DC/DC converters. 5-1

110 DC Input Synchronous Rectifier Switch Control Circuit SR PWM VCC GND SW Node COMP Averaging Circuit Z Output Fig. 1. Synchronous buck converter schematic. To begin a discussion of DC/DC converters, a few fundamental relationships need understanding. In an ideal (lossless) buck converter, the input voltage and the duty cycle of the switch determine the output voltage. t Vout D on Vin Vin Ts Where the duty cycle is defined as the ratio of the main switch ON time to the total period. This relationship holds as long as there is continuous current flowing in the inductor. Another important relationship relates the inductor value to the amount of AC ripple current in the converter. Iout ( Vin Vout) L D Ts Where Iout is the peak-to-peak ripple current in the output inductor. Notice the effect the input to output voltage differential has on the result. Z Z The next step is to follow the operation of the circuit for one switching cycle. Referring to Fig.. At some time just prior to t0, a signal from the control IC turns OFF the SR. At t0, the PWM signal turns ON the main switch and the inductor current starts to transition from the SR to the switch. At t1, the SW node voltage rises above the Vout voltage level and the current in the switch and the inductor begins to increase. At t, the switching transition is complete. At t3, the PWM signal turns OFF the switch, and the inductor current begins to transition to the body diode of the SR. At t4, the SW node voltage falls below Vout and the current in the SR and in the inductor begins to decrease. At t5, the transition is complete and the inductor current continues decreasing. At this time, the current is still fully in the SR body diode. At t6, the gate signal driving the SR turns ON the SR and the current transitions from the body diode of that MOSFET to its channel. Evidence of this is the SW node going closer to GND than the body diode voltage of the MOSFET had allowed. Notice that during the t6-t7 interval, the voltage across the R DS(on) of the SR decays because of the decay of the current in the inductor. At t7, the SR gate signal turns OFF the SR and the inductor current transitions from the channel back to its body diode. At t8, the cycle starts again with the PWM signal turning on the main switch MOSFET. 5-

111 PWM Switch Synchronous Rectifier Switch Current GND Synchronous Rectifier Current Synchronous Rectifier GND Vin Switch Node GND Average Vout Inductor Current t0 t t1 Ts t6 t3 t4 t5 Fig.. Synchronous buck converter waveforms. B. Discontinuous Current Operation One of the key differences in circuit operation between a synchronous and a non-synchronous converter occurs at light loads when the converter s DC load current is less than half the magnitude of the peak-to-peak ripple current ( Iout) in the output inductor. In a nonsynchronous buck converter, when the inductor current valley attempts to go below zero, current no longer flows due to the rectifier diode s blocking effect (see Fig. 3). In this condition, the inductor is running discontinuous because current flow is interrupted. When this occurs at t4, the SW node rings up to the output voltage (t4 to t5) and settles at that level until the next switching cycle begins at t6. This low energy 5-3 GND t7 t8 Average Iout ringing is generated by the energy in the inductor resonating with MOSFET parasitic capacitance. When the inductor goes discontinuous, the duty cycle required to maintain output voltage regulation is no longer simply the ratio of the output voltage to the input voltage, but is determined by the relationship: D L Zout Ts Vin Vout Vin Vout

112 PWM Synchronous Rectifier Switch Current GND Synchronous Rectifier Current GND Swtch Node Average Vout GND Inductor Current GND t0 t1 t t3 t4 t5 Fig. 3. Operation with discontinuous inductor current. t6 Notice that D is no longer a linear function of the input-to-output ratio. This is because the inductor acts as a current source feeding the output impedance of the converter. The issue that arises from this effect is that the closed loop gain of the converter is reduced, and is no longer a linear function. Care should be taken to verify loop stability and response characteristics under both conditions. The synchronous converter can either allow current to flow in only one direction as a nonsynchronous converter does, or, by allowing the synchronous rectifier to remain ON for the entire t3 to t5 interval, can operate so that current is allowed to flow in the reverse direction. The advantage is clear from the earlier discussion. If current is continuous in the output inductor then the output voltage remains a linear function of the duty cycle and the loop stability remains constant over the entire load current range. A disadvantage is that under light loads, there is now power dissipated in the channel of the SR MOSFET and in the inductor as current flows in the reverse direction. A second advantage to allowing reverse current to flow in the SR is that the converter is now capable of sinking current from the output if the output has excess energy. As a consequence, any power absorbed at the output of the converter while it is sinking current is returned to the input of the converter. To prevent the input supply from being pumped up, the input source must be capable of absorbing this excess energy. C. Cross Conduction and Gate Switching Delay In a synchronous converter, where devices are turned ON and OFF alternatively, the potential exists for both devices to be momentarily turned ON at the same time, leading to a high shoot through current from the input source to the ground return and most likely, catastrophic results. To prevent this, a turn OFF to turn ON delay is added to the gate drive signals. In Fig. 4, the switch turn ON is delayed 5-4

113 slightly from the turn OFF of the SR, and the turn ON of the SR is delayed slightly from the turn OFF of the switch. As shown earlier, during these delayed times, current does not flow in the conduction channel of the SR, but in the parasitic body diode of the SR MOSFET. Too much time delay has the effect of increased power dissipation because the power loss in the body diode is usually much greater than the losses in the channel for a given current. The design goal is to minimize the amount of time to delay from the turn OFF of one device to the turn ON of the other without causing cross conduction. Unfortunately, the required delay is not a fixed requirement. Output load current, MOSFET drive capability and MOSFET device characteristics all influence delay, and so a self adjusting (or adaptive) method is necessary to avoid having to set a relatively long period of time. In the adaptive approach, the switch node (SW) or a MOSFET gate signal is monitored for the crossing of a pre-determined voltage level. When the node crosses that level, then the device being monitored is assumed to be OFF, and so the next device is allowed to turn ON. While this approach compensates for component and load variations, it is also a reactive approach one event has to occur before the next step can take place. There is an inherent delay in this approach, as the signal has to propagate through the control IC. When the turn-on of the MOSFET is included, this delay may be as long as 50 ns to 75 ns. PWM Switch Synchronous Rectifier Total Synchronous Rectifier Current GND Diode Current GND Channel Current GND Switch Node Vout GND t0 t t3 t1 t5 t7 t4 t8 t6 Fig. 4. Waveforms of current through MOSFET junction & body diode of synchronous rectifier. 5-5

114 SW Node Vin Main Switch Vout Synchronous Rectifier MOSFET Ld Cdg GND Driver Lg Rgi Cds Channel Conduction Body Diode Conduction Monitor Level Cgs Ls Fixed Delay Adaptive Delay Predictive Delay Fig. 5. Delay time for three approaches. As switching frequencies continue to climb to the MHz range and output voltages creep lower, a new predictive approach is used to further reduce power loss. By monitoring the switch node as it transitions below a ground reference, (monitor level in Fig. 5) the control IC determines whether the body diode of the SR has begun to conduct. By using this information, the control IC then adjusts the delay for the next switching cycle to minimize or eliminate body diode conduction. This monitoring occurs continuously for both edges of the SR s conduction interval, assuring the optimum delay period is only one cycle away. Fig. 5 is a simplified illustration showing the relative delay times for the three approaches. D. Synchronous Rectifier Parasitic Turn On Another issue related to synchronous buck operation is parasitic turn-on of the synchronous rectifier MOSFET. Since the nature of low voltage converters requires the use of low gate threshold MOSFETs, care must be taken to insure that the SR is not turned ON inadvertently. The failure mode is this: High dv/dt on the SW node when the SR is turned OFF can raise the voltage on the SR gate (through capacitive coupling from the drain-to-gate) to the point where the SR is momentarily turned ON. Refer to Fig. 6 for the following discussion. Fig. 6. Synchronous rectifier parasitic components. In the box labeled Synchronous Rectifier MOSFET, Lg, Ld and Ls represent the inductance inherent to the device package leads. The gate resistor Rgi is the characteristic MOSFET gate resistance and is dependent on the type of MOSFET and its construction. The three capacitors are also inherent to the device construction and their values are found in manufacturers data sheets. When the SW node starts to rise, the drain voltage of the SR MOSFET rises as well. The rate of rise causes currents to flow in the parasitic MOSFET capacitors. Current through Cdg must go into either Cgs or be shunted through the gate lead and returned to GND by the driver. Current not shunted around the MOSFET causes the voltage on Cgs to rise. If this voltage rises to the threshold voltage of the MOSFET, the rectifier MOSFET turns on and shoot through current flows. The oscilloscope waveform in Fig. 7 shows an SR gate spike during the rising edge of the SW node. The best line of defense to parasitic turn ON is to keep the impedance from the gate to source of the SR as low as possible. Close attention should be paid to the layout of the gate drive circuit. The circuit should be low resistance, (a wide, short track) and low inductance (a wide track with a GND return path directly beneath it). Minimize the loop area in the circuit and use a ground plane effectively. Also, use a driver or 5-6

115 control IC that has a very low pull down (or sinking) impedance. Also, reducing the rate of rise of the SW node with either a snubber or by limiting gate drive to the main switch can help to minimize the problem. In Fig. 7, the gate voltage of the SR can briefly exceed the minimum specified threshold of a low Vgs MOSFET (about 0.4 V). Since the amount of time that the gate voltage spends above the threshold is small, at roughly 5 ns to 6 ns, the results are perfectly acceptable in most applications. If the SW node dv/dt were increased much beyond the above value or extended in duration, significant shoot through current could occur. Appendix E gives a simulation model helpful for predicting parasitic turn ON. Bottom Gate 1 V/div t - Time - 50 ns/div Fig. 7. SR gate waveform. SW 1 V/div dv/dt Bump III. CONVERTER COMPONENT SELECTION A. Inductor Selection With the large number of companies competing to sell size optimized, high performance inductors for DC/DC applications, an in-depth understanding of magnetic component design is typically not required for a successful design. It is still important to consider how the operating conditions of the supply affects the inductor s performance in order to minimize losses and avoid core saturation. The optimum inductor value for a particular supply is dependent on the switching frequency, transient performance, and the conduction losses in the inductor and other components. Some of the merits for selecting a low vs. high inductor value for a given core size and geometry are summarized below: Benefits of Lower Inductor Values Low DCR: lower DC inductor losses in windings Fewer turns: higher DC saturation current High di/dt: faster response to load step / dump (see Section F) High di/dt: fewer output capacitors required for good load transient recovery Benefits of Higher Inductor Values Low ripple: lower AC inductor losses in core (flux) and windings (skin effect) (see Appendix B) Low ripple: lower conduction losses in MOSFETs (see Section B) Low ripple: lower RMS ripple current for capacitors Low ripple: continuous inductor current flow over wider load range (See Section B) In general, lower inductor values are best for higher frequency converters, since the peak-topeak ripple current decreases linearly with switching frequency. A good rule of thumb is to select an inductor that produces a ripple current of 10% to 30% of full load DC current. Too large an inductance value leads to poor loop response, and too small an inductance value leads to high AC losses. The losses in the inductor are composed of conduction losses due to RMS current and to a lesser degree, AC losses in the wire due to skin effect, and hysteresis/eddy current losses in the core (A further discussion is in Appendix B). The RMS conduction loss due to the winding resistance is: PLRMS ILRMS RL PP IL ILRMS Iout + Where 1 5-7

116 Manufacturers offer several inductors for a particular core, where the lower inductance values have fewer turns of heavier gauge wire ( L N ) than the higher values. Because of this relationship, lower inductor values have less winding resistance but create higher RMS currents as the ripple increases. B. Switch MOSFET The primary tradeoff in selecting a MOSFET is to balance package type, cost, and power loss. These three factors are usually related, and so the designer needs to weigh the priorities. For small size, D-PAK and SO-8 packages are commonly used in on board DC/DC converters. The final choice depends on the ability for the package to adequately remove heat generated by the MOSFET die in the application, and to transfer it to the environment in order to keep the junction temperature within acceptable limits. When selecting the MOSFETs, there is a fundamental choice of whether to use a N- channel or P-channel device for the upper switch. N-channel MOSFETs have the advantage of lower on resistance for a given die size and often have lower gate charge. They also tend to be relatively inexpensive. Their chief drawback is that they need a bootstrapped drive circuit or a special bias supply for the driver to work, since the gate drive must be several volts above the input voltage to the converter to enhance the MOSFET fully. Conversely, P-channel MOSFETs have simpler gate drive requirements. They require that their gate be pulled a few volts below the input voltage for them to be turned on. Their disadvantage is that their cost is higher as compared to their N-channel counterpart for an equivalent R DS(on), and they generally have slower switching times. The losses in the upper switch MOSFET are found by breaking down the losses into various elements: conduction losses, switching losses, and gate losses. The conduction losses are a function of the load current, the switching frequency, and the value of the ripple current. The peak-to-peak ripple current in the output inductor is: ILPP ( Vin Iout [ RDS( on ) SW + RL] Vout) D Ts L Adding the contribution to the overall current in the upper MOSFET, the RMS of this current is used in determining the AC conduction loss. and ISWRMS IL D ( Iout + PP 1 PSW conduction ISWRMS RDS( on ) SW The values of the output inductor and the switching period have a direct impact on the conduction loss. For a fixed frequency, the value of the inductor determines the amplitude of the peak-to-peak ripple current, which, as the equations indicate, affects the conduction loss. Fig. 8 shows a curve of power loss in the switch and SR for ripple current values at a single switching frequency. Notice the power loss increases by about 5% with 30% ripple current, confirming that the ripple current should be kept below 30% of the overall load current. Normalized Switch and SR Power Loss (W) I RIPPLE /I LOAD (%) Fig. 8. MOSFET Power dissipation for various ripple current values at a single switching frequency. ) 5-8

117 The switching loss in the MOSFET is calculated by this lengthy statement. PSWswitching ( QgdSW + QgsSW ) ISW pk Ig Vin Fs QossSW + QossSR + Here the impact each term has on switching loss can be seen. Notice that the Qoss of the synchronous rectifier plays a minor role in the losses of the switch. The final power loss is associated with driving the gate: PgSW QgSW Vg Fs In each of the three loss equations, there is frequency dependence. Fig. 9 shows a set of typical curves of losses in a switch MOSFET as a function of switching frequency in a typical application. Clearly, the gate losses and the switching losses show the most variation with switching frequency. C. Synchronous Rectifier Selection The conduction losses in the Synchronous Rectifier (SR) are comprised of two elements: The losses through the channel of the MOSFET, and in the parasitic body diode. In the body diode, the average power loss is Tdelay1 + Tdelay Pdiode avg Vfr Iout Ts Where Tdelay1 and Tdelay are the gate driver and MOSFET turn-on delay times and are the only times current flows through the body diode. The RMS current in the SR is found in a similar fashion to that in the upper switch, however instead of using (1-D) as the duty cycle, the time delay is subtracted from the SR conduction time. This is the amount of current that is reduced in the channel of the device. ISRchannelRMS Tdelay1 Tdelay ILpp (1 D ) ( Iout + Ts 1 ) 0.45 P LOSS(switch) - Switch Loss - W Conduction Loss Switching Loss Output Loss Gate Loss k 1 M f - Frequency - Hz Fig. 9. Upper MOSFET losses as a function of frequency. Moreover, the loss is PSRchannelconduction ISRchannelRMS RDS( on ) SR While the conduction loss in the SR channel is reduced by increasing the time delays, the loss in the SR device as a whole increases because the ON loss in the SR channel is usually less than the loss in the SR body diode for the same current. The switching loss in the gate of the SR is found in a similar manner to that of the upper MOSFET. PgSR QgSR Vg Fs Figure 10 shows these losses as a function of switching frequency. 5-9

118 0.30 MOSFETs. Reference [1] provides background information. P LOSS(switch) - Switch Loss - W Channel Conduction Loss Conduction Loss Gate Loss 100 k 1 M Vgtdrv Qg Fs Pgtdrive Rghi Rglo + Rghi + Rg + Rgi Rglo + Rg + Rgi The gate drive loss is a function of operating frequency, the driver s internal resistances, the MOSFET gate charge requirement and the internal MOSFET gate resistance. See Fig. 11. Driver equivalent switch and resistance Gate Drive Voltage f - Frequency - Hz Fig. 10. SR losses as a function of switching frequency. For illustrative purposes, the curves are plotted with a gate drive delay time of 0 ns and 10 A of current. With this delay time, the conduction losses have significant frequency dependence. The SR diode s power loss increases with frequency at a rate higher than the decrease in loss in the MOSFET s channel. By comparison, with only ns of body diode conduction, the curves would be essentially flat over this frequency band. PWM Gate Drive Rghi Rglo Rg Switch or Synchronous Rectifier Rgi MOSFET D. PWM Controller Selection In selecting a PWM controller IC, the overall DC/DC converter s design criteria needs to be considered. Some key parameters are: Operating frequency Voltage amplifier GBW Reference voltage and tolerance Package size Gate drive capability Phasing of the gate drive to be compatible with P-Channel/N-Channel switch selection Plus any other features specific to the application, such as clock synchronization, power good indicators, soft-start, etc. From a loss standpoint, the IC dissipates power in the process of driving the two Fig. 11. Gate drive equivalent circuit. For low voltage applications, there are a limited number of MOSFETs available that have R DS(on) values specified with a.5 Vgs. One method that opens the doors to a larger selection of MOSFETs is to use a charge pump to boost the input voltage to a higher voltage, say 4.5 V. This allows use of lower R DS(on) MOSFETs that have a Vgs rating at a higher voltage. When using a charge pump, there is increased loss in the gates of the MOSFETs (because of the higher voltage) and the losses in the control IC increases due to the increased gate drive energy and the efficiency (about 80%) of the charge pump. The benefit is that the R DS(on) of a MOSFET is lower at a Vgs of 4.5 V than at.5 V, giving lower conduction loss. 5-10

119 Fig. 1 shows the total power loss for a DC/DC converter for two types of MOSFETs, with and without using a charge pump. Even though the losses increase with operating frequency for both cases, there is a distinct difference in losses and in the slopes for a MOSFET operated at a.5 Vgs and the same MOSFET operated with a higher Vgs. The tradeoff a designer must make here is to decide whether it is a better solution to use a less expensive MOSFET and a charge pump, or use a more expensive part that has a lower R DS(on). The Si4836DY, which has a low R DS(on), benefits from the use of a charge pump only at low switching frequencies. At higher switching frequencies, the power loss in the charge pump and in driving the MOSFET gates is higher than the benefit gained by having a lower R DS(on). By contrast, the Si4866DY, which has a higher R DS(on) and lower gate charge requirement, benefits from the use of a charge pump at all operating frequencies. This is because the decrease in losses due to driving the gate to a higher voltage, are greater than the increase in losses incurred in getting the higher gate drive voltage. P LOSS - Power Loss - W Without Charge Pump Si4866DY With Charge Pump Si4866DY With Charge Pump Si4836DY 100 k 1 M f - Frequency - Hz Without Charge Pump Si4836DY E. Capacitor Types and Characteristics When selecting capacitors, power loss, size and circuit noise are primary concerns. For a capacitor placed on the output, the value and type of capacitor also influences the loop bandwidth and load transient response of the converter. The number of capacitor types available for use in power supply applications has increased over the last decade, resulting in a broad selection of parts. Common capacitor types used in low voltage DC/DC converters are aluminum electrolytic, tantalum, and ceramic. Some of the newer chemistries include solid polymer aluminum (SPA), aluminum with an organic electrolyte (OS-CON), and tantalum with organic electrolyte (POSCAP). While the variety should be viewed as a positive trend, a greater burden is placed on the power supply designer to understand the cost, availability, and performance characteristics of the various types. To make matters worse, it is often impossible to do a lineby-line comparison of parameters between different manufacturers or types, since the datasheets do not present information in a uniform matter. Table 1 compares the performance of the various types with respect to size; ripple performance, and relative cost. It should be noted that there are several manufactures for many of these types, and the particular part number listed in Table 1 is only a representative sample. One method commonly used to quantify the effectiveness of a capacitor is the product of capacitance and voltage rating per volume (Volt x µfarad/mm 3 ), listed in the 4 th column of Table 1. Ceramic and tantalum have the best volumetric capacitance followed by conventional electrolytic. Fig. 1. Power loss comparison with and without using a charge pump. 5-11

120 TABLE 1. CAPACITOR TYPE RELATIVE COMPARISONS Capacitor Type Value (µf) Voltage (V) Current (A) Case Size (mm) Volt x µf /Volume ESR (ESR*µF) ESL Aluminum Electrolytic/Sanyo Dia. x mω (150) CA/CG 06MV nh OS-CON SP Series/Sanyo Dia. x mω (1) 4SP1000M 4 nh Solid Polymer /Cornell Dubilier ESRE181M04R POSCAP/Sanyo 4TPE0MI Tantalum/Kemet T495X477(1)006AS Ceramic /TDK C35X5R0J476M Ceramic/TDK C01X5R0J106M x 4.3 x mω (.7) 3 nh x 4.3 x mω (.) 3 nh x 4.3 x mω (3.5) 3 nh x 3. x m (0.047) 0.5 nh x.0 x 1. m (0.0) 1 nh Relative Cost/Farad ESR is compared in the next column using a benchmark of ESR x µf, because the capacitor values are different between types. If multiple capacitors are placed in parallel, the ESR and ESL values can generally be divided by the number of devices, although the PCB interconnect limits the improvement at some point. In the ESR category, ceramic is the clear winner followed by solid polymer and POSCAP. Conventional aluminum has relatively poor ESR performance, making its use difficult for low voltage/high current systems. The final column is relative cost with aluminum electrolytic used as the benchmark. The cost range represents an educated guess for the technology and should not be used as a guide for a purchasing manager. As it turns out, the low ESR ceramic types have the highest cost per Farad, making their use expensive for bulk storage. Conversely, the inexpensive aluminum electrolytic types have the highest ESR and a low ripple current rating. The correct choice of capacitor for a particular application is on the shoulders of the designer who must weigh the various tradeoffs. It is possible in some cases to get the benefits of multiple technologies by mixing capacitor types. This can lead to a cost effective, high performance design, but may complicate the feedback analysis. R CAP - Impedance - Ω µf OSCON 180 µf Solid Polymer 10 µf Ceramic 470 µf Tantalum f - Frequency - khz Fig. 13. Impedance curves for various capacitor types and values. Once the capacitor types are selected, it is a good idea to scour the datasheet for additional information that may affect the design. This information should include (but not be limited to): leakage current, voltage coefficients, temperature and moisture effects, shelf/lifetime ratings, mechanical vibration, and failure modes. It is also a good idea to get a plot of capacitor impedance as a function of frequency as shown in Fig. 13. These graphs are found in some datasheets, but it is often necessary to use an 5-1

121 impedance analyzer to obtain the plot for a particular value and voltage rating. The graphs are very useful in obtaining the ESR, ESL, and resonant frequency for the capacitors. Sizing the Input Capacitor for Ripple Since the current delivered to the DC/DC converter is an average (DC) current and the current in the switching MOSFET is pulsating, a large capacitor is placed at the input of the converter to average the input current. To reduce conducted EMI on a system board it is advisable to contain the switching current in a small loop within the layout of the printed circuit board. (See Appendix C). The input capacitor provides a low-impedance voltage source for the converter and helps to filter the pulsating current. Important parameters in the selection process include capacitance value, ESR, ESL, and RMS current rating. Iin Ic (sw OFF) + Ic (sw ON) Cin Isw Ic + Iin SW1 Io SW Lout Ich Cout Fig. 14. Current flow in a buck converter. Io Iload The current in the input capacitor is composed of two elements. During the ON time of the switch, the capacitor current is the switch current less the DC input current, and during the switch OFF time, the capacitor is recharged by the input source. At a fixed input voltage, the steady state amp-seconds of the input capacitor balance. To find the power dissipation of the input capacitors, the two elements are combined and the RMS value is found. (See equation at bottom of page) Using this value and the ESR of the input capacitor gives the overall loss. Pincap IincapRMS Resr Notice that the impact the peak-to-peak contribution to the ripple current has on the overall current in the capacitor, even at high ripple current ratios, is relatively small. Smaller inductor values and/or lower switching frequencies leads to higher peak-to-peak currents, but that has little impact on the input capacitors. If a DC/DC converter is designed to operate over a wide input voltage range, then the ripple current is highest at the input voltage that places the duty cycle closest to 50%. (See Fig. 37 for a curve.) Once the RMS input current is established and a capacitor selected, the following equation is used to calculate the input ripple voltage due to capacitance and ESR as shown in Fig 15. D Lesl Vin pp Iin Resr + Iin + Iin Fs C Tedge The first two traces in Fig. 15 show the switch and input capacitor currents for a typical buck converter. The lower traces illustrate the effects of ESR, capacitance, and ESL on input ripple voltage. The current at the switching frequency across the capacitance and the ESR generates a low frequency ripple, and the fast edges created by the SW node across the ESL creates high frequency noise spikes. IincapRMS ( ISW Iin ) pk avg + ( ISW ) pp 1 D + ( Iin ) ( 1 D) avg 5-13

122 Care must be taken to insure that the peakto-peak ripple is not so large as to cause the UVLO circuit in the PWM controller to inadvertently shut down the converter. Also, noise spikes generated by the ESL should not be so large to cause intermittent operation of the controller or EMI. Switch current Cin current Cin Ripple Voltage ESR C ESL Fig. 15. Typical input current waveforms and input voltage ripple due to ESL and ESR. F. Selecting the Output Capacitor The output capacitor is chosen to minimize output noise voltage and to guarantee regulation during transient loads. Knowing which of these goals is predominant helps greatly in selecting the right component for the design. Selecting based on Load Transient Response Current transients at the output are a function of the load s characteristics and can be on the order of 100 A/µs. The value, ESR, and ESL of the output capacitor determines the magnitude of undershoot or overshoot during a transient as illustrated in Fig. 16. The top traces show the inductor and load currents on the same axis, during a sudden load step increase and decrease. The bottom trace represents the transient seen at the output of the converter. The initial transient spike during a step load change is due to the di/dt of the load being greater than the inductor can support. The amplitude of the initial spike is given below where Istep is the magnitude of the step and di/dt is the slope. The ESR and ESL values refer to the combined effect of the output capacitors and PC board traces. The initial voltage spike can be minimized with the addition of ceramic capacitors. di Lesl V spike I STEP R esr + dt As shown in Fig. 16, the undershoot which follows the initial spike, results from the load current being supported by the output capacitor, awaiting the inductor current to catch up. The amount of time required for the current in the inductor to match the load current depends on inductor value, maximum duty cycle, and feedback loop response. If the feedback loop is designed aggressively, the buck stage can reach full duty cycle quickly, resulting in the minimal undershoot: V under L I STEP Cout D (Vin Vout ) MAX The minimum overshoot during a load drop is calculated in a similar fashion. Where undershoot is affected by the difference between Vin and Vout, the overshoot is only affected by Vout. L I STEP Vover Cout Vout The above equations assume that the step di/dt is longer than the inductance can support given the small Vin - Vout voltage differential, necessitating some amount of bulk storage capacitance at the output. If the converter has a small enough L, or a benign enough load step requirement, the bulk storage may not be necessary, in which case a design using only ceramic capacitors may be achieved. 5-14

123 A step increase in load is primarily supported by the output capacitors, but is partially supplied by the input. Interestingly, load drops on the output have little effect on the input capacitor since the high side switch is turned OFF during Output Currents Vout AC Coupled Iload ESL ESR Cout & ESR ESR ESL Iinductor Cout & ESR Fig. 16. Vout undershoot and overshoot during a load transient. Output Capacitor Ripple and Power Loss It is good design practice to compare the steady state inductor ripple current with the output capacitor s ripple current rating. As with the input capacitor, only the AC component of load current generates power loss in the output capacitor. The voltage ripple is given by: Vin Lesl IL Vout PP IL Resr + + L Fs Cout 8 0 A the transient. The larger effect is determined by how well the output capacitors can absorb the stored energy in the inductor when the load is suddenly removed. IV. DESIGN EXAMPLE To illustrate the design of a synchronous buck DC/DC converter, the concepts presented are used to design a 3.3-V input, 1.-V output converter capable of delivering up to 10 A of load current. The approach taken is to first optimize for power density and second for cost. This means low power dissipation and small size are predominantly the design goals. The PWM controller used in this example is the TPS This part is chosen for its small size, 600kHz operating frequency, its strong gate drivers, and its Predictive Delay Gate Drive TM circuitry. The next step is to estimate the conversion duty cycle. D est Vout Vin % The output ripple current also generates a power loss in the output capacitors. Since the ripple current is a simple saw tooth waveform, the power loss is Poutcap IL RMS R esr

124 TABLE. POWER LOSS CALCULATIONS Switch MOSFET Si4836DY FDS6574A IRF7459 Si4866DY Units R DS(on) at 100 C Ohms Qg.00E E E E-08 Coulombs Qoss 9.4E E E E-09 Coulombs Coss.80E-09.1E E E-09 Farads Qgd 5.80E E E E-09 Coulombs Qgs 4.44E E E-09.56E-09 Coulombs Number of FETs Rg Ohms Synchronous Rectifier MOSFET Si4836DY FDS6574A IRF7459 Si4836DY R DS(on) at 100 C Ohms Qg.00E E E-08.00E-08 Coulombs Qoss 9.4E E E E-09 Coulombs Coss.80E-09.10E E-09.80E-09 Farads Vfr Volts Diode Qrr 4.40E E E E-08 Coulombs Number of FETs Rg Ohms Duty cycle 38.33% 39.43% 4.57% 38.80% I inductor ripple peak-peak Amperes IswPEAK Amperes IswRMS Amperes IsrRMS Amperes IsrAVG Amperes I_incapRMS Amperes Switch MOSFET Conduction loss Watts Gate loss Watts Switching loss Watts Output loss Watts Total SW FET Losses Watts Synchronous Rectifier MOSFET Channel conduction losses Watts Diode conduction losses Watts Gate losses Watts Diode recovery loss Total SR FET losses Watts Inductor loss Watts Switch gate driver loss Watts SR driver loss Watts Output capacitor loss Watts Quiescent IC power loss Watts Snubber loss Watts PCB loss Watts Preliminary power loss Watts Input capacitor loss Watts Overall power loss Watts Converter efficiency 86.3% 8.8% 78.7% 86.7% 5-16

125 A. Inductor selection Using the 10-0% ripple current rule-ofthumb, we get the following range of values for the inductor: (see equation below) To illustrate the tradeoff between ripple current and inductor DC resistance, the converter efficiency over the load range is compared for four inductors (0.47 µh/ mω, 0.68 µh/.5 mω, 0.8 µh/3 mω, 1.0 µη/3.5 mω) from Vishay s IHLP-5050CE series (see Fig. 17). These low profile inductors have a case size of 13 mm x 13 mm x 3.5 mm. In this comparison, the converter with the low value/low DCR inductor has lowest overall losses at full load where the high value/high DCR inductor performs better at light load. The 0.68 µh inductor is selected for our example because it gives good efficiency over a broad load range. If a physically larger inductor were selected, then the DCR would be lower and a higher inductor value would give lower ripple and therefore lower light load losses. If the converter were designed for a nominal 6 amps of load current, then perhaps the 1.0 µh inductor would be a better choice because it yields better light load efficiency. Efficiency (%) µh 0.68 µh 1.0 µh 0.8 µh I - Current - A B. MOSFET Selection In the earlier discussion, it was shown that the losses in the upper MOSFET, the lower MOSFET, and the gate driver were all interrelated. One method to choose the best MOSFETs for the converter is to compare the power dissipation values for a number of different MOSFET types. A survey of the industry finds a number of MOSFETs in SO-8 packages that have their R DS(on) values specified at.5-v Vgs. MOSFETs are selected from three vendors and the calculations outlined in Section 3 are entered into a spreadsheet (Table ). Note that manufacturers specify data sheet parameters somewhat differently, causing lab results to slightly differ from the results given here. In the upper section of the table, the MOSFETs are listed with the values used in the calculations. The same MOSFET is used as the switch and as the SR for three of the cases. In the fourth case, a low R DS(on) MOSFET is chosen for the SR, and a MOSFET with a low gate charge is chosen as the switch. Comparing the MOSFETs, the Vishay Si4836 has a very low R DS(on) and should have the lowest conduction losses. At the other end of the spectrum is the IRF7459. This part has a higher R DS(on) and a much lower gate charge, and so it has lower power loss at high frequencies. The last column shows the Si4836 as the SR, and a low gate charge Si4866 as the switch. This combination (after many more comparisons than shown here) has the lowest overall power loss. The middle portion of the table shows the results of current calculations. As expected, the higher R DS(on) devices create the need for higher duty cycles. By including the loss elements in the calculation of duty cycle, the effect that the R DS(on) and inductor resistances have is noticeable. Fig. 17. Overall converter efficiency using various inductor values with a common core. ( Vin Vout) D Ts ( ) L 0.63to1.6 µh Iout 1to A 5-17

126 Vout + Iout D Vin Iout ( R1 + RDS( on ) SR) ( R SW R SR) DS( on ) DS( on ) In the bottom portion of the table, the losses are calculated and combined. Notice for each of the devices, the varying amount of power loss in each category. Taking the switching losses as an example: Because there is a finite amount of time it takes to turn OFF the upper switch, and even though the voltage across it is low, the current is relatively high and the losses significant. The switch loss includes the loss due to driving the output of the SR. Since the Qoss is small, the voltage is low, and the operating frequency is moderate, the additional power loss is minimal. The Predictive Gate Drive technology in the TPS40003 limits the body diode conduction in the SR MOSFET to almost negligible levels. This means that since the body diode conduction period is so small, on the order of ns, then the power loss in the body diode is about 3 mw. By contrast, a converter operating at this frequency with 50 ns of body diode conduction time would dissipate 75 mw! Without this power loss reduction, it is unlikely that an SO-8 package could be used because the power dissipation would be too high for the package to effectively dissipate. Interestingly, selecting the Si4866 as the switch gives the lowest overall loss. Even though the conduction losses are higher than the Si4836 (as in the first case), the lower switching, gate, output and driver losses more than compensate. C. Input Capacitor Selection The losses in the converter are combined and the average input current is found. With this, the RMS ripple current in the input capacitors is then calculated to be a little over 5 A. To meet the ripple current (I_ incaprms ) requirements indicated in Table, two 4-V, 180-µF surface mount Solid Polymer (SP) capacitors are selected. They have a combined ripple rating of 7. A at 105 C, 7.5 mω of ESR, and 3 nh of ESL. Continuing down the table, the "Preliminary Loss" line indicates the calculation for ripple current in the 5-18 input capacitor. The power loss in (Input cap loss) is about 00 mw (100 mw each). To examine the magnitude of noise filtered by these capacitors, first look at the ripple at the fundamental switching frequency. Iin D Vin PP Iin Re sr + F Cin mv 600 Hz 360 µ F With a 10 ns switching edge on the SW node, the input spike voltage is: ISWpk VspikeINPP Lesl TEDGE 1.8V (SP capacitor only) 1.5nH 1 10 ns The major contributor to ripple is from the ESL and can be reduced by adding four 10 µf ceramic capacitors (with a combined ESL of 0.5 nh) in parallel. 1 Vin spikepp 0.5 nh 300 mv 10 n (SP + Ceramics) These ceramic capacitors are placed as physically close to the switch and SR MOSFETs as possible to minimize noise. D. Output Capacitor Selection For this application, suppose a A to 10 A load transient was possible with a 15 A/µs slope. A 470 µf output capacitor (15 mω ESR, 3 nh ESL) is selected because it has the same case size as the input capacitors. The resulting minimum under and overshoots are calculated below: L I STEP V under Cout DMAX (Vin Vout ) 0.68µ mv 470 µ 0.9 ( )

127 L I STEP 0.68 µ 8 V over 39 mv Cout Vout 470 µ 1. For this example, the low inductor value and high capacitance values yield a small voltage excursion. The actual values of under and overshoot may be higher depending on the response time of the feedback loop. Two 10 µf ceramic capacitors are added, with 1 mω total ESR and 0.5 nh ESL, to reduce the ESL spike as shown. Note that this calculation does not include printed circuit board interconnect parasitics, which generally serve to increase the spike: di Lesl Vspike ISTEP Resr + dt 15 A µ s (SP Only) ( 10 ) n 165mV mv (SP + Ceramics) The peak-to-peak ripple voltage during steady state operation is reduced significantly by the addition of the ceramic capacitors: The impedance of the capacitors at the switching frequency plus the ESR gives the output voltage: IL Vout PP PP IL PP R esr + 8 F Cout mV k 470 µ The power loss in the output capacitor is given in Table. E. Thermal Design The temperature rise of the components is the next to be determined. The temperature rise of the MOSFETs and the PWM IC is dependent on the PC board layout and the heat sinking afforded by device packaging. These are rough estimates that need to be verified by thermal imaging or direct measurement before the application is committed to production. Temperature rise in the high current traces on the board should also be predicted; this is discussed in Appendix C. Control IC The TPS40003 uses a 10 pin MSOP PowerPAD package where the die is attached to an exposed heat slug (Fig. 18) that should be soldered directly to a ground plane []. With an inner layer ground plane of 3 in, the specified junction to ambient thermal resistance (θja) is 60 C/Watt (the junction to case thermal resistance (θjc) is 5 C/Watt). θja is heavily dependent on the ground plane area and smaller planes results in an increased θja. As a comparison, a conventional 10 pin MSOP package has a θja of 40 C/Watt and a θjc of 40 C/Watt. The total gate drive losses are calculated to be 5 mw, and the quiescent power loss is on the order of 16 mw which results in a.5 C of rise. A much smaller ground plane can be used for the controller in this case. LEADFRAME (COPPER ALLOY) IC (SILICON) DIE ATTACH (EPOXY) LEADFRAME DIE PAD - EXPOSED AT BASE OF THE PACKAGE MOLD COMPOUND (EPOXY) Section View of a PowerPAD(tm) PACKAGE Fig. 18. PowerPAD section view. MOSFETs The SI4836DY and Si4866DY MOSFETs are in conventional SO-8 packages that have a θja of 67 C/Watt while mounted on a 1 in plane. The main switch dissipates 503 mw at full load, resulting in a temperature rise at the junction of 33 C. The synchronous rectifier dissipates 305 mw, yielding a 0 C rise. The die of the MOSFETs and controller should be kept well below 150 C for reliability purposes, because MOSFET R DS(on) increases with temperature and care should be taken to avoid thermal run-away. Capacitors The temperature rise of a "black body" depends on many factors [3] ; the placement of the component in airflow, its mounting direction, and 5-19

128 its surface area to name a few. To approximate the temperature rise (in degrees Centigrade), this somewhat complicated expression is used. Filter Circuit Vout ht P Surface Area T rise 1.8 Where P is the power dissipated, ht is the height of the component (in millimeters) above the plane, and SurfaceArea is the area of the device (in mm ) exposed to the air. For the input capacitors, they dissipate 100 mw at full load, the exposed surface area is 18 mm, resulting in a heat rise of 36 C. The actual heat rise is likely lower because the capacitor leads are connected to large power and ground traces that conduct heat from the center of the package. Temperature rise in the output capacitor is small since it dissipates only 16 mw. Inductor The same formula is used to approximate the inductor loss. It dissipates 50 mw at full load, the exposed surface area is 351 mm, resulting in a temperature rise of 3 C. F. Feedback Loop Design The feedback loop is now designed for the example converter. The converter power stage frequency response characteristics are first determined, and then based on the resulting curves; a compensation network is designed to give the desired result. A feedback model for a voltage mode buck converter is shown in Fig. 19. Vin + PWM Gain (%/V) Compensation OSCON or other Capacitor w/esr * Ceramic helps at high frequency Σ + Control Voltage Fig. 19. Voltage mode control model. The PWM gain is found by the relationship: K PWM Vin Vramp Where Vramp is the 1-V peak-to-peak voltage of the ramp going to the PWM circuit. With a high input voltage of 3.6 V, the overall PWM gain is: K PWM dB The L-C filter gives the output voltage a double pole response to the output of the compensation network. F DP π 1 L f C f * 8.9 khz 5-0

129 The compensation network can be designed to have a crossover frequency either above or below the L-C filter's double pole frequency (F DP ). Crossing the loop below the double pole is easier to design since it only involves setting the overall gain and one pole. It does however, result in a ringing transient response because the feedback loop cannot respond as fast as the L-C filter rings. Crossing the loop above the double pole frequency requires more effort in designing the compensator but provides better transient response. In either case, good design practice dictates a phase margin of at least 45 degrees for proper damping. A factor to consider when crossing the loop above F DP is the zero introduced by the equivalent series resistance (ESR) of the filter capacitor. The main filter capacitor is an Solid Polymer type. The ESR is specified to have a maximum value of 10 mω. This yields a minimum ESR zero frequency of: 1 FESR π CF RESR 34 khz Since ESR (and therefore the ESR zero frequency) can vary, the variation must be considered when designing the loop compensation. A simple but effective approach to this problem is to design the compensation so that the loop crossover frequency with a maximum ESR capacitor does not exceed 0% of the switching frequency and that adequate phase margin exists for a low ESR capacitor. The following discussion assumes that F DP is at a lower frequency than the ESR zero of the output capacitor - which is usually the case. Since the converter operates at a nominal switching frequency (Fs) of 600 khz, then a reasonable target for a maximum loop crossover frequency is 100 khz. This value is less than 0% of Fs and should avoid major problems. Fig. 0 shows the gain plots for the various elements of the feedback loop. The line labeled "Filter & PWM Response" places the filter and PWM response curve flat at 11 db until the filter double pole (F DP ), where it decays with a 40-dB/decade slope. At the ESR zero frequency of the output capacitor, it changes to a slope of 0 db/decade. The maximum ESR response curve is shown by the dashed split-off from the solid (minimum ESR) response curve. It should be noted that the ceramic capacitors on the output do help to reduce the high frequency output impedance but contribute little to the compensation problem since they are not close in capacitance value to the main filter capacitor. In this example, they may be ignored for purposes of designing the feedback compensation. Gain - db K PWM 11 db Compensation Response F DP 8.9 khz khz B A C F p1 100 khz F p 00 khz 5 MHz GBWP Error Amplifier Limit Filter and PWM Response F z1 F z 8.9 khz -30 w/ ESR 0 mω w/ ESR 10 mω k 10 k 100 k 1 M Fig. 0. Line bode plots of filter, PWM and compensation amplifier response khz

130 The line labeled "5MHz GBWP Error Amp Limit" shows the upper limit of gain vs. frequency the compensation network can produce if the error amplifier has a GBWP limit of 5 MHz. The compensation network gain response must stay below this line because the error amplifier imposes a limitation on how high the compensation network response can go. With the desired maximum loop crossover frequency limited to 100 khz, the compensation gain should be no more than 1.5 db at 100 khz. The response should also have a +0 db/decade slope over the frequency range where the loop crosses zero for the range of ESR values. To construct the line Bode plot for the compensation response begin at the max loop crossover condition of 1.5 db at 100 khz (Point A) and go lower in frequency at a slope of 0 db/decade to a point about an octave below the minimum ESR zero frequency (Point B). In this case, the line is extended to F DP. Placing the start of the slope here insures that the two zeros of the compensation response have a chance to get the phase response of the overall loop into a comfortable position. To minimize DC error, the compensation response is set to a 0 db/decade slope below Point B. This provides the highest practical DC gain and the best load regulation. At the high frequency end of the compensation response (Point A), a pole is placed at the upper loop crossover frequency limit. This turns the compensation response to a "zero" slope and insures that the loop crosses at or below this point since the PWM and filter response here is on a negative slope. Finally, a second pole is placed at a slightly higher frequency (00 khz at Point C) to roll off high frequency gain at a known rate. This avoids the instability that results if the output ripple voltage, when amplified through the compensation network, produces a rising slope on the output of the error amplifier, which exceeds the slope of the ramp signal at the PWM. See Control Loop Cookbook by Lloyd Dixon [4] for more details. The desired loop compensation response described above is obtained using a "Type 3" compensation network as shown in Fig. 1. The zero frequencies are given by: 1 Fz1 π R4C R1R R eq R1 + R And the poles are:,fz 1, π Req C1 1 1 Fp1,Fp π R3C1 π R4C3 Vout R1 R C1 R3 Vref C + C3 R4 Vcmp Fig. 1. Type III compensator schematic. The gain of the compensator at the p1 is G p1 R eq R4 R3 R eq + R 3 R 4 R R eq eq + R R The poles, zero, and dominant gain are set at: F z1 F z 8.9 khz, F p1 100 khz, F p 00 khz G p1 1.5 db 1 The desired output voltage and reference voltage at the non-inverting input of the error amplifier determine the ratio of the R1-R voltage divider: V ref V out R R 1 + R The reference voltage of the TPS40003 is 700 mv, and the desired output voltage is 1. V

131 By arbitrarily picking the value of 10 kω for R, then R1 must be 7.14 kω, (or 7.15 kω, in standard 1% values). Substituting in the above equations gives the following results: (Standard values are given in parenthesis). Req C 1 R3 R4 C C kω 7.15 kω 10.0 kω kω 1 π Req Fz 1 π C 1 F p1 Req R3 G z1 Req + R k 4.3nF ( 4.7 nf ) 370 ( 374 Ω ) 4.08 k ( 4.1 k ) 1 π R4 Fz1 4.4 nf ( 4.7 nf ) 1 π R4 F p 195 pf ( 0 pf ) The resulting compensator has the response characteristic shown in Fig The compensated system open loop response Bode plot in Fig. 3 shows the range of expected possibilities for the loop crossover frequency due to ESR variation. The minimum loop crossover frequency occurs at the minimum ESR zero frequency of the output capacitor. This is a direct result of positioning of the compensation response to limit the maximum loop crossover frequency in the maximum ESR case. In practice, the maximum crossover frequency is less than the maximum design of in the line Bode plot of Fig. 0 since that method approximates the actual frequency response with its asymptotes. If necessary, the loop bandwidth can be more tightly controlled by lowering the gain of the compensation network a few db and shifting the double zero frequency a little lower. The system here has a predicted crossover frequency (Fc) range of 34.4-kHz for a low ESR (mω) capacitor to a maximum of 65 khz for an output capacitor with a maximum ESR. The predicted phase margin ranges from 5 for a minimum ESR output capacitor to 79 for a maximum ESR capacitor. Gain - db Phase Gain k 10 k 100 k 1 M f - Frequency - Hz Fig.. Compensator gain and phase response Phase Margin - Degrees Gain - db Phase Margin (Low ESR) Phase Margin (High ESR) Gain (High ESR) Gain -135 (Low ESR) k 10 k 100 k M f - Frequency - Hz Fig. 3. System open loop gain and phase response Phase Margin- Degrees 5-3

132 3.3 Vin 560 µf x 0 kω 10 µf x4 1 ILIM BOOT nf 4.1 kω 3 FB COMP HDRV SW nf Si4866DY IHLP5050CE µh 1. Vout 0 pf 4.7 nf 4 5 SS/SD GND VDD LDRV 7 6 Si4836DY 1.5 Ω 5.6 nf 470 µf 10 µf x 7.15 kω 374 Ω 4.7 nf 10.0 k Fig. 4. Final DC/DC converter schematic. V. TEST RESULTS The DC/DC converter discussed in Fig. 4 was built and tested. The following waveforms show some of the issues discussed in the body of the text. V GATE - Voltage - V SR Gate t- Time - 1 µs/div Fig. 5. Gate drive waveforms. Top Gate In Fig. 5 and Fig. 6, the relationship of the gate drive signals for the high side switch and the SR, along with the relationship to the SW node can be seen. Note the slight bump in the SR gate waveform as the SW node rises. Load current in this case is 8.5 A. SW node transition times are about 0 ns. The ringing on the SW node increases with current and is much less pronounced at lighter loads. Limiting the slew rate on this node helps to alleviate the ringing. For more information see Appendix C. V GATE - Voltage - V t- Time - 1 µs/div Fig. 6. Switch node waveform. 5-4

133 V GATE - Voltage - mv t- Time - 1 µs/div Fig. 7. Output ripple and noise. The measured output ripple and noise at full load was about 0 mv peak-peak. Averaging out the noise on the waveform shows approximately 15 mvpk-pk ripple, well within the maximum predicted 1 mv. Efficiency (%) Predicted Actual I LOAD - Load Current - A Fig. 8. Efficiency vs. load current. The efficiency curves track fairly well. Errors in calculation may be attributed to the method of calculating MOSFET losses, and to errors associated in calculating PCB losses. Gain - db Gain Phase k 10 k 100 k f - Frequency - Hz Fig. 9. Measured loop frequency response. The measure frequency response curves also track fairly well with those predicted. The crossover frequency is approximately 45 khz with 90 of phase margin. VI. CONCLUSION The design of low voltage DC/DC converters requires an understanding of a wide variety of issues and an understanding of how design decisions can have an effect in final converter performance. While the discussion here presented the basic concepts behind converter design, there are many other areas to expand upon. Appendix B discusses high frequency inductor issues. Appendix C describes how parasitic elements, in both the PC board layout, and in the components themselves, can contribute to causing potential circuit design problems. In Appendix D, there is a discussion of how to design a converter for very high load currents. Appendix E illustrates a schematic used to simulate the effects of parasitic turn ON Phase Margin - Degrees 5-5

134 Cdg Coss D Fs Ig Iout Iout Iswpk L Ld Lg Ls Pswconduction Qg Qgd Qgs Qoss RL R DS(on) sw R DS(on) sr Rg Rghi Rgi Rglo TEDGE Ton Ts Vfr Vin Vgth Vout Zout APPENDIX A. TABLE OF VARIABLE NAMES Drain-to-gate (aka."miller") capacitance of a MOSFET Coss of a MOSFET Operating duty cycle of the DC/DC converter. In an ideal converter, DVout/Vin In the practical case, component losses causes the duty cycle to be larger Switching frequency of the DC/DC converter MOSFET gate current AC Peak to peak ripple current in the output inductor. DC output load current Peak current in the upper, switch MOSFET Value of output inductor Package inductance of the drain pin of a MOSFET Package inductance of the gate pin of a MOSFET Package inductance of the source pin of a MOSFET Conduction loss in the switch MOSFET MOSFET total gate charge requirement MOSFET gate to drain charge MOSFET gate to source charge MOSFET output charge DC winding resistance of the output inductor Static R DS(on) of the upper, switch MOSFET Static R DS(on) of the lower, synchronous rectifier MOSFET Resistor placed in series with the gate driver and the gate of the MOSFET Equivalent gate driver pull up resistance Equivalent internal MOSFET gate resistance at the "Miller" plateau Equivalent gate driver pull down resistance at the "Miller" plateau Transition time of the switch node (SW) edge On time of the DC/DC converter during one switching cycle Switching period of the DC/DC converter and is 1/Fs Forward voltage drop across the synchronous rectifier's body diode when it is conducting current. This current is flowing in the source pin, and out of the drain pin. DC input voltage to the converter Gate turn ON threshold voltage of a MOSFET DC output voltage of the converter Output impedance seen by the converter. This impedance includes the impedance of the output capacitor(s) and the load 5-6

135 APPENDIX B. INDUCTOR CORE MATERIALS AND HIGH-FREQUENCY EFFECTS A. Inductor Basics Inductors require a non-magnetic gap in order to provide energy storage. In ferrite-based cores, this gap consists of a physical spacing between the core halves. The BH loop for a gapped and ungapped core is shown in Fig. 30, where field intensity (H) is plotted on the X-axis and flux density (B) is plotted on the Y-axis. The gap lowers the permeability (µ), causing the B-H curve to be stretched in the H direction, allowing higher currents to be supported without core saturation. In continuous current mode the inductor operates in a minor B-H loop as shown. The flux density in the core changes with applied voltage and time (V ON T ON or V OFF T OFF ) causing the field intensity and inductor current to change. Flux losses are proportional to the area of the minor B-H loop. Ferrite cores have low flux losses and can be used at frequencies as high as 1 MHz to MHz. Most inductors used in commercial DC/DC applications are of the ferrite variety, where shielded cores are often employed to minimize external fields. Ferrite cores have some disadvantages, however, such as low flux density (B MAX ), sharp saturation characteristics, fringing flux losses near the air gap, and reliability issues in high shock environments. L B µh µ N B MAX B V Ungapped Core Gapped Core µ gapped µ ungapped I OUT I ripple H I Fig. 30. B-H Curve showing minor hysteresis loop with continuous current If a more robust and possibly size-reduced solution is required, a "distributed" gap material can be used such as powdered iron or Magnetic's Kool-Mu. With these core materials, the stored energy resides in the iron or binder material rather than the air gap. An advantage of distributed gap cores is that they have a softer saturation characteristic when compared with gapped ferrite. Cores available in these materials are often toroidal in shape, lowering the external magnetic fields and fringing losses. They also come in a choice of permeability, allowing various Inductor values and DC currents to be supported. The powered iron cores perform well with pure DC currents, but the AC core losses make their use impractical above 300 khz. Kool-Mu cores offer lower losses with reasonable efficiencies up to about 700 khz. 5-7

136 Planar magnetic inductors are often considered for low profile applications, where the printed circuit board (PCB) traces are used for windings. This technique becomes more difficult at high currents due to the thin trace thickness and heating issues with inner layers. Practical planar magnetic inductors are often built on a small section of a custom PCB with thicker copper. B. Core Losses Core losses in the inductor are determined by the volt-seconds flux swing in the core (see Fig. 30), the frequency of operation, and the material used. With the push for higher frequencies, the selection of core material has a greater effect on power loss. The following equations predict the core losses for magnetics traditional P-Type ferrite material (>500 khz) with a newer high frequency K-Type: PL PTYPE f B (P-Material) PL KTYPE f B (K-Material) Where PL is given in mw/cm 3, f in khz, and B in kg. To illustrate the importance of proper core material selection, losses for P and K type ferrite materials are plotted against frequency in Fig. 31 for a 1cm 3 core with a minor B-H loop of 00 Gauss. Although inductor manufactures do not always provide information on core material, it is important to get information on core losses for high frequency designs. C. AC Wire Losses A portion of the AC loss in the winding of the inductor is generated by skin effect. [5] At high frequencies, the current in a conductor (in this case the inductor winding) flows at the surface of the conductor and not at the center, as if the current were flowing in a hollow tube. This means that the effective cross sectional area of a conductor at high switching frequencies is less than that at DC, and therefore the impedance at high-frequency is much higher than at DC. Fortunately, in a buck inductor, only the peak-to-peak portion of the ripple current is subject to this higher impedance. 30 P-Type 0 18 AWG 14 AWG P LOSS - Power Loss - W 1 K-Type Rac/Rdc AWG 4 AWG k 1.5 k k.5 k f - Frequency - Hz Fig. 31. P and K material losses vs. frequency for 1 cm 3 core with 00 Gauss B-H swing k 1 M 10 M f - Frequency - Hz Fig. 3. Ratio of AC to DC impedance in a copper wire as a function of frequency. 5-8

137 The amount of increase in AC resistance depends on the diameter of the conductor, the material, and the frequency. As frequency increases, the current flows closer to the outer walls of the conductor. Fig. 3 graphs the ratio of AC resistance to DC resistance in copper vs. frequency for four common wire gauges. Notice that the larger diameter wires lose their effectiveness at relatively low operating frequencies. For higher frequency or higher ripple current applications, multiple strands of finer wire, or a thin sheet of copper foil may be used to maintain a low resistance ratio. The following example helps describe how skin effect impacts losses. From a heating standpoint, a reasonable current density in a copper conductor is around 500 A/cm. For a 10-A load current, a conductor with a 0.00cm cross sectional area is required. From a wire gauge table, 14AWG wire should be used (Area 0.0cm, Rdc.0083 Ω/M). With an operating frequency of 600 khz, the equivalent AC resistance is Ω/M. If the AC RMS ripple current in the inductor is A, the total loss in the conductor is ( ) 996 mω/m). If the wire is 10 cm long, then the AC wire loss due to skin effect is about 100 mw. Although a lot of discussion in this appendix has been allotted to AC skin effect losses and AC core losses, the DC losses in the inductor dominate in most applications. The AC losses become more important at high frequencies or with high ripple currents. For more information, two recommended sources are Unitrode's Magnetic Design Handbook by Lloyd Dixon [6] and the Magnetics Incorporated website at APPENDIX C. LAYOUT ISSUES FOR LOW-VOLTAGE SYSTEMS In operation, a low voltage DC-DC converter is more complicated than basic theory would lead one to believe. There are operational issues that can crop up due to the PCB layout that may have an effect on circuit function and/or reliability. A few of these issues are discussed here. A. Trace Resistance Despite the recent improvements in power components and controllers, the resistivity (p) of copper used in PCBs remains at 0.67 mω x mil at room temperature with a 0.39% increase per C. Trace resistance is given below with the dimensions depicted in Fig. 33. Trace thickness (T) is typically specified by the number of ounces required to cover a square foot of board. For example, one ounce copper has a thickness of 1.4 mils (1mil inch). ρ L R T W Ifoward T - trace thickness W - trace width Ireturn S - trace separation L - trace length Fig. 33. Circuit trace geometry. 5-9

138 For the 3.3 V to 1. V converter discussed in the design example, " long x 00 mil traces on 1 ounce copper were used for the forward and return connections between the DC/DC output and load. Each trace has only 3 mω of resistance at room temperature. With the 10 A of load current, power loss is approximately 500 mw. A good design practice is to check the current density in each trace to guarantee that trace temperature rise is acceptable. One standard that is commonly used to specify temperature rise in PCB traces is MIL-STD-475E. This standard is used to derive the curves of Fig. 34, which plots trace width and the maximum allowable current for a 0 C temperature rise. This graph assumes that the copper is on the top or bottom layers (inner PCB layers have much lower ratings in MIL-STD-475E) and neglects the skin effect for the AC current component. The curves tell us that for the 10 A example above, a 0 rise in the trace is expected. 40 oz. I TRACE(max) - Maxumum Trace Current - A Trace Width - Inches 1 oz. Fig. 34. Current carrying of a copper PCB trace for a 0 C temperature rise. B. Trace Inductance Parasitic inductance is formed by the separation between the forward and return traces in a PCB and can be calculated using the following equation and the trace geometry in Fig. 33. Parasitic inductance is not an issue with steady state DC current, but may create noise problems during rapidly changing in input, load, or switching currents. ph mil L L S W Returning to the example that uses a 00 mil x 00mil output connection, the forward and return traces are separated by the 50 mil thickness of the board. The inductance is calculated to be 1.6 nh per connection resulting in a 18 mv transient spike between the output and load (assuming a 40 A/µs edge). Transient problems at the load can be solved with the addition of ceramic capacitors to slow the di/dt edges and reduce the transient spike. Switch currents in a high frequency converter can easily reach 1 A/ns. The resulting voltage spikes that occur from trace and package inductance near the MOSFETs can cause a number of unwanted results including EMI issues, component stress, noise glitches at the input, and interference with upstream supplies. These issues are resolved with careful layout and adequate bypassing with low ESR/ESL capacitors.

139 C. High Current Layout The proper layout of the printed circuit board (PCB) is critical in achieving acceptable efficiency and transient performance in low voltage, high current systems. Fig. 35 shows a parasitic model for a DC/DC converter, which can also be used to simulate the effects of transient behavior. The input and output capacitors have been split into two types where an electrolytic is used for bulk storage, and a ceramic is used to filter high frequency edges. ESR and ESL effects have been included for the capacitors. The model for the MOSFETs include the drain to source capacitance, Cds, the R DS(on) and the package inductance, LPKG. The inductor model includes winding resistance (RW) and interwinding capacitance (CW). The remaining parasitic elements represent the resistance (RPCB) and inductance (LPCB) of the PCB traces. The model in has been simplified by combining PCB trace parasitics and the component models, by combining forward and return trace parasitics at the input and output, and by ignoring board capacitance. This model is a good starting point, but may need to be modified to better reflect the actual board layout if a specific problem should arise. LPCB RPCB LPKG CDS SW Node CW LPCB RPCB ESR ESR SBUCK RON LPKG LBUCK ESR ESR ESR Converter Input ESL CINBULK ESL CINHF SR RON CDS ESL COUTBULK ESL COUTHF Converter Ouput LPCB RPCB LPCB RPCB Fig. 35. Simplified parasitic model for DC/DC buck converter. To minimize circuit noise, the loop created by the input capacitors and the two series MOSFETs should be kept as small as possible. By doing so, any noise generated by the pulsating current flowing through the input capacitors' ESR and ESL is minimized, and the switching MOSFETs has the benefit of having the "full" input voltage to work from. The loop formed by the SR, the output inductor and the output capacitor should also be kept as small as possible to minimize ringing on the SW node 5-31

140 D. SW Node Ringing What effect does this ringing have on circuit operation? The answer is - it depends. If the control scheme is looking at the SW node to determine when to take some action (possibly to sense overcurrent, or adjust gate drive timing) then there is a potential for mis-operation of the converter. From an EMI/RFI perspective, the energy level in the ring is relatively low and does not generally pose a problem. The fast rise and fall of the SW node at the PWM transitions are usually more cause for concern. When the main switch MOSFET turns on, the SW node rises rapidly toward the input voltage of the converter. After a few nanoseconds, SW reaches the input voltage - and keeps right on going. The reason for this is parasitic Ls and Cs "connected" to the SW node. Referring to Fig. 35, the components that cause the ringing are the Cds of the SR MOSFET, package inductance in the switch MOSFET, and inductance in the board traces through the input bypass capacitors, and any capacitance seen looking into the buck inductor. As the SW node rises, current is flowing in the inductances to charge up the capacitance seen at the SW node. When the SW node reaches Vin, the energy stored in those inductances has to go somewhere, showing up as a ringing response on SW. Resistances in the loop determine the decay time. Since the aim is to make an efficient power converter, the parasitic resistances are typically minimized and do not do a good job of damping out the SW node ringing. Hence the ring may last up to several microseconds. Two methods are generally used to reduce the ringing: Minimize the excess inductive energy buildup as SW rises; or provide a means to dissipate the energy in a controlled fashion Limiting the rise time on the SW node minimizes the excess inductive energy buildup. This amounts to purposely slowing the switching time of the main switch MOSFET by adding some resistance in between the MOSFET gate and its driver circuit. The effectiveness of this depends on how much the SW node dv/dt can be reduced, what the effective capacitance of the SW node is and what the inductor current is at the time the SW node reaches Vin. The closer that the current in the buck inductor is to what the SW capacitance needs to charge at a certain dv/dt, the less the ringing problem will be. There is a trade off though. The slower the SW node dv/dt, the more switching loss occurs in the switch and the SR. The other common method to control ringing is to use a snubber circuit. A simple series R-C network around the SR can control ringing effectively in most cases. A general approach to determining snubber component values is to add capacitance around the rectifier device until the observed ring frequency is approximately halved from its original value. The resistor value to put in series with this capacitor should be something near the impedance of the capacitor at the new ring frequency. A caution here is that a snubber can increase losses in the converter if components are not chosen wisely. For a more detailed discussion see Snubber Circuits: Theory Design and Application, Unitrode SEM-900 by Philip Todd. [7] 5-3

141 APPENDIX D. INTERLEAVED CONVERTERS When an application's load current requirement grows to a level too high for a single converter to easily handle, often the solution is to parallel power stages. By phase shifting the PWM signals to the converter power stages, or "channels", there is an added benefit of reducing the RMS ripple current in the input capacitors. This is because for each converter channel, the effective current is 1/n that of a single channel power stage. The effective duty cycle of the converter is also n times that of a single channel power stage. Fig. 36 illustrates this concept for paralleling two power stages. Vin Iout Iout PWM1 Vout C1 I Iout Synchronization Iout 1 Channel Channels * I Iout PWM Fig. 36. Interleaving. The RMS current improvement in the input capacitor for a single, a two, and a four-phase converter is shown in Fig. 37. The ripple current (and therefore the power loss) in the input capacitors reaches a maximum where the sum of the duty cycles equals 0.5, and reaches a minimum where the sum of the duty cycles approaches 100%. 5-33

142 60 50 Single Phase Relative Power Loss - % Dual Phase 10 Quad Phase Percent Duty Cycle - % Fig. 37. Input capacitor RMS ripple current in an interleaved converter. One other benefit to interleaving multiple synchronous buck regulators is the improved effect on transient response. Why is that? Fig. 38 shows the magnitude of DC and ripple current for single phase, two phase, three phase, and four-phase converters. Notice that the average level of the current is decreased by the addition of phases, and the magnitude of the ripple is allowed to be increased. Fig. 38. Increase in ripple current. 5-34

143 Fig. 39. Transient response waveforms for multi-phase converter. A smaller inductor gives the greatest benefit in transient response recovery. Fig. 39 shows the output voltage response for a one, two, three and a four-phase converter. On the left side of the figure, where a load drop is being viewed, there is a large amount of energy in the inductor transferred into the output capacitors. When more phases are added, there is less energy to "ring" the output voltage higher because the energy storage decreases as the square of the current through it. By increasing the number of phases, the current per phase drops by 1/n. During a load step increase, the single-phase converter has a response time quite a bit slower than the other cases because the output inductance is the highest. APPENDIX E. PARASITIC TURN-ON MODELING The simulation results discussed in Section II.D were generated from a simulation based on the circuit in Fig. 40. This schematic can be used for initial modeling to determine if a potential problem exists with parasitic turn on of the SR MOSFET. Ld Lg + Lpcb Cdg Cds Cgs + PWL Voltage Source Ls Fig. 40. Parasitic turn on model. 5-35