Performance Analysis of Reversible Fast Decimal Adders

Transcription

1 Proceedings of the World Congress on Engineering and Coputer Science 7 WCECS 7, October 4-6, 7, San rancisco, USA Perforance Analysis of Reversible ast Decial Adders Rekha K. Jaes, Shahana T. K., K. Poulose Jacob, and Sreela Sasi Abstract - This paper presents a perforance analysis of reversible, fault tolerant VLSI ipleentations of carry select and hybrid decial adders suitable for ulti-digit BCD addition. The designs enable partial parallel processing of all digits that perfor high-speed addition in decial doain. When the nuber of digits is ore than 5 the hybrid decial adder can operate 5 ties faster than conventional decial adder using classical logic gates. The speed up factor of hybrid adder increases above when the nuber of decial digits is ore than 5 for reversible logic ipleentation. Such highspeed decial adders find applications in real tie processors and internet-based applications. The ipleentations use only reversible conservative redkin gates, which ake it suitable for VLSI circuits. Index Ters - decial arithetic, delay reduction, reversible logic, VLSI ipleentation I. INTRODUCTION Currently, fast decial arithetic is gaining popularity in the coputing counity due to the growing iportance of coercial, financial, and internet-based applications, which norally process decial data. Low power designs with high perforance are given prie iportance by researchers, as power has becoe a first-order design consideration. While efforts are being ade to reduce power dissipation due to leakage currents, alternate circuit design considerations are also gaining iportance. In recent years, reversible logic has eerged as one of the ost iportant approaches for power optiization. Landauer s principle states that a heat equivalent to kt*ln is generated for every bit of inforation lost, where k is the Boltzann s constant and T is the teperature []. Bennett showed that energy dissipation would not occur if the coputations were carried out using reversible circuits [] since these circuits do not lose inforation. Classical logic gates such as AND, OR, and XOR are not reversible. Hence, these gates dissipate heat and ay reduce the life of the circuit. So, reversible logic is in deand in high-speed power aware circuits. Manuscript received July 4, 7. Rekha K. Jaes is with Division of Electronics, Cochin University of Science and Technology, Kochi, Kerala-68, India (phone: ; e-ail: rekhajaes@ cusat.ac.in). Shahana T. K., is with Division of Electronics, Cochin University of Science and Technology, Kochi, Kerala, India. (e-ail: shahanatk@cusat.ac.in). Dr. K. Poulose Jacob is with Departent of Coputer Science, Cochin University of Science and Technology, Kochi, Kerala, India (e-ail: kpj@cusat.ac.in). Dr. Sreela Sasi is with the Coputer Science Departent, Gannon University, Erie, PA, USA. (e-ail: sasi@gannon.edu). A reversible conventional Binary Coded Decial (BCD) adder is proposed in [3] using NG (New Gate) and NTG (New Toffoli Gate) reversible gates. Even though the ipleentation is odified in [4] using TSG reversible gates, this approach is not taking care of the fanout restriction of reversible circuits, and hence it is only a near-reversible ipleentation. An iproved reversible ipleentation of decial adder with reduced nuber of garbage outputs is proposed in [5]. These ipleentations are for the conventional BCD adders, which are relatively slow. Parity checking is one of the oldest and the ost widely used ethods for error detection in digital systes. Parity preservation proves to be useful for ensuring the robustness of reversible logic circuits. Parity-preserving reversible logic gates can be used for fault detection. B. Parhai deonstrated the feasibility of parity-preserving approach in the design of reversible logic circuits with exaples of adder circuits [6]. In this research, carry select and hybrid decial adders suitable for ulti-digit BCD addition are ipleented using parity preserving reversible redkin gates. redkin gates are conservative reversible gates. A gate is conservative if the Haing weight (nuber of logical ones) of its input equals the Haing weight of its output. If a gate is conservative and reversible then it is parity preserving. The organization of this paper is as follows: Initially, fast decial adders such as carry select and hybrid adders are described. A coparison of carry select and hybrid BCD adders with conventional decial adder in ters of speed and area is done for classical gate ipleentation. Next section describes ipleentations of carry select and hybrid adders using only parity preserving reversible redkin gates. An optiu block size for a hybrid adder is also derived. inally, a graphical delay analysis of different fault tolerant ipleentations noralized to a redkin gate is presented. II. CARRY SELECT BCD ADDER The carry select BCD adder shown in ig. consists of a 4- bit binary adder, a 6-correction circuit, and a odified special adder along with a circuit (-input AND, -input OR and a : ultiplexer) to generate decial carry out (d cout ). The 4-bit binary adder adds the BCD inputs and generates a binary su, S (S 3- ) that is checked by the 6-correction circuit. The output of the 6-correction circuit L is given as L= C out + S 3 (S +S ) () ISBN: WCECS 7

2 Proceedings of the World Congress on Engineering and Coputer Science 7 WCECS 7, October 4-6, 7, San rancisco, USA where T dcout(carry-select) is the delay to generate K-bit fro the BCD inputs for the first digit T ux is the delay of a : ultiplexer T su-digit(carry-salact) is the delay of special adder for last digit III. HYBRID BCD ADDER Hybrid logic for N-digit BCD addition can be used for delay reduction and is shown in ig.. The N-digit BCD input is divided into -digit fixed blocks. Each -digit adder consists of single digit carry select adders. To speed up addition, carry lookahead logic is included in -digit blocks. or an -digit adder, Decial C out at th digit (K - ) can be coputed as given in equation (4) using equation (). ig : Carry Select BCD adder On receiving C in, a K-bit can be generated using equation (). K = S 3 S C in + L = P C in + L () where P is the carry propagate signal (S 3 S ) If the carry select technique is adopted for K-bit generation then k denotes the K-bit with C in = and k with C in = and is given by k =P +L and k =L. After coputing both bits (k and k ) a selection is done using a : ultiplexer. To reduce the hardware and to increase the speed of the circuit, the final adder stage (4-bit special adder) is a odified version of a 4-bit binary adder consisting of a half adder, full adders and an XOR gate as in ig.. An N-digit carry select adder will have a total (worst case) delay (T dsu (carry-select) ) equal to the su of the carry delay through the first digit (T dcout(carry-select) ), the carry select delays through the next (N-) digits, and the su delay through the last digit (T su-digit(carry-select) ). This is given in equation (3). T dsu(carry-select) = T d-cout(carry-select) +(N-)T ux +T su-digit(carry-select) (3) K - = C in P k + L i [ P j ] (4) k= i= j=i+ where L i is the L-bit of i th digit P i is the propagate bit for i th digit This can be written as K - = k (-) C in + k (-) C in (5) where k (-) = K - with C in = k (-) = K - with C in = The coputations up to the generation of L i and P i bits at each digit are carried out in parallel for all digits. The delay for L-bit generation is given as T L = T adder + T 6-correction (6) where T adder is the delay of the 4-bit binary adder, T 6-correction is the delay of the 6-correction circuit k (-) and k (-) for an -digit block are coputed using L i and P i as given in equation (4) after a delay of T k(-) which is the delay of an -input AND gate and (+) input OR gate. b (N-)-(N-) a (N-)-(N-) b (-)- a (-)- b (-)- a (-)- Carry lookahead Carry lookahead Carry lookahead C in d cout Mux -digit adder Mux -digit adder Mux -digit adder BCD Su (d N-)-(N-) ) BCD Su (d (-)- ) BCD Su (d (-)- ) ig. Hybrid N-digit Decial Adder ISBN: WCECS 7

3 Proceedings of the World Congress on Engineering and Coputer Science 7 WCECS 7, October 4-6, 7, San rancisco, USA On receiving C in, the Decial C out at th digit (K - ) is generated after an additional delay of a : ultiplexer (T ux ) and is given as T -dcout = T L + T k(-) + T ux (7) The total (worst case) delay of an N-digit hybrid BCD adder (T dsu (hybrid) ) with fixed size carry look ahead block is the su of the carry delay through the first -digit lookahead adder block (T -dcout ), the carry select delays through the interediate blocks, and the su delay through the last -digit block (T su--digit ). This is given in equation (8). T dsu (hybrid) = T -dcout + [(N/)-] T ux + T su--digit (8) where T su--digit = T ux + T su-digit (9) The total (worst case) delay of an N-digit conventional BCD adder (T dsu (conventional) ) given in equation () is the su of N ties the carry delay through one digit and the su delay through the last digit (T su-digit(conventional) ). T dsu (conventional) = N T dcout(conventional) + T su-digit(conventional) () A coparison of conventional, carry select and hybrid (with =4) BCD adders in ters of area and critical path delay is done with the logic synthesis tool Leonardo Spectru fro Mentor Graphics Corporation using ASIC Library. The critical path delay and area are noralized with respect to a full adder critical path delay of.98 ns and area of 38μ. ig. 3 shows the graphical analysis of delay, and ig. 4 shows the area-delay product noralized to that of a full adder. The area overhead of carry select and hybrid adders is copensated by the speed advantage copared to the conventional adder. Area-delay product nnoralized to a full adder Area-delay analysis of different BCD adders Conventional BCD adder Carry select BCD adder Hybrid BCD adder ig. 4: Analysis of area-delay product of Conventional, Carry Select and Hybrid BCD Adders ig. 5 deonstrates the speed up factor of carry select and hybrid BCD adders copared to conventional BCD adder as the nuber of digits increases. Hybrid decial adder is three ties faster than the conventional BCD adder as the nuber of digits increases above while the carry select BCD adder attains a speed up factor of.5 at this level. It is noted that the hybrid adder attains speed up over carry select BCD adder only when the nuber of input digits increases above 8. The delay coparison graphs show that hybrid adder is 5 ties faster than that for the conventional BCD adder, when the input word length is above Delay analysis of different BCD adders Conventional BCD adder Carry Select BCD adder Hybrid BCD adder Speed iproveent for Carry select and Hybrid BCD adders Carry select vs. Conventional BCD adder Hybrid vs. Conventional BCD adder Delay noralized to a full adder Speed up factor ig. 3: Delay analysis of Conventional, Carry Select and Hybrid BCD Adders ig. 5. Speed up factor for Carry select and Hybrid BCD adders vs. conventional BCD adder ISBN: WCECS 7

4 Proceedings of the World Congress on Engineering and Coputer Science 7 WCECS 7, October 4-6, 7, San rancisco, USA IV. REVERSIBLE GATES This section describes parity preserving reversible logic gates such as eynan Double Gate (G) and redkin Gate (RG). A 3*3 eynan Double Gate (G) [6] has 3 inputs A, B, C and 3 outputs P=A, Q=A B, R=A C. A 3*3 redkin Gate (RG) [7] has 3 inputs A, B, C and 3 outputs P=A, Q= A B AC, R= AB A C. These two gates satisfy the condition A B C=P Q R. In general, a parity preserving reversible gate is a gate in which the following condition is valid. X i = Y i () where X indicates an input, Y, an output, and i the nuber of inputs or outputs of the reversible gate. V. PARITY PRESERVING REVERSIBLE CARRY SELECT BCD ADDER Recently, Hafiz [3], Thapliyal [4] and Jaes [5] proposed reversible ipleentations of conventional BCD adders. But these ipleentations ake use of reversible gates other than parity preserving gates, and hence they are not fault tolerant ipleentations. This research proposes a reversible ipleentation of fast BCD adders using the parity preserving reversible redkin gates. The basic coponent of any adder is a full adder. A nuber of parity preserving reversible full adders are available in literature [6, 8]. ig. 6 and ig. 7 show the ipleentation of a half adder and a full adder using parity preserving redkin gates. The full adder ipleentation requires only 5 redkin gates at 3 levels, copared to 3-level 6-gate (5 redkin gates and eynan gate) ipleentation in [6], and 5-level 5- redkin gate ipleentation in [8] while observing the fanout restrictions. The 4-bit binary adder realized using a half adder and 3 full adders will achieve delay reduction by using ipleentations in ig. 6 and ig. 7. The least significant bit (half adder) requires a path delay of two RGs to generate C fro the addends. Then the carry ripples through the subsequent full adders with a path delay of two RGs per bit. This is because the first redkin gates of all full adders work in parallel with the first redkin gate of half adder in an n-bit binary adder. But in the ipleentation in [6], the delay is of 3 levels for each bit. So, an advantage of delay level/bit is achieved in this ipleentation. The delay to generate C out or Su in the n-bit binary adder is T c-ripple = T su-ripple = +(n-) () B A AB=Carry A B=Su B A C Su Carry ig. 7: ull adder using redkin Gates or a conventional n-bit adder with n full adders, it is T c-ripple (conventional) = T su-ripple(conventional) = 3+(n-) (3) or a BCD adder this delay is the delay with n=4 for each digit. In carry select BCD adder, since all digits are added in parallel this delay reains the sae as a single digit for N digit addition. The parity preserving reversible ipleentation of a 6- correction circuit is shown in ig. 8. The ipleentation requires 3 RGs to generate the L output. This circuit takes only ore delays after generating the Su to generate the L-bit. The delays to generate L-bit fro the BCD inputs for carry select and conventional BCD adders are given in (4) and (5). T L(carry-select) = 4+(n-) (4) T L (conventional) = 5+(n-) (5) ig. 9 shows the generation of K-bit or the Decial C out. The generation of k and k takes the delay of only one redkin gate after receiving L-bit as seen in ig. 9. After coputing both values (k and k ) a selection is done by a single RG, since an RG works as a : ultiplexer with A input as control input and B and C inputs as data inputs. So, the additional delay in each digit to generate K-bit after receiving C in is only due to one RG. S3 S S S L ig. 8: Generation of L-bit using redkin Gates S3 L S3 k k ig. 9: Generation of K-bit using k and k S3 Cout Cin Cin K=Decial Cout ig. 6: Half adder using redkin Gates ISBN: WCECS 7

5 Proceedings of the World Congress on Engineering and Coputer Science 7 WCECS 7, October 4-6, 7, San rancisco, USA The delay in generation of K-bit (Decial C out ) for one digit for carry select BCD adder is given in equation (6), where n=4. T d-cout(carry-select) = 6+ (n-) (6) Special adder ipleented using one half adder, two full adders and one XOR gate requires 5 redkin gates (3 for half adder, 5 for each full adder, for XOR gate) to generate the BCD su (d 3- ). The Decial C out or the K-bit is the last input to be received for the special adder. The K input passes through a axiu of 5 redkin gates to generate the BCD su (d 3- ). But C in is received by the special adder along with the K-bit only. On receiving C in the half adder of the special adder generates the carry bit after one redkin gate delay. The full adders and one XOR gate adds 5 ore redkin gate delays. So the delay of special adder (T su-digit(carry-select) ) is the delay of 6 redkin gates. or an N-digit BCD adder, Decial C out at N th digit (K (N-) ) is generated after a delay equal to the su of delay of K-bit generation for the first digit (T dcout(carry-select) )and the ultiplexer delays through the next (N-)digits. It is given in equation (7). T N-d-cout(carry-select) = T dcout(carry-select) +(N-)T ux = 6+(n-) + (N-) (7) Substituting the delays in equation (3), the total worst case delay (T dsu (carry-select) ) in ters of redkin gate delay is T d-su (carry-select) = 6+(n-) + (N-) + 6 (8) or a conventional BCD adder the final adder is a 4-bit binary adder. The K input passes through a axiu of 6 redkin gates (3 full adders) of the final adder to generate the BCD su. So total (worst case) delay of an N-digit conventional BCD adder in ters of redkin gate delay is T d-su (conventional) VI. = N T dcout(conventional) + T su-digit (conventional) = N T L(conventional) + T su-digit(conventional) = (5+(n-)) N + 6 (9) HYBRID REVERSIBLE BCD ADDER The total (worst case) delay of an N-digit hybrid BCD adder with fixed size carry look ahead block is given in equation (8). The first ter in equation (8) requires a delay as given in equation (7). In reversible ipleentation using redkin gates the delay to generate all L i bits is T L (given in equation (4)) with n=4. All P i will be available when the generation of L i gets over. T k(-) is the delay of an -input AND gate and (+) input OR gate. A input AND or a input OR can be ipleented by a single redkin gate. Higher order AND and OR gates can be constructed using redkin gates arranged in a binary tree. An -input AND gate or an -input OR gate requires (-) redkin gates. In a binary tree ipleentation an input passes through a axiu of log redkin gates [8]. On receiving C in, the selection of k (-) or k (-) requires one ore redkin delay for each -digit block. Hence the carry delay through the first -digit lookahead adder block is T -dcout = + log + log ( ) + () The delay for carry select for interediate blocks is N -. The su delay through the last -digit block is (+6). Total delay in generating N-digit BCD su is given as T d-su (hybrid) = + log + log ( ) + N () However, the assuption log = is valid for the sall block sizes applicable to carry look ahead adder designs. Thus, () can be written as N T d-su (hybrid) = 5++ Miniizing T d-su (hybrid) with respect to block size opt = ().5N (3) Substituting (3) into () gives the shortest delay for a fixed block size hybrid BCD reversible adder. T d-su (hybrid) = N (4) ig. graphically deonstrates the coputation of optiu block size (corresponding to shortest delay) of hybrid reversible BCD adders for different input lengths. ig. shows a coparative delay analysis of conventional, carry select and hybrid BCD adder reversible ipleentations noralized to that of a redkin gate. Delay of reversible Hybrid BCD adder Graphical analysis of optiu block size for Hybrid BCD adder 5 7 N= N=5 N= N= per block ig. : Graphical analysis of optiu block size of Hybrid reversible BCD adder for different input lengths ISBN: WCECS 7

6 Proceedings of the World Congress on Engineering and Coputer Science 7 WCECS 7, October 4-6, 7, San rancisco, USA Delay noralized to a redkin gate [log(delay)] Delay analysis of different reversible BCD adders Conventional Carry Select Hybrid Speed up factor Speed iproveent of Carry select and Hybrid reversible BCD adders Carry select vs Conventional Hybrid vs Conventional ig. : Delay analysis of VLSI ipleentations of BCD adders igure deonstrates the speed up factor of reversible redkin gate ipleentations of carry select and hybrid BCD adders copared to conventional BCD adder. It can be noted that the hybrid adder attains speed over carry select BCD adder for all values of N in reversible ipleentation. Speed up factor of hybrid adder increases above when the nuber of decial digits is ore than 5 for fault tolerant reversible logic ipleentation. VII. CONCLUSION AND UTURE WORK This research fors the basis of a fast Decial ALU for a reversible CPU. aster decial adder circuits have been explored for several decades. This paper continues that practice by describing several reversible BCD adders using only redkin gate (RG), a conservative reversible logic gate. VLSI ipleentations using only one type of odular building blocks can decrease syste design and anufacturing cost. ig. : Speed up factor for VLSI reversible ipleentations of fast BCD adders vs. Conventional BCD adder The perforance coparison of carry select and hybrid BCD adders with conventional BCD adder are presented. It is noted that the hybrid BCD adder attains speed up over carry select and conventional BCD adders, for any input length in a reversible ipleentation. Varying the size of the carry lookahead blocks can reduce the total worst case delay, since carries generated or absorbed in the adder center have shorter data paths [9]. Investigations into deterining alternate ipleentations can be done using logic synthesis ethods [,, ]. Characterization of new failies of n-input n-output reversible gates that can be used for regular structures is an area which can be investigated further. Additionally, it is noted that there is a lack of siulation tools that support reversible gates, and this is ost definitely an area worthy of attention. REERENCES [] R. Landauer, Irreversibility and Heat Generation in Coputational Process, IBM Journal of Research and Dev., 5, pp.83-9, 96. [] Bennett, C., Logical Reversibility of Coputation, IBM Journal of Research and Developent, 7, pp.55-53, 973. [3] Md. Hafiz Hasan Babu and A. R. Chowdhury, "Design of a Reversible Binary Coded Decial Adder by Using Reversible 4-bit Parallel Adder, VLSI Design 5, pp.55-6, Jan 5. [4] H. Thapliyal, S. Kotiyal and M.B Srinivas, Novel BCD Adders and their Reversible Logic Ipleentation for IEEE 754r orat, 9 th VLSI Design 6, pp , Jan 6. [5] R. Jaes, T. K. Shahana, K. P. Jacob and S. Sasi, Iproved Reversible Logic Ipleentation of Decial Adder, To be published in Proceedings of IEEE th VDAT Syposiu Aug, 7. [6] B. Parhai; ault Tolerant Reversible Circuits Proc. 4th Asiloar Conf. Signals, Systes, and Coputers, CA, Oct 6. [7] E. redkin and T. Toffoli, Conservative logic, Intl. J. Theoretical Physics, Vol, 98, pp [8] J.W.Bruce, M.A.Thornton, L.Shivakuariah, P.S.Kokate, X.Li, "Efficient Adder Circuits Based on a Conservative Logic Gate", Proceedings of the IEEE Coputer Society Annual Syposiu on VLSI, April, PA, USA, pp [9] B. Parhai, Coputer Arithetic: Algoriths and Hardware Designs, Oxford University Press,. [] Ditri Maslov, "Reversible Logic Synthesis, PhD Dissertation, Coputer Science Departent, University of New Brunswick, Canada, October 3. [] P. Gupta, A. Agrawal, N. K. Jha, An algorith for synthesis of reversible logic circuits, IEEE Transactions on Coputer Aided Design of Integrated Circuits and Systes, Nov. 6, Volue: 5, Issue, pp [] Guowu Yang; ei Xie; Xiaoyu Song; Hung, W.N.N.; Perkowski, M.A., A constructive Algorith for Reversible Logic synthesis IEEE Congress on Evolutionary Coputation, July 6, pp ISBN: WCECS 7