N-Channel 30-V (D-S) MOSFET

Transcription

1 New Product N-Channel 30-V (D-S) MOSFET SiS42DN PRODUCT SUMMARY V DS (V) R DS(on) (Ω) I D (A) a Q g (Typ.) 30 D at V GS = 0 V at V GS = 4.5 V 2 D 7 D 6 PowerPAK 22-8 D 5 S S mm 3.30 mm Bottom View S 3 G nc Ordering Information: SiS42DN-T-GE3 (Lead (Pb)-free and Halogen-free) FEATURES Halogen-free According to IEC TrenchFET Power MOSFET 00 % R g Tested APPLICATIONS Notebook PC - System Power - Load Switch ABSOLUTE MAXIMUM RATINGS T A = 25 C, unless otherwise noted G D S N-Channel MOSFET Parameter Symbol Limit Unit Drain-Source Voltage V DS 30 V Gate-Source Voltage V GS ± 20 T C = 25 C 2a T Continuous Drain Current (T J = 50 C) C = 70 C I 2 a D T A = 25 C 8.7 b, c T A = 70 C 7 b, c A Pulsed Drain Current I DM 30 T Continuous Source-Drain Diode Current C = 25 C I 2 a S T A = 25 C 2.7 b, c Single Pulse Avalanche Current I L = 0. mh AS 5 Single Pulse Avalanche Energy E AS.25 mj T C = 25 C 5.6 T Maximum Power Dissipation C = 70 C 0 P D W T A = 25 C 3.2 b, c T A = 70 C 2 b, c Operating Junction and Storage Temperature Range T J, T stg - 55 to 50 C Soldering Recommendations (Peak Temperature) e, f 260 THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambient b, d t 0 s R thja C/W Maximum Junction-to-Case (Drain) Steady State R thjc Notes: a. Package Limited. b. Surface Mounted on " x " FR4 board. c. t = 0 s. d. Maximum under Steady State conditions is 8 C/W. e. See Solder Profile (/ppg?73257). The PowerPAK 22 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. f. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: S Rev. C, 02-Feb-09

2 SiS42DN New Product SPECIFICATIONS T J = 25 C, unless otherwise noted Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage V DS V GS = 0 V, I D = 250 µa 30 V V DS Temperature Coefficient ΔV DS /T J 35 I D = 250 µa V GS(th) Temperature Coefficient ΔV GS(th) /T J mv/ C Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 250 µa V Gate-Source Leakage I GSS V DS = 0 V, V GS = ± 20 V ± 00 na V DS = 30 V, V GS = 0 V Zero Gate Voltage Drain Current I DSS V DS = 30 V, V GS = 0 V, T J = 55 C 5 µa On-State Drain Current a I D(on) V DS 5 V, V GS = 0 V 20 A V GS = 0 V, I D = 7.8 A Drain-Source On-State Resistance a R DS(on) V GS = 4.5 V, I D = 7.0 A Ω Forward Transconductance a g fs V DS = 0 V, I D = 7.8 A 7 S Dynamic b Input Capacitance C iss 435 Output Capacitance C oss V DS = 5 V, V GS = 0 V, f = MHz 95 pf Reverse Transfer Capacitance C rss 42 V Total Gate Charge Q DS = 5 V, V GS = 0 V, I D = 7.8 A 8 2 g nc Gate-Source Charge Q gs V DS = 5 V, V GS = 4.5 V, I D = 7.8 A.4 Gate-Drain Charge Q gd. Gate Resistance R g f = MHz Ω Turn-On Delay Time t d(on) 5 25 Rise Time t r V DD = 5 V, R L = 2.4 Ω 2 20 Turn-Off Delay Time t d(off) I D 6.3 A, V GEN = 4.5 V, R g = Ω 3 20 Fall Time t f 0 5 Turn-On Delay Time t d(on) 5 0 ns Rise Time t r V DD = 5 V, R L = 2.4 Ω 0 5 Turn-Off Delay Time t d(off) I D 6.3 A, V GEN = 0 V, R g = Ω 5 25 Fall Time t f 0 5 Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 25 C 4.2 Pulse Diode Forward Current I SM 30 A Body Diode Voltage V SD I S = 6.3 A, V GS = 0 V V Body Diode Reverse Recovery Time t rr 5 25 ns Body Diode Reverse Recovery Charge Q rr 7 2 nc I F = 6.3 A, di/dt = 00 A/µs, T J = 25 C Reverse Recovery Fall Time t a 9 ns Reverse Recovery Rise Time t b 6 Notes: a. Pulse test; pulse width 300 µs, duty cycle 2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Document Number: S Rev. C, 02-Feb-09

3 New Product SiS42DN TYPICAL CHARACTERISTICS 25 C, unless otherwise noted V GS =0thru 4 V 0 8 I D - Drain Current (A) V GS =3V I D - Drain Current (A) T C = 25 C T C = 25 C V DS - Drain-to-Source Voltage (V) Output Characteristics T C = - 55 C V GS - Gate-to-Source Voltage (V) Transfer Characteristics On-Resistance (Ω) R DS(on) V GS =4.5V V GS =0V C - Capacitance (pf) C iss C oss I D - Drain Current (A) On-Resistance vs. Drain Current 0 C rss V DS - Drain-to-Source Voltage (V) Capacitance.8 - Gate-to-Source Voltage (V) V GS I D =7.8 A V DS =5V V DS =24V R DS(on) - On-Resistance (Normalized) I D =7.8 A V GS =0V V GS =4.5V Q g - Total Gate Charge (nc) Gate Charge T J -Junction Temperature ( C) On-Resistance vs. Junction Temperature Document Number: S Rev. C, 02-Feb-09 3

4 SiS42DN New Product TYPICAL CHARACTERISTICS 25 C, unless otherwise noted I D =7.8 A - Source Current (A) I S 0 T J = 50 C T J = 25 C - On-Resistance (Ω) R DS(on) T J = 25 C T J = 25 C V SD -Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage V GS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage I D = 250 µa 40 (V) V GS(th) Power (W) T J - Temperature ( C) Threshold Voltage Time (s) Single Pulse Power 00 Limited by R DS(on) * - Drain Current (A) I D 0 0. T A =25 C Single Pulse BVDSS Limited 00 µs ms 0 ms 00 ms s 0 s DC V DS - Drain-to-Source Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Safe Operating Area, Junction-to-Ambient 4 Document Number: S Rev. C, 02-Feb-09

5 New Product SiS42DN TYPICAL CHARACTERISTICS 25 C, unless otherwise noted I D - Drain Current (A) Package Limited Power (W) T C - Case Temperature ( C) Current Derating* T C - Case Temperature ( C) Power Derating * The power dissipation P D is based on T J(max) = 50 C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: S Rev. C, 02-Feb-09 5

6 SiS42DN New Product TYPICAL CHARACTERISTICS 25 C, unless otherwise noted Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance t 0.02 t 2 t. Duty Cycle, D = t 2 2. Per Unit Base = R thja = 8 C/W 3. T JM -T A =P DM Z (t) thja Single Pulse 4. Surface Mounted Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Notes: P DM Normalized Effective Transient Thermal Impedance Duty Cycle = Single Pulse Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg? Document Number: S Rev. C, 02-Feb-09

7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, Vishay ), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 9000 Revision: 8-Jul-08

8 Package Reliability ENVIRONMENTAL AND PACKAGE TESTING DATA FOR PowerPAK 22 Stress Sample Size Device Hr./Cyc Condition Total Fails Fail Percentage BOND TNT 20 60, C +N HAST 4,046 40, C, 85%RH Power Cycle 246 5,27,288 DELTA T j = Pressure Pot 6,46 675,36 2, 5 PSIG Solder DUNK,74 6, C, 0SEC Solderability,075 0, M Temp Cycle 0,363 3,533, C 50 C Document Number: Jan-05

9 Silicon Technology Reliability N-CHANNEL ACCELERATED OPERATING LIFE TEST RESULT Sample Size Equivalent Device Hours Failure Rate in FIT.36 Failure Rate in FIT is calculated according to JEDEC Standard JESD85, Methods for Calculating Failure Rates in Units of FITs, based on accelerated high temperature operating life test results by using an apparent activation energy of 0.7 ev. The junction temperature of the device at use is assumed to be 55 C. A constant failure rate distribution is assumed. The upper confidence bound of the failure rate is 60 %. Document Number: Revision: 28-Jul-08

10 N-Channel 30-V (D-S) MOSFET SPICE Device Model SiS42DN CHARACTERISTICS N-Channel Vertical DMOS Macro Model (Subcircuit Model) Level 3 MOS Apply for both Linear and Switching Application Accurate over the - 55 C to 25 C Temperature Range Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the N-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 C to 25 C temperature ranges under the pulsed 0 V to 0 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched C gd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: S Rev. A, 5-Dec-08

11 SPICE Device Model SiS42DN SPECIFICATIONS (T J = 25 C UNLESS OTHERWISE NOTED) Static Parameter Symbol Test Condition Simulated Data Measured Data Gate Threshold Voltage V GS(th) V DS = V GS, I D = 250 μa.7 V Drain-Source On-State Resistance a R DS(on) V GS = 0 V, I D = 7.8 A V GS = 4.5 V, I D = 7 A Forward Transconductance a g fs V DS = 0 V, I D = 7.8 A 9 7 S Body Diode Voltage V SD I S = 6.3 A V Dynamic b Input Capacitance C iss Output Capacitance C oss V DS = 5 V, V GS = 0 V, f = MHz Reverse Transfer Capacitance Total Gate Charge C rss Q g V DS = 5 V, V GS = 0 V, I D = 7.8 A Gate-Source Charge Q gs V DS = 5 V, V GS = 4.5 V, I D = 7.8 A.4.4 Gate-Drain Charge.. Notes a. Pulse test; pulse width 300 μs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Q gd Unit Ω pf nc Document Number: S Rev. A, 5-Dec-08

12 SPICE Device Model SiS42DN COMPARISON OF MODEL WITH MEASURED DATA (T J = 25 C UNLESS OTHERWISE NOTED) Document Number: S Rev. A, 5-Dec-08 3

13 SPICE Device Model SiS42DN COMPARISON OF MODEL WITH MEASURED DATA (T J = 25 C UNLESS OTHERWISE NOTED) Document Number: S Rev. A, 5-Dec-08

14 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, Vishay ), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 9000 Revision: 8-Jul-08

15 θ Package Information PowerPAK 22, (Single/Dual) W D4 H E2 E4 K L 8 M e Z 2 D D D2 D b θ θ θ L A E3 BACKSIDE VIEW OF SINGLE PAD c A 2 E E Notes:. Inch will govern 2 Dimensions exclusive of mold gate burrs DETAIL Z H D2 D4 D3 (2x) E2 E4 D D2 K K D5 L b 3. Dimensions exclusive of mold flash and cutting burrs E3 BACKSIDE VIEW OF DUAL PAD MILLIMETERS INCHES DIM Min. Nom. Max. Min. Nom. Max. A A b c D D D D D G D E E E E G E e 0.65 BSC BSC K K H L L θ W M ECN: T-0774-Rev. G, 24-Dec-07 DWG: 5882 Document Number: Dec-07

16 Part Marking Information DEVICES: PowerPAK SO-8 PowerPAK SO-8L PowerPAK 22-8 PowerPAIR 6 x 3.7 Single and Dual L L T Y W F 740 = Example Base Part Number = Siliconix Logo LL = Lot Code = ESD Symbol = Pin Indicator T = Assembly Factory Code Y = Year Code W = Week Code F = Wafer Fab Code The current marking strategy is reflected. Contact your local sales representative for historical marking strategies for these packages. Document Number: Mar-09

17 Reel Information LOK REEL T 40 Typ. Opening (Optional) 6 ± W 20.5 ± ± ± 0.2 Measured at hub H (φ ) A (φ ) 20 Typ. Notes:. Material: antistatic plastic (high impact polystyrene) 2. Shelf Life: 2 years 3. Color: Any color is acceptable VER APPLICATION A W TAPE WIDTH H T SOIC-4/6 TO-25 (Short Lead) TO-252/TO-252 (Reverse Lead) PLCC-20 TSSOP-8/4/6/20/28 SSOP-24 SOIC-6 (W) SOIC-8 (N), SOIC-8 (N) epad MSOP-8/0 PowerPAK SO-8 PowerPAK 22 MICRO FOOT MLP33-5, MLP33-8, MLP33-0 QFN (4x4)/(3x3)/DFN-0 (3x3)/ MLP44-6 MLP65-8/20L SOT-23/43 TSOP-5/6/SC70JW-8L ChipFET SC70/SC75A/SC89 MICRO FOOT SC-89 (SOT-666) SOT23-5, 6 SOT-23/43 SC70 MICRO FOOT SOIC-20(W)/24(W) D2PAK SSOP-28 QSOP-36 Note , see page 2 for drawing detail. PowerPAK MLF 9 x 9 PowerPAK MLP 6 x 6 MLF 8 x 8 PolarPAK MLP55-28L MLP55-32L PowerPAIR 6 x 5 PowerPAIR 6 x 3 J PowerPAIR SO8-L PowerPAK SC70 PowerPAK SC75 MiniQFN PowerPAK MLP22-5 PowerPAK ChipFET PowerPAK SC75-6L (PIC) PowerPAK TSC75-6L (PIC) TSOP-6, ChipFET PowerPAK SC70, PowerPAK SC75 PowerPAK MLF 0 x ± ± ± ± ± 2.5 ± ± ± 0.5 Document Number: 7385 Revision: 0-Jun ± TO-220 (for Kimball, V304-T) 330 ± MICRO FOOT PowerPAK 2 x ± ECN: C Rev. BA, 0-Jun-09 DWG: X ± 2 or 55 ± 2 or 79 ± 2 ± ± 2.5 ± ± 2.5 ± ± 2.5 ± ± 2.6 ± 0.25

18 Reel Information LOK REEL (DRAWING DETAIL) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC 24. REF SENSITIVE DEVICES R 6.6 REF 7 REF 0.5 ± ± ± ± 4 ± 0.5 R 45.8 ± 0.5 R5 REF.8 (BOTTOM) 60 6 ± ± ± REF 90 R7 REF 4.7 Sd ± ± ± REF 30.8 REF 56.8 ± 9 ± 0.5 FULL R 78 ± FULL R 22.4 ± ± ± ± ± R0.8 R0.8 Notes:. Material: polystyrene (white) 2. Antistatic coated 3. Flange warpage: 3 mm max. 4. All dimensions in mm 5. ESD-surface resistivity ~ 0 Ω/sq. 6. General tolerance: ± 0.25 mm 7. Part number: P900 Document Number: Revision: 0-Jun-09

19 Tape Information PowerPAK ± ± 0.05 see note see note 8.00 Ø.50 min. Ø A.75 ± 0.0 R0.2 max. (R0.30 max. for version ) Bo 2.0 ± 0.3 Ko Section A-A Ao A R0.3 typ. (R.O.5 typ. for version ) 5.50 ± 0.05 see note 6 Version A 0 B 0 K ± ± 0..4 ± (TW only) 3.6 ± ± 0..4 ± 0. Notes. 0 sprocket hole pitch cumulative tolerance ± Camber not to exceed mm in 00 mm. 3. Material: black advantek polystyrene. 4. A 0 and B 0 measured on a plane 0.3 mm above the bottom of the pocket. 5. K 0 measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. It should be measured from: a. sprocket hole to pocket center b. sprocket hole to pocket hole 7. All sizes in mm unless specified. 8. Tolerances will be ± 0. mm unless specified. QUANTITY PER REEL T 3000 ECN: T Rev. D, -Feb-08 DWG: x Document Number: Feb-08

20 AN822 PowerPAK 22 Mounting and Thermal Considerations Johnson Zhao MOSFETs for switching applications are now available with die on resistances around mω and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 22-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 22-8 s construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed. THE PowerPAK PACKAGE The PowerPAK 22-8 package (Figure ) is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is mounted on. The PowerPAK 22-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note PowerPAK SO-8 Mounting and Thermal Considerations. ) The PowerPAK 22-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6 s. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 22-8 is a good option. Both the single and dual PowerPAK 22-8 utilize the same pin-outs as the single and dual PowerPAK SO-8. The low.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints. PowerPAK 22 SINGLE MOUNTING To take the advantage of the single PowerPAK 22-8 s thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs. Click on the PowerPAK 22-8 single in the index of this document. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improvement in thermal performance. Figure. PowerPAK 22 Devices Document Number Mar-06

21 AN822 PowerPAK 22 DUAL To take the advantage of the dual PowerPAK 22-8 s thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs. Click on the PowerPAK 22-8 dual in the index of this document. The gap between the two drain pads is 0 mils. This matches the spacing of the two drain pads on the PowerPAK 22-8 dual package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improvement in thermal performance. REFLOW SOLDERING surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see doc? Ramp-Up Rate + 6 C /Second Maximum Temperature at 55 ± 5 C 20 Seconds Maximum Temperature Above 80 C Seconds Maximum Temperature /- 0 C Time at Maximum Temperature Seconds Ramp-Down Rate + 6 C/Second Maximum Figure 2. Solder Reflow Temperature Profile C 0 s (max) 3 C/s (max) 4 C/s (max) C 83 C 3 C/s (max) 60 s (min) Pre-Heating Zone 50 s (max) Reflow Zone Maximum peak temperature at 240 C is allowed. Figure 3. Solder Reflow Temperatures and Time Durations 2 Document Number Mar-06

22 AN822 TABLE : EQIVALENT STEADY STATE PERFORMANCE Package SO-8 TSSOP-8 TSOP-8 PPAK 22 PPAK SO-8 Configuration Single Dual Single Dual Single Dual Single Dual Single Dual Thermal Resiatance R thjc (C/W) PowerPAK 22 Standard SO-8 Standard TSSOP-8 TSOP C 85 C 49 C 25 C 2.4 C/W 20 C/W 52 C/W 40 C/W PC Board at 45 C Figure 4. Temperature of Devices on a PC Board THERMAL PERFORMANCE Introduction A basic measure of a device s thermal performance is the junction-to-case thermal resistance, Rθjc, or the junction to- foot thermal resistance, Rθjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table shows a comparison of the PowerPAK 22-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance. By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 C (Figure 4). Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK 22-8 and the other SMT packages, die temperatures are determined to be 49.8 C for the PowerPAK 22-8, 85 C for the standard SO-8, 49 C for standard TSSOP-8, and 25 C for TSOP-6. This is a 4.8 C rise above the board temperature for the Power- PAK 22-8, and over 40 C for other SMT packages. A 4.8 C rise has minimal effect on r DS(ON) whereas a rise of over 40 C will cause an increase in r DS(ON) as high as 20 %. Spreading Copper Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 22-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed. Document Number Mar-06 3

23 AN Spreading Copper (sq. in.) 20 0 Spreading Copper (sq. in.) R t hj A ( C/W) % % 0 % Figure 5. Spreading Copper - Si740DN R thj A ( C/W) % 00 % 0 % Figure 6. Spreading Copper - Junction-to-Ambient Performance CONCLUSIONS As a derivative of the PowerPAK SO-8, the PowerPAK 22-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8. Recommended PowerPAK 22-8 land patterns are provided to aid in PC board layout for designs using this new package. The PowerPAK 22-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps r DS(ON) low, and permits the device to handle more current than a same- or larger-size MOS- FET die in the standard TSSOP-8 or SO-8 packages. 4 Document Number Mar-06

24 Application Note 826 RECOMMENDED MINIMUM PADS FOR PowerPAK 22-8 Single 0.52 (3.860) (0.990) (.725) 0.00 (0.255) 0.06 (0.405) (2.235) (2.390) (0.660) (0.635) (0.760) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: Revision: 2-Jan-08 7

25 SiS42DN_RC R-C Thermal Model Parameters DESCRIPTION The parametric values in the R-C thermal model have been derived using curve-fitting techniques. R-C values for the electrical circuit in the Foster/Tank and Cauer/Filter configurations are included. When implemented in P-Spice, these values have matching characteristic curves to the single-pulse transient thermal impedance curves for the MOSFET. These RC values can be used in the P-SPICE simulation to evaluate the thermal behavior of the MOSFET junction temperature under a defined power profile. These techniques are described in Application Note AN609, "Thermal Simulation of Power MOSFETs on the P-Spice Platform." R-C THERMAL MODEL FOR TANK CONFIGURATION R-C VALUES FOR TANK CONFIGURATION Thermal Resistance ( C/W) Junction to Ambient Case Foot RT m N/A RT N/A RT N/A RT N/A Thermal Capacitance (Joules/ C) Junction to Ambient Case Foot CT u.4620 m N/A CT m m N/A CT m u N/A CT m N/A This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: Revision: 27-Oct-08

26 SiS42DN_RC R-C THERMAL MODEL FOR FILTER CONFIGURATION R-C VALUES FOR FILTER CONFIGURATION Thermal Resistance ( C/W) Junction to Ambient Case Foot RF N/A RF N/A RF N/A RF m N/A Thermal Capacitance (Joules/ C) Junction to Ambient Case Foot CF u u N/A CF m.986 m N/A CF m m N/A CF m N/A Note NA indicates not applicable Document Number: Revision: 27-Oct-08

27 SiS42DN_RC Document Number: Revision: 27-Oct-08 3