CRYSTEK. RF PLL Synthesizer MICROWAVE CRYSTEK. Features. Applications CPLL " SQ SMD CORPORATION GHz. Standard 3 Wire Interface

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1 MIROWAVE A Division of rystek orporation PLL Features GHz Standard 3 Wire Interface Small layout 0.6" 0.6" Applications Digital Radio Equipment Fixed Wireless Access Satellite ommunications Systems Base Stations Personal ommunications Systems Portable Radios Test Instruments Wireless Infrastructure The PLL66 is a complete PLL/Synthesizer needing only an external frequency reference and supply voltages for the internal PLL (phase lock loop) and VO (voltage controlled oscillator). The rystek PLL66 is programmed using a standard three line interface (Data, lock and Load Enable). The PLL66 family has been initially released to cover 100 MHz to 5 GHz in bands. It is housed in a compact 0.6-in. 0.6-in in. SMD package which saves board space. Typical phase noise at 4 GHz is -90 at 10 khz offset with 0 dbm minimum output power. Page 1 of 7

2 MIROWAVE A Division of rystek orporation PLL PERFORMANE SPEIFIATION Frequency Range: Step Size: Settling Time, to within ± 1kHz (Freq. step < 25MHz): Output Power: Output Phase Noise: (See Plot offset Power Supply: V1=VO Supply V2=PLL Supply Supply urrent: I1=VO Input urrent I2=PLL Input urrent Spurious Suppression PFDSpur Reference Feedthru Harmonic Suppression (2 nd Harmonic): 2 nd Reference Frequency MIN TYP MAX UNITS k GHz khz msec dbm Input Reference Level 0.8 V2 Vp-p RF Output Level Input Impedance RF Output Impedance Operating Temperature Range: Logic Inputs (lock, Data, and LE): Input High Voltage Input Low Voltage Locked Detector (LD): Locked Un-Locked ma ma MHz dbm Ohm Ohm Page 2 of 7

3 MIROWAVE A Division of rystek orporation PLL Page 3 of 7

4 MIROWAVE A Division of rystek orporation PLL TOP VIEW BOTTOM VIEW 0.00 PLL Date ode REF V2 V1 RF LE DATA LK LD N/ LE= Load Enable, MOS Input DATA= Serial Data Input LK= lock LD= Lock Detect REF= Reference Input V1= Analog Supply Input (VO) V2= Digital Supply Input (PLL) RF= RF Output BOTTOM ORIENTATION MARK TOP ORIENTATION MARK Pad Detail REOMMENDED REFLOW SOLDERING PROFILE TEMPERATURE Ramp-Up 3 /Sec Max. ritical Temperature Zone Ramp-Down 6 /Sec. Preheat 180 Secs. Max. 90 Secs. Max. 8 Minutes Max. 260 for 10 Secs. Max. Page 4 of 7

5 MIROWAVE A Division of rystek orporation PLL ENVIRONMENTAL OMPLIANE Parameter onditions Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 1014 Resistance to Solvents MIL-STD-883, Method 2016 Introduction Programming Guide for PLL66-XXXX The PLL66 uses a simple 3 wire interface to program four internal registers. See Figure 1. LOK t 1 t 2 t 3 t 4 DATA DB23 (MSB) DB22 DB2 DB1(ONTROL BIT 2) DB0(LSB) (ONTROL BIT 1) t 6 LE LE t 5 Figure 1. Timing Diagram There are four 24 bit registers that need to be programmed. Which register is written into is simply controlled by ontrol Bits 1 and 2. Table I summarizes the Truth Table for ontrol Bits 1 and 2. ontrol Bits Data Latch R ounter N ounter (A and B) Function Latch (Including Prescaler) Initialization Latch Table I. 2, 1 Truth Table Page 5 of 7

6 MIROWAVE A Division of rystek orporation PLL Table II shows the details of the four 24 bit registers. REFERENE OUNTER LATH RESERVED LOK DETET PREISION TEST MODE ANTI- BAKLASH WIDTH 14-BIT REFERENE OUNTER ONTROL X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 2(0) 1(0) N OUNTER LATH P GAIN RESERVED 13-BIT OUNTER 6-BIT OUNTER ONTROL G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 2(0) 1(1) FUNTION LATH PRESALER VALUE 2 URRENT SETTING2 URRENT SETTING 1 TIMER OUNTER ONTROL FASTLOK MODE FASTLOK ENABLE P THREE- STATE PD POLARITY MUXOUT ONTROL 1 OUNTER RESET ONTROL P2 P1 PD2 P16 P15 P14 P13 P12 P11 T4 T3 T2 T1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 2(1) 1(0) INITIALIZATION LATH PRESALER VALUE 2 URRENT SETTING2 URRENT SETTING 1 TIMER OUNTER ONTROL FASTLOK MODE FASTLOK ENABLE P THREE- STATE PD POLARITY MUXOUT ONTROL 1 OUNTER RESET ONTROL P2 P1 PD2 P16 P15 P14 P13 P12 P11 T4 T3 T2 T1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 2(1) 1(1) Table II. Latch Summary When using the PLL66 family in a synthesizer application, all four 24 bit registers need to be written into after power-up. After writing all four latches the first time, subsequent frequency step changes can be accomplished by changing the N ounter Latch only. Specifications subject to change without notice. Page 6 of 7

7 MIROWAVE A Division of rystek orporation PLL Programming rystek p/n: PLL The following is specific programming for PLL (2.450 GHz fixed frequency with 100 khz Step Size and 10 MHz input reference frequency). Program all three registers with the following: R ounter Latch: H N ounter Latch: 02FD51 H Function Latch: 9F8083 H The above values will set the PLL to GHz Page 7 of 7