L2 1uH R5 10 D1 MBR0530T1. 1uF Vcc Comp. C7 0.1uF BST. Hdrv NX2114. Ldrv. Gnd 3. C3 2.2nF

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1 DESCRIPTION Evaluation board available. NX4/4A 00kHz & 600kHz SYNCHRONOUS PWM CONTROLLER The NX4 controller IC is a synchronous Buck controller IC designed for step down DC to DC converter applications. Synchronous control operation replaces the traditional catch diode with an Nch MOSET resulting in improved converter efficiency. Although the NX4 controller is optimized to convert single 5V bus voltages to supplies as low as 0.8V output voltage, however using a few external components it can also be used for other input supplies such as V input (See NX data sheet for more optimized solution). The NX4 operates at 00kHz while 4A is set at 600kHz operation which together with less than 50 ns of dead band provides an efficient and cost effective solution. Other features of the device are: Internal digital soft start; Vcc undervoltage lock out; Output undervoltage protection with digital filter and shutdown capability via the enable pin. ON O R6 0k R7 0k Vin +5V C 47p C4 47u,70mohm C8 47u,70mohm N904 7 C.5n R4.k 6 C6 u Vcc Comp b R5 0 5 NX4 Gnd BST L uh PRELIMINARY DATA SHEET Pb ree Product EATURES Synchronous Controller in 8 Pin Package Bus voltage operation from V to 5V Single 5V Supply Operation Short protection with feedback UVLO Internal 00kHz for 4 and 600kHz for 4A Internal Digital Soft Start unction Shut Down via pulling comp pin low Pb-free and RoHS compliant APPLICATIONS Graphic Card on board converters Memory Vddq Supply in mother board applications On board DC to DC such as 5V to.v,.5v or.8v Hard Disk Drive Set Top Box D MBR050T Hdrv SW Ldrv 8 4 C7 0.u C5 u M M TYPICAL APPLICATION L.5uH Cin 0u,mohm Vout +.6V,6A Co x (0u,5mohm) R 0.k R.5k R 0.k C.n igure - Typical application of 4 ORDERING INORMATION Device Temperature Package requency Pb-ree NX4CSTR 0 to 70 o C SOIC-8L 00kHz Yes NX4ACSTR 0 to 70 o C SOIC-8L 600kHz Yes

2 NX4/4A ABSOLUTE MAXIMUM RATINGS(NOTE) Vcc to GND & BST to SW voltage V BST to GND Voltage... 5V Storage Temperature Range o C to 50 o C Operating Junction Temperature Range o C to 5 o C NOTE: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INORMATION 8-PIN PLASTIC SOIC (S) θ / JA o 0 CW BST HDrv Gnd SW Comp b LDrv 4 5 Vcc ELECTRICAL SPECIICATIONS Unless otherwise specified, these specifications apply over Vcc 5V, and T A 0 to 70 o C. Typical values refer to T A 5 o C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER SYM Test Condition Min TYP MAX Units Reference Voltage Ref Voltage V RE 4.5V<Vcc<5.5V 0.8 V Ref Voltage line regulation 0. % Supply Voltage(Vcc) V CC Voltage Range V CC V V CC Supply Current (Static) I CC (Static) Outputs not switching. ma V CC Supply Current (Dynamic) I CC (Dynamic) C LOAD 00p S 00kHz 5 ma Supply Voltage(V BST ) V BST Supply Current (Static) I BST (Static) Outputs not switching 0.5 ma V BST Supply Current (Dynamic) I BST (Dynamic) C LOAD 00p S 00kHz 5 ma Under Voltage Lockout V CC -Threshold V CC _UVLO V CC Rising 4. V V CC -Hysteresis V CC _Hyst V CC alling 0. V

3 NX4/4A PARAMETER SYM Test Condition Min TYP MAX Units SS Soft Start time Tss sw00khz, 4.4 ms Oscillator (Rt) requency S sw600khz, 4A khz 4A 600 khz Ramp-Amplitude Voltage V RAMP.7 V Max Duty Cycle 94 % Min Duty Cycle 0 % Error Amplifiers Transconductance 900 umho Input Bias Current Ib 0 na Comp SD Threshold 0. V B Under Voltage Protection B Under voltage threshold 0.4 V High Side Driver(C L 00p) Output Impedance, Sourcing Current Output Impedance, Sinking Current Output Sourcing Current V BST -V HDRV 5V A Output Sinking Current V HDRV -V SW 5V A Rise Time THdrv(Rise) 0% to 90% 50 ns all Time THdrv(all) 90% to 0% 50 ns Deadband Time Low Side Driver (C L 00p) Output Impedance, Sourcing Current Output Impedance, Sinking Current R source (Hdrv) I00mA R sink (Hdrv) I00mA Tdead(L to H) Ldrv going Low to Hdrv going High, 0%-0%. ohm 0 ns R source (Ldrv) I00mA. ohm R sink (Ldrv) I00mA 0.5 ohm Output Sourcing Current V PVCC -V LDRV 5V A Output Sinking Current V LDRV -PGND5V 4 A Rise Time TLdrv(Rise) 0% to 90% 50 ns all Time TLdrv(all) 90% to 0% 50 ns Deadband Time Tdead(H to SW going Low to Ldrv 0 ns L) going High, 0% to 0% 0.8 ohm

4 NX4/4A PIN DESCRIPTIONS PIN # PIN SYMBOL PIN DESCRIPTION BST This pin supplies voltage to the high side driver. A high frequency ceramic capacitor of 0. to u must be connected from this pin to SW pin. HDRV GND 4 LDRV 5 Vcc 6 B 7 COMP 8 SW High side MOSET gate driver. Ground pin. Low side MOSET gate driver. Voltage supply for the internal circuit as well as the low side MOSET gate driver. A u high frequency ceramic capacitor must be connected from this pin to GND pin. This pin is the error amplifier inverting input. This pin is also connected to the output UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV outputs are latched off. This pin is the output of the error amplifier and together with B pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.V, both drivers are turned off and internal soft start is reset. This pin is connected to the source of the high side MOSET and provides return path for the high side driver. 4

5 NX4/4A BLOCK DIAGRAM VCC 5 UVLO BST Hdrv DRIVER 8 4 SW Ldrv GND OSC Q Q S R 7 6 COMP B 0.V LATCH DIGITAL SS TIMER VRE 0.4V igure - Simplified block diagram of the NX4 5

6 NX4/4A Demoboard design and waveforms Vin +5V C 47p C4 47u,70mohm C8 47u,70mohm 7 C.5n R4.k 6 C6 u Vcc Comp b R5 0 5 NX4 Gnd BST L uh D N589 Hdrv SW Ldrv 8 4 sdfd C7 0.u C5 u M M L.5uH Cin 0u,mohm Vout +.6V,6A Co x (0u,5mohm) R 0.k Bill of Material R 0.k R.5kohm C.n igure - demoboard design on NX4 Name Component description Vendor Vendor P/N Number R 0.k % chip resistor R 0.k % chip resistor R.5k % chip resistor sdfdsf R4.k % chip resistor R5 0 chip resistor C 47p ceramic C.5n ceramic C.n ceramic C4,C8 47u,6V,70mohm,SMD Sanyo 6TQC47M C5,C6 u ceramic C7 0.u ceramic C IN 0u,6.V,mohm,SMD Sanyo 6TPD0M C O 0u,4V,5mohm,SMD Sanyo 4TPE0M D Diode DN589 M,M MOSET airchild DS694 L.5uH,6.8A Coilcraft DO6P-5 L uh,6.4a Coilcraft DO6P-0 Note: To make sure short circuit protection of device functions correctly, C8 and R5 are necessary for filtering noise in single power supply design. 6

7 NX4/4A 95 Vin5V,Vout.6V 90 Efficiency (%) Current (A) igure : Output efficiency igure 4: Voltage V output voltage, 7A output current igure 5: Start up time igure 6: Output voltage transient response for load curent 0A-6A igure 7: Output voltage droop during transient(0a-6a) igure 8: Startup operation waveform 7

8 NX4/4A APPLICATION INORMATION Symbol Used In Application Information: VIN - Input voltage V - Output voltage I - Output current VRIPPLE - Output voltage ripple S - Working frequency IRIPPLE - Inductor current ripple Design Example The following is typical application for NX4, the schematic is figure. VIN 5V V.6V I6A VRIPPLE <0mV 6A step Output Inductor Selection The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 0% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations: L I RIPPLE VIN-V V I V k I RIPPLE IN S PUT where k is between 0. to 0.4. Select k0.4, then L 0.4 6A 5V 00kHz L 5V-.6V.6V.5uH...() Choose inductor from COILCRAT DO6P-5 with L.5uH is a good choice. Current Ripple is recalculated as V -V V IN I RIPPLE L V IN S 5V-.6V.6v.4A.5uH 5v 00kHz...() Output Capacitor Selection Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(dc) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(). IRIPPLE VRIPPLE ESR IRIPPLE + 8 C S...() Where ESR is the output capacitors' equivalent series resistance,c is the value of output capacitors. Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation() and the second term can be neglected. or this example, POSCAP are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple. VRIPPLE 0mV ESR desire 8.6mΩ I.A...(4) RIPPLE If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. or example, for 0mV output ripple, POSCAP 4TPE0M with 5mΩ are chosen. N ESR E IRIPPLE V...(5) RIPPLE Number of Capacitor is calculated as 5mΩ.A N 0mV N.8 The number of capacitor has to be round up to a integer. Choose N. 8

9 NX4/4A If ceramic capacitors are chosen as output capacitors, both terms in equation () need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors. or example, one 00u, X5R ceramic capacitor with mω ESR is used. The amount of output ripple is.a VRIPPLE mω.a kHz 00u 4.6mV+ 9.6mV.mV Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as: V DROOP< step load I STEP During the transient, the voltage droop during the transient is composed of two sections. One Section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. or example, for the overshoot, when load from high load to light load with a I STEP transient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation. V...(6) Vovershoot ESR Istep + τ L C where τ is the a function of capacitor, etc. 0 if L Lcrit τ L Istep ESR C if L L V L where crit step step crit...(7) ESR C V ESRE CE V I I...(8) where ESR E and C E represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. or low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L is true. In that case, the transient spec is dependent on the ESR of capacitor. crit In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following ESRE Istep V N + τ...(9) V L C V where tran E tran 0 if L Lcrit τ L Istep ESR C if L L V E E crit...(0) or example, assume voltage droop during transient is 00mV for 6A load step. If the POSCAP R5TPE0MC (0u, mω ) is used, the critical inductance is given as L ESR C V E E crit Istep 5mΩ 0µ.6V 0.88 µ H 6A The selected inductor is.5uh which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is L Istep τ ESRE C V.5µ H 6A 5m Ω 0 µ.us.6v ESR I V N + τ V L C V E step tran E tran 5mΩ 6A + 60mV.6V.us.5µ H 0µ 60mV.7 The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N. E 9

10 NX4/4A It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. or more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 0% to 00% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 80 o phase shift, and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between /0 and /5 of the switching frequency, phase margin greater than 50 o and the gain crossing 0dB with - 0dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. Z...() π R C 4 Z...() π (R + R) C P...() π R C P...(4) C C π R4 C + C where Z,Z,P and P are poles and zeros in the compensator. Their locations are shown in figure 0. The transfer function of type III compensator for transconductance amplifier is given by: Ve gm Zf V + g Z + Z /R m in in or the voltage amplifier, the transfer function of compensator is V V e Zf Z in To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>/gm. R R R>>/gm is desirable. Zf Vout Zin C A. Type III compensator design or low ESR output capacitors, typically such as R R C R4 Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier. C R b Vref gm Ve igure 9 - Type III compensator using transconductance amplifier 0

11 NX4/4A Gain(db) power stage LC loop gain compensator 40dB/decade ESR 0dB/decade O 0kHz. C ( - ) π R z p ( - ) π 0kΩ 6.kHz 48kHz.n V π L R C OSC O 4 out Vin C.7V π 0kHz.5uH 440u 5V.n 9.kΩ Choose C.n, R 4.kΩ. 5. Calculate C with zero z at 75% of the LC double pole by equation (). Z Z O P P igure 0 - Bode plot of Type III compensator Design example for type III compensator are in order. The crossover frequency has to be selected as LC < O < ESR, and O </0~/5 s.. Calculate the location of LC double pole LC and ESR zero ESR. LC ESR π L C π.5uh 440u 6.kHz π ESR C π 7.5m Ω 440u 48kHz. Set R equal to0.kω, then R 0.kΩ.. Set zero Z LC and p ESR. 4. Calculate R 4 and C with the crossover frequency at /0~ /5 of the switching frequency. Set C π R Z 4 π kHz.k Ω.55n Choose C.5n. 6. Calculate C by equation (4) with pole p at half the switching frequency. C π R 4 P π.k Ω 50kHz 48p Choose C 47p. 7. Calculate R by equation (). R π C P π 48kHz.n.5kΩ Choose R.5kΩ.

12 NX4/4A B. Type II compensator design If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. Type II compensator can be realized by simple RC circuit without feedback as shown in figure. R and C introduce a zero to cancel the double pole effect. C introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain. R R Vout b Vref gm Ve R C C R Gaing R... (5) m R+R z... (6) π R C p... (7) π R C power stage igure - Type II compensator with transconductance amplifier or this type of compensator, O has to satisfy LC < ESR << O </0~/5 s. The following uses typical design in figure 9 as an example for type II compensator design, two 680u with 4mΩ electrolytic capacitors are used..calculate the location of LC double pole LC and ESR zero ESR. Gain(db) loop gain compensator Z LC 40dB/decade ESR 0dB/decade O Gain P igure - Bode plot of Type II compensator LC ESR π L C π.5uh 60u.5kHz π ESR C π 0.5m Ω 60u 5.7kHz.Set R equal to0.kω. Using equation 8, the final selection of R is.4kω.. Set crossover frequency at /0~ /5 of the swithing frequency, here O0kHz. 4.Calculate R value by the following equation.

13 .6V, the result of R is 0kΩ. NX4/4A V π L R+R OSC O R V in R ESR g m R.7V π 0kHz.5uH 0.5 Ω.9mA/V 0.k Ω+.4kΩ.4kΩ 4.kΩ R R Vout b Vref Choose R 4.5kΩ. 5. Calculate C by setting compensator zero Z at 75% of the LC double pole. C π R z π 4.5k Ω kHz.n Choose C n. 6. Calculate C by setting compensator pole p at half the swithing frequency. C p R s p.74k Ω 00kHz 5p Choose C 0p. Output Voltage Calculation Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the b pin is 0.8V when the output voltage is at the desired value. The following equation and picture show the relationship between V, VRE and voltage divider. R V RE R V -V RE...(8) where R is part of the compensator, and the value of R value can be set by voltage divider. Choose R0kΩ, to set the output voltage at Voltage divider igure - Voltage divider In general, the minimum output load impedance including the resistor divider should be less than 5kΩ to prevent overcharge the output voltage by leakage current (e.g. Error Amplifier feedback pin bias current). A minimum load for 5kΩ less (</6w for most of application) is recommended to put at the output. or example, in this application, Vout.6V The power loss is /6W less RLOAD.6V.6V/(/6W) 40Ω Select minimum load, kω should be good enough. Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply current to the MOSETs. Usually u ceramic capacitor is chosen to decouple the high frequency noise. The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as: I I D -D RMS D V...(9) V IN VIN 5V, V.6V, I6A, using equation (9), the result of input RMS current is.80a. or higher efficiency, low ESR capacitors are recommended. One Sanyo TPD series POSCAP 6TPD0M 6V 0u with mω is chosen as input bulk capacitor.

14 NX4/4A Power MOSETs Selection The NX4 requires two N-Channel power MOSETs. The selection of MOSETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSET on resistance and power dissipation. The main consideration is the power loss contribution of MOSETs to the overall converter efficiency. In this design example, two airchild DS694 are used. They have the following parameters: VDS0V, ID A, R DSON 4.4mΩ,QGATE 0nC. There are three factors causing the MOSET power loss: conduction loss, switching loss and gate driver loss. Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits. It is proportional to frequency and is defined as: P (Q V + Q V )...(0) gate HGATE HGS LGATE LGS S where QHGATE is the high side MOSETs gate charge, QLGATE is the low side MOSETs gate charge, VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. According to equation (0), PGATE 0.0W. This power dissipation should not exceed maximum power dissipation of the driver device. Conduction loss is simply defined as: P I D R K HCON DS(ON) P I ( D) R K LCON DS(ON) P P + P TOTAL HCON LCON...() where the RDS(ON) will increases as MOSET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K equals to.4 at 5 o C according to DS694 datasheet. Using equation (), the result of PTOTAL is 0.75W. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. P V I T SW IN SW S...() where I is output current, TSW is swithing time,and S is switching frequency. Swithing loss PSW is frequency dependent. Soft Start, Enable and shut Down The NX4 has a digital start up. It is based on digital counter with 04 cycles. or NX4 with 00kHz operation, the start up time is about.5ms. or NX4A with 600kHz operation, the start up time is about half of NX4,.75mS. NX4/NX4A can be enabled or disabled by pulling COMP pin below 0.V. The function is illustrated in the following diagram. During the normal operation, the lowest COMP voltage is clamped to be about 700mV, the COMP voltage is higher than 0.V. If external switch with 0Ω R dson or less to pull down COMP pin, when COMP is below 0.V, the digital soft start will be reset to zero. All the drivers will be off. The synchronous buck is shut off. When external switch is released, and COMP is above 0.V, a soft start will initiates and system starts from the beginning. O Compensation Network ON comp B V.V Clamp Shut down igure 4 - Enable and Shut down NX4 by pulling down COMP pin. eedback Under Voltage Shut Down NX4 relies on the eedback Under Voltage Lock Out (B UVLO ) to provide short circuit protection. Basically, NX4 has a comparator compare the feedback voltage with the B UVLO threshold 0.4V. 4

15 NX4/4A During the normal operation, if the output is short, the feedback voltage will be lower than 0.4V and comparator will change the state. After certain internal delay, both high side and low side driver will be turned off. The output will be latched. The normal operation should be achieved by removing the short and recycle the VCC. igure 5 - Operation waveforms during short condition. CH-bus voltage 5V/DIV CH-Vcc voltage 5V/DIV CH-b voltage 0.5V/DIV CH4-output current 0A/DIV igure 6 - Operation waveform with start up at short. During the start up, the output voltage is discharged to zero by the synchronous ET. B voltage starts increase from zero when digital start block operates. Before half of the start up time, the eedback Under Voltage Lock Out comparator is disabled. After half of start up time, the eedback UVLO comparator is enabled. The B UVLO threshold is set to be half of voltage at the positive input of error amplifier. With this set up, if the output is short before soft start, the eedback UVLO comparator can catch it and turn off the driver. The short circuit operation waveform during normal operation and during the soft start are shown as follows. During the normal operation, eedback UVLO will take the role. But during the soft start, due to the input voltage dropping, UVLO Vcc will take the role, hiccup happens. The eedback UVLO can provide short circuit protection under certain conditions. However, since feedback does not have accurate information of current, this protection only provides certain level of over current protection. MOSET should design such that it can survive with high pulse current for a short period of time. Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSET, low-side MOSET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended. Layout guidelines:. irst put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them.. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic 5

16 NX4/4A cap which usually is u need to be practically touching the drain pin of the upper MOSET, a plane connection is a must.. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSET and source of the high-side MOSET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to B needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 0. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC.. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. 6

17 NX4/4A TYPICAL APPLICATION Single Supply 5V Input Vin L uh +5V C4 u C R 0 D MBR050T C5 u Cin x (470u,60mohm) C 50p u C 8.n R4 7k 7 6 C6 u b 5 Vcc Comp NX4 Gnd BST Hdrv SW Ldrv 8 4 C7 0.u M M L.5uH Vout +.5V,0A Co 4 x (0u,80mohm) R 4.7k % R 0k % igure 7 - Application of NX4 for 5V input and.5v output with electrolytic capacitors Vin L uh +5V C 4.7p C u C4 u 7 C 0p R4 0k 6 C6 u 5 Comp b Vcc R 0 NX4A Gnd BST Hdrv SW Ldrv 8 4 D MBR050T C7 0.u C5 u M M L.uH Cin x u X7R Co 0 x u X7R Vout +.V,4A R 0k % R 787 R 0k % C 80p igure 8 - Application of NX4 A for 5V input and.v output with ceramic output capacitors 7

18 NX4/4A TYPICAL APPLICATIONS(CONT') Dual power supply (+5V BIAS,+V BUS) Vin L uh +V C u C5 u Cin x (47u,60mohm) Vin +5V R5 0k R6 680 R8 k R7 5 k N904 N904 C 70p C6 u 7 C 5n R4.74k 6 5 Comp b Vcc NX4 Gnd BST D MBR050T Hdrv SW Ldrv 8 4 C4 0.u M M L.5uH Vout +.V,0A Co x (680u,4mohm) R.4 k % R 0. k % igure 9 -Application of NX4 for 5V bias and V input bus Single power supply (+V to +4V BUS) Vin L uh +~5V C4 u R5 k N904 C5 u Cin x (47u,60mohm) TL4 C 0p R6 0 k R7 0 k 7 C.7n R4 5k 6 C6.u 5 Comp b Vcc NX4 Gnd BST D MBR050T Hdrv SW Ldrv 8 4 C7 0.u M M L 5uH Vout +.6V,5A Co x (680u,4mohm) R 0 k % R 0k % R C 787 n igure 0 -Application of NX4 for high input bus application 8

19 NX4/4A SOIC8 PACKAGE LINE DIMENSIONS 9

20 NX4/4A 0