Efficient Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers

Transcription

1 1 Efficient Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers Sridhar Rajagopal Srikrishna Bhashyam Joseph R. Cavallaro Behnaam Aazhang Sridhar Rajagopal Srikrishna Bhashyam Joseph R. Cavallaro and Behnaam Aazhang are affiliated with the Center for Multimedia Communication, Department of Electrical and Computer Engineering MS-366, Rice University, 6100 Main St., Houston, TX This work was supported in part by Nokia Corporation, Texas Instruments Inc., the Texas Advanced Technology Program under grants and , and by NSF under grants NCR and ANI July 28, 2000 DRAFT

2 2 Abstract This paper presents efficient algorithms and architecture designs that can meet real-time requirements of multiuser channel estimation and detection in future wireless base-station receivers. Sophisticated algorithms proposed to implement multiuser channel estimation and detection make their real-time implementation difficult on current Digital Signal Processor (DSP)-based receivers. A maximum-likelihood based multiuser channel estimation scheme requiring matrix inversions is redesigned from an implementation perspective for a reduced complexity, iterative scheme with a simple fixed-point VLSI architecture. A reduced-complexity, bit-streaming multiuser detection algorithm that avoids the need for multishot detection is also developed for a simple, pipelined VLSI architecture. Thus, we show that real-time solutions, with 3-4 orders of magnitude performance improvements over DSPs, can be achieved for next generation wireless systems by (1) designing the algorithms from an implementation perspective, without significant loss in error rate performance, (2) task partitioning and (3) designing bit-streaming fixed-point VLSI architectures to exploit available pipelining, parallelism and bit-level computations. Keywords Wireless communications, real-time implementation, multiuser channel estimation, multiuser detection, VLSI architecture, Digital Signal Processors, W-CDMA, base-stations, fixed point I. INTRODUCTION Next generation wireless cellular systems [1], [2], are being designed to support extremely high data rates (in Mbps) and Quality-of-Service (QoS) guarantees required for multimedia communication. Wideband Code-Division Multiple Access (W-CDMA) [3] has been chosen as the multiple access protocol to support these features. The existing narrowband CDMA IS-95 standard supports only voice and low-data rates up to 9.6 Kbps and uses single-user algorithms at the base-station receiver that ignore Multiple Access Interference (MAI) between different users. To achieve improved performance at these high data rates requires the implementation of highly sophisticated and complex multiuser algorithms for channel estimation and detection. These algorithms combat MAI by jointly processing the signals of all users at the base-station receiver. This leads to a large increase in implementation complexity for the receiver due to the matrix-oriented multiuser algorithms involving matrix multiplications and inversions [4]. This also usually requires block-based computations and floating point accuracy, which add to the implementation complexity of the receiver. A direct implementation of these multiuser algorithms using current generation DSP-based base-station receivers fails to meet third generation DRAFT July 28, 2000

3 3 real-time requirements [5]. Therefore, only single user algorithms for channel estimation and detection [6], [7] have been implemented in all current practical CDMA systems, such as IS-95. Implementations for multiuser detection have been studied in [4], [8], [9], [10]. However, these detector implementations either assume perfect channel estimation or assume single user estimation using sliding-correlator type structures [11]. The detector implementations also assume that channel estimation is done in real-time and the data rates are considered to be dependent only on the detector. However, many advanced multiuser channel estimation schemes [6], [12] have high computational complexity, even more than that for multiuser detection, due to matrix inversions involved and cannot be performed in real-time. Also, algorithms for estimation and detection are block-computation based due to the need for repeated inversion updates for estimation [13] and multi-shot detection [14], [15], which make their real-time implementation more difficult. Jointly performing multiuser channel estimation and detection is shown to have lower computational complexity and better error rate performance than performing multiuser estimation and detection separately [13] as the detector uses the channel estimate matrix directly without extracting the parameters such as multipath delays and amplitudes. Hence, we shall consider this joint algorithm for multiuser channel estimation and detection for redesign from a VLSI architecture perspective. In [5], we have shown that a multi-processor based DSP-solution can meet real-time requirement for these algorithms as there is significant parallelism in the algorithms. However, the number of processing elements required and the communication overheads make their implementation infeasible. However, the parallelism and bit-level computations in these algorithms that are not well exploited on DSPs, can be well-revealed and exploited by a VLSI architecture. In this paper, we present efficient algorithms for multiuser channel estimation and detection, designed from an implementation perspective and their mapping to real-time VLSI architectures. We redesign a multiuser channel estimation algorithm [13], based on the maximum likelihood principle and present an iterative scheme, which is computationally effective, suitable for a fixed point implementation and is equivalent to matrix inversion in terms of error rate performance. A new bit-streaming multiuser detection scheme based on parallel interference cancellation is presented that avoids the need for multishot detection [14], [15] for a simple pipelined VLSI architecture. VLSI architectures for multiuser channel estimation and detection are developed July 28, 2000 DRAFT

4 4 using time-constrained designs. We have considered different area-time tradeoffs to develop real-time architectures with minimum area overhead in earlier work [16]. The time-constrained design helps us to exploit the available parallelism, pipelining and bit-level computations to achieve data rates far greater than those targeted for next generation real-time requirements. Thus, the main contribution of this paper is to show real-time performance for multiuser algorithms by (1) designing the algorithms from an architecture perspective, without significant loss in error rate performance, (2) task partitioning and (3) designing bit-streaming fixed point VLSI architectures to exploit available pipelining, parallelism and bit-level computations. We concentrate on the base-station receiver and neglect power issues in our considerations. The architecture design considerations for the mobile handset has to be power-efficient [9] and this also needs to be accounted for in the design as a critical parameter. Architectures for the mobile handset have similar algorithms for implementation. Blind versions [17] of these algorithms are available for the mobile handset. However, in this case, the channel is synchronous and only a single user has to be detected which reduces the computational complexity. The organization of this paper is as follows. The next section provides an introduction to multiuser channel estimation and detection and their real-time requirements. In section 3, the reduced complexity bit-streaming algorithms for multiuser channel estimation and detection are presented. The multiuser channel estimation algorithm is augmented for a reduced complexity fixed point solution, without loss in error rate performance. A new bit-streaming multiuser detection algorithm is presented which avoids the need for multishot detection for a highly pipelined and efficient VLSI architecture. Section 4 shows the task partitioning of the algorithms and presents real-time time-constrained VLSI architectures for multiuser channel estimation and multiuser detection along with their hardware requirements and time complexity. The results in terms of computational time savings and comparisons with DSP-based solutions are provided in section 5. The conclusions and summary are presented in section 6. II. MULTIUSER CHANNEL ESTIMATION AND DETECTION In this section, we present the real-time requirements for next generation wireless cellular systems. Then, we develop the system model and describe the multiuser channel estimation and detection algorithms that need to be implemented in real-time. We redesign these algorithms for real-time VLSI architectures with reduced complexity in the later sections. DRAFT July 28, 2000

5 5 A. Real-time requirements Data transmission in next generation wireless systems [1] will be done in frames of 10 ms using a chip rate of Mcps. The data transmission can be done in variable rates depending on the spreading factor (N), as shown in Table I (from 3GPP standards [18]). Spreading factor refers to the number of transmitted symbols (chips) per information symbol [3]. The table gives an example of the number of bits in a frame for spreading factors of 4, 32 and 256 chips per data bit using orthogonal Walsh codes. To support real-time, the number of bits detected per frame should be at the rate of transmission. We implement our design assuming a spreading factor of 32 chips per data bit. This implies that the real-time requirement of the joint estimation and detection scheme is to detect input data bits at a rate of 128 Kbps i.e. one bit of every user has to be estimated and detected in less than s, assuming that the estimation and detection blocks will be pipelined. We use the data rate of 128 Kbps as the target data rate for our proposed VLSI architectures in an overloaded W-CDMA system with 32 users (N =32, K =32) in our architecture design specifications. B. Received signal model We assume Binary Phase Shift Keying (BPSK) modulation for the transmitted signal. This scheme uses spread spectrum signaling, where each active user uses a unique signature sequence (spreading code) to modulate the data bits. The base-station receives a summation of the signals of all the active users after they travel through different paths in the channel. These channel paths induce different delays, attenuations and phase-shifts to their signals and the mobility of TABLE I PROPOSED DATA RATES FOR NEXT GENERATION COMMUNICATION SYSTEMS. THIS TABLE SHOWS THE DESIRED DATA RATES FOR SPREADING FACTORS OF 4, 32 AND 256 FOR W-CDMA. Spreading Factor Bits Per Data Rates (N) Frame (Bits per second) Mbps Kbps Kbps July 28, 2000 DRAFT

6 6 the users causes fading in the channel. Moreover, the signals from different users interfere with each other in addition to the Additive White Gaussian noise (AWGN) present in the channel. Multiuser channel estimation refers to the joint estimation of these unknown parameters for all users to mitigate these undesirable effects and accurately detect the received bits of different users. Multiuser Detection refers to the detection of the received bits for all users jointly by canceling the interference between the different users. The model for the received signal at the output of the multipath channel [13] can be expressed as r i = Ad i + i (1) where r i 2 C N is the received signal vector after chip-matched filtering [7], [15] due to the bits of all K asynchronous users, spread with a spreading factor N, A 2 C 2KN is the effective spreading code matrix, containing information about the spreading codes, attenuation and delays from the various paths, d i 2 f;1 +1g 2K = [d 1 i;1 d 1 i ::: d K i;1 d K i ] > are the bits of K users to be detected, i is AWGN and i is the time index. The size of the data bits of the users d i is 2K as we assume that all paths of all users are coarse synchronized within one symbol period from the arbitrary timing reference. Hence, only two symbols of each user will overlap in each observation window. This model can be easily extended to include more general situations for the delays [19], without affecting the derivation of the channel estimation algorithms. The estimate of the matrix A contains the effective spreading code of all active users and the channel effects and is used for accurately detecting the received data bits of different users. We will call this estimate of the effective spreading code matrix, ^A, our channel estimate as it contains the channel information directly in the form needed for detection. C. Maximum likelihood channel estimation The channel estimation and detection block in the base-station receiver is shown in Figure 1. The channel information is obtained by transmission of a pilot signal, b(known) 2 f;1 +1g 2K, which is a sequence of bits that are known at the receiver (training sequence). The received pilot signal, r(pilot) 2 C 2K, is compared with the known bits to form an estimate of the channel. However, the pilot sequence may not be available continuously, as in the specifications for the third generation communication systems [18]. In this scenario, the decisions from the multiuser detection block, ^d, are fed back to the channel estimation block along with the DRAFT July 28, 2000

7 7 received data bits, r(data), delayed by the time required for detection, for tracking the channel estimates when the pilot signal is absent. The derivation of the joint estimation and detection algorithm chosen for redesign with an implementation perspective is detailed in [13]. The multiuser channel estimation algorithm is based on the maximum likelihood principle, where the probability of received input given the transmitted bits is maximized. The computations that occur during the estimation phase [13] are: R br = 1 L R bb = 1 L LX LX i=1 i=1 b i r H i (2) b i b T i (3) where L is the length of the pilot sequence, R br 2 C 2KN is the cross-correlation matrix between the pilot bits, b i, and the received signal, r i, and R bb 2 R 2K2K is the auto-correlation matrix. The correlation matrices are averaged over a window of length L. The effective spreading code matrix containing the channel estimates can be obtained by solving R ^A bb = R br : (4) The channel estimate ^A is used for accurately detecting the unknown bits. The detected bits, ^d, which are obtained at the detection stage, are fed back to the estimation block for tracking purposes for a fading channel and to the rest of the processing blocks in the base-station receiver. It is difficult to maintain numerical stability for matrix inversion (equation (4)), using decomposition techniques such as QR or LU, with fixed point. Also, tracking requires the rebuilding of the correlation matrices and computing the inverse for every update, which is computationally inefficient. Hence, we present a redesigned scheme for meeting the real-time requirements, which eliminates matrix inversion by an iterative scheme. D. Multiuser Detection Multiuser detection cancels the interference from other users to improve the error rate performance, compared to the traditional single user detection using only a matched filter [7]. We implement the multistage detection method [14], based on the principle of Parallel Interference Cancellation. This scheme cancels the interference from different users, successively in stages July 28, 2000 DRAFT

8 8 and is shown to have computation complexity linear with the number of users. It is possible to feed the channel estimate matrix directly into the multistage detector instead of explicitly extracting the parameters. The channel matrix A is rearranged into its odd and even columns A 0 A 1 2 C NK which corresponds to the successive bit vectors d i;1 and d i, which are to be detected. In vector form, the received vector is 2 d 1 i;1. 3 r i = [A 0 A 1 ] 64 d K i;1 d 1 i. d K i 75 + i : (5) D.1 Matched Filter Detector The bits, d i, of the K users to be detected lie between the received signal r i and r i;1 boundaries. The matched filter detector [7], [15] does a correlation of the input bits with the received bits. Hence, the matched filter detector can be represented as ^d i = sign(<[a H 1 r i;1 + A H 0 r i]): (6) The multistage detector uses the matched filter to get an initial estimate of the bits and then subtracts the interference from all other users. D.2 Multistage Detector The multistage detector [14], [20] performs parallel interference cancellation iteratively in stages. To subtract the interference, the interfering bits from other users are removed. The desired user s bits receive interference from the past or future overlapping symbols of different users because they are asynchronous. The effect of interference from the past and future symbols of users is as shown in Figure 2. To subtract interference from other users succeeding incoming bits, a block based detection scheme is typically used. Detecting a block of bits simultaneously (multishot detection) can give performance gains [15]. However, in order to do multishot detection, the above model should DRAFT July 28, 2000

9 9 be extended to include multiple bits. Let us consider D bits at a time (i =1 2 D). So, we form the multishot received vector r 2 R ND by concatenating D vectors (r i i =1 2 D). r = 2 64 A 0 A A 0 A A 0 A d 1 1. d K 1. + i : (7) Let A2C NDKD represent the new multishot channel matrix. We now proceed to the detection part of the algorithm, which uses the computed channel estimates. The multistage multiuser detector needs initial estimates of the bits for performing the detection iteratively. The initial soft decision outputs y (0) 2 R KD and hard decision outputs ^d (0) 2 R KD of the detector are obtained from a matched filter as y (0) = <[A H r] (8) ^d (0) = sign(y (0) ) (9) y (l) = y (0) ;<[A H A;diag(A H A)]^d (l;1) (10) ^d (l) = sign(y (l) ) (11) where y (l) and ^d (l) are the soft and hard decisions respectively, after each stage of the multistage detector. These computations are iterated for l =1 2 M where M is the maximum number of iterations chosen for convergence. 2 The structure of A H A2C KDKD is as shown: d 1 D. d K D A H 0 A 1 A H 0 A A H 1 A 0 A H 0 A 0 + A H 1 A 1 A H 0 A A H A 1 0 A H A A H A : (12) The tri-diagonal block-toeplitz nature of the matrix arises due to the assumption of the static nature of the channel during the detection window and assuming that the asynchronous delays of July 28, 2000 DRAFT

10 10 the different users are coarse synchronized within one symbol duration [13], [19]. We exploit the tri-diagonal nature of the matrix later, for reducing the complexity and pipelining the algorithm effectively. The hard decisions, ^d, which are made at the end of the final stage, are fed back to the estimation block in the decision feedback mode for tracking in the absence of the pilot signal and to the rest of the processing blocks in the receiver. The soft decisions, y, could also be forwarded to the decoding stage in a joint detection and decoding scheme [21] for enhanced performance. There have been detectors proposed using differencing methods [20] to take advantage of the convergence behavior of the iterations. These detectors work on the principle that if there is no change in the sign of the detected bit in succeeding stages, the difference becomes zero and this fact is used to reduce the computations. However, the advantage is useful only in case of sequential execution of the detection loops in programmable DSPs. Hence, we do not implement the differencing scheme in our design for a VLSI architecture. III. EFFICIENT ALGORITHMS FOR MULTIUSER CHANNEL ESTIMATION AND DETECTION In this section, we present reduced complexity schemes for multiuser channel estimation and detection, which lead to efficient VLSI architectures. The previously existing channel estimation scheme is enhanced for an iterative scheme that avoids matrix inversions and has a simple fixed point architecture. The multiuser detection is enhanced for a highly pipelined and bit-oriented scheme which has a simple and effective VLSI architecture. A. Iterative scheme for channel estimation A direct computation of the maximum likelihood based channel estimate ^A involves the computation of the correlation matrices R bb and R br, and then the computation of R ;1 bb R br at the end of the preamble (pilot). The inversion at the end of the preamble is computationally expensive and delays the start of detection beyond the preamble. This delay limits the information rate. In our iterative algorithm, we approximate the maximum likelihood solution based on the following ideas: 1. The product R ;1 bb R br is directly approximated using iterative algorithms such as the gradient descent algorithm [22]. 2. The iterative algorithm is enhanced to update the estimate as the preamble is being received DRAFT July 28, 2000

11 11 rather than waiting until the end of the preamble. Thus, the computation per bit is reduced by spreading the computation over the entire preamble. We present an iterative gradient-based adaptation scheme for matrix inversion. The channel estimate, ^A, is updated iteratively every bit and is available immediately after the end of the pilot sequence. The updating of the estimate is done using the iterative scheme as shown below: R (i) br = R (i;1) br + b i r H i ; b i;lr H i;l (13) R (i) bb = R (i;1) bb + b i b T i ; b i;lb T i;l (14) ^A (i) = ^A (i;1) ; (R (i) bb ^A (i;1) ; R (i) br ) (15) The auto-correlation and cross-correlation matrices are formed by accumulating the correlations over the length of the pilot (preamble) and are updated during the tracking phase by calculating the matrices over a sliding window. Correspondingly, the term b i;lb T i;l in equations (13) and (14), representing the correlation contribution from the oldest bit in the window, is not required during the preamble while it is required to obtain the sliding window estimate during tracking. Tracking is simpler in this iterative scheme as the channel estimates and correlation matrices are updated iteratively. Only a few iterations need to be performed for a slowly fading channel and the previous estimate serves as a very good initialization. During the initial pilot phase, tracking is absent and the equations for correlation (equations (13)-(15)) reduce to the previous estimation scheme using inversion (equations (2)-(4)). Another advantage of this scheme is that it lends itself to a simple fixed point solution, which was difficult to achieve using the previous inversion scheme based on maximum likelihood [13]. There are no divisions except for the multiplication by the convergence parameter which can be implemented as a right-shift, by making it a power of two. This can be done as the algorithm converges for a wide range of [23]. This algorithm shows good convergence behavior as R bb is a symmetric, positive definite matrix and has a small condition number [22]. A detailed analysis of this scheme is presented for long codes in [23] and a similar analysis is valid for the short code case as well. For simulation purposes, we assume a Gold code of length 31. We choose this code for W-CDMA [18] as it has desirable auto-correlation and cross-correlation properties for an asynchronous transmission scheme. Figure 3 shows the performance of both schemes, the iterative method and the previous scheme using matrix inversion for a static multipath environment. The July 28, 2000 DRAFT

12 12 Bit Error Rate (BER) is calculated using the channel estimates after the end of the pilot phase for two types of detectors, a Matched Filter Detector (MF) [7], [15] and a Multistage Multiuser Detector (MUD) [14]. The simulations are carried out for a pilot of length 150 bits, having 3 paths, for 15 users, all transmitting at the same power and for a detection window length of 12. The simulation was carried out for bits per user. The value of for the iterative scheme was chosen to be From the simulations, it can be observed that the iterative scheme (ITER) essentially gives the same error rate performance as that of the original scheme. The analysis of the system for a multipath fading channel with tracking is as shown in Figure 4. Here we see that the proposed tracking scheme based on the update equations (13)-(15) is able to effectively track the time-varying channel. The poor performance of the static channel assumption for this Rayleigh fading channel (with mobile velocity 10 Kmph) shows the importance of tracking. The simulation was done using 1000 bits per user for 15 equal-power users. The original channel estimation scheme using matrix inversions would require a matrix inversion followed by a matrix multiplication for every update while the iterative scheme reduces the complexity to a matrix multiplication per update. B. Pipelined Detection The multishot detection scheme [14] proposed in the earlier section is block-based as it requires computation of succeeding incoming bits of users, which are not available. This results in taking a window of (D+2) bits and using it to detect D bits as the edge bits are not detected accurately due to windowing effects. Thus, there are 2 additional computations per block and per iteration that are not used. Also, such a block-based implementation needs a windowing strategy and has to wait until all the bits needed in the window are received and are available for computation. This is as shown in Figure 5 for a detection window of length 10. It can be observed that the detection is done in blocks of 12 bits, and the edge bits are thrown away and recalculated in the next iteration. However, the stages in the multistage detector can be efficiently pipelined to avoid edge computations and to work on a bit streaming basis. This is equivalent to the normal detection of a block of infinite length, detected in a simple pipelined fashion. Also, the computations can be reduced to work on smaller matrix sets. This can be done due to the block Toeplitz nature of the matrix ^A H ^A as seen from equation (12). The computations performed on DRAFT July 28, 2000

13 13 the intermediate bits reduce to L = <[ ^A H 1 ^A 0 ] (16) C = <[ ^A H 0 ^A 0 + ^A H 1 ^A 1 ; diag( ^A H 0 ^A 0 + ^A H 1 ^A 1 )] (17) y (l) i = y (0) i ; L^d (l;1) i;1 ; C^d (l;1) H (l;1) i ; L ^d i+1 (18) ^d (l) i = sign(y i (l) ) (19) Equation (18) may be thought of subtracting the interference from the past bit of users, who have more delay, and the future bits of the users, who have less delay than the desired user. The left matrix L 2 R KK, stands for the partial correlation between the past bits of the interfering users and the desired user, the right matrix L H, stands for the partial correlation between the future bits of the interfering users and the desired user. The center matrix C 2 R KK, is the correlation of the current bits of interfering users and the diagonal elements are made zeros since only the interference from other users, represented by the non-diagonal elements, needs to be cancelled. The lower index, i, represents time, while the upper index, l, represents the iterations. The initial estimates are obtained from the matched filter. The above equation (18) is similar to the model chosen for output of the matched filter for multiuser detection in [24]. The equations (16)-(19) are equivalent to the equations (8)-(11), where the block-based nature of the computations are replaced by bit-streaming computations. The detection can now be pipelined as shown in Figure 6. An example highlighting the calculation of bit 3 in the detector is shown. An initial estimate of the received signal is done using a matched filter detector, which depends only on the current and the past received bits. The stages of the multiuser detector need bits 2 and 4 of all users to cancel the interference for bit 3. Hence, the first stage can cancel the interference only after the bits 2 and 4 estimates of the matched filter are available. The other stages have a similar structure. Hence, while bit 3 is being estimated from the final stage, the matched filter is estimating bit 9, the first stage bit 7 and the second stage bit 5. There are no edge bit computations in this scheme and hence, they can be avoided and recalculated in the next iteration as the window progresses. Thus, we get 2=(D +2)savings in computation per detection stage, where D is the detection window length. Also, instead of detecting a block of bits together, each bit is detected in a streaming fashion. July 28, 2000 DRAFT

14 14 IV. TASK DECOMPOSITION AND VLSI ARCHITECTURES VLSI architectures for multiuser channel estimation and detection, which accelerate their implementation and meet real-time requirements, are presented in this section. The task partitioning of the algorithm into sub-blocks is carried out for pipelining and for utilizing the inherent parallelism present in the channel estimation and detection. We have presented a complete areatime tradeoff analysis of the VLSI architecture for channel estimation in [16]. Here, we focus only on a time-constrained architecture for both channel estimation and detection as a timeconstrained design gives an estimate of the maximum available parallelism. A time-constrained solution for detection is also presented to reveal the amount of bit-level parallelism and the advantages due to pipelining. Since both the time-constrained estimation and detection architectures are shown to far exceed the targeted data rates, an area-time optimal architecture that meets the data rate requirements with minimum area overhead could be easily developed. A. Task decomposition of multiuser channel estimation and detection The various sub-blocks in the joint multiuser channel estimation and detection algorithm are as shown in Figure 7. The figure shows the blocks required for channel estimation, the glue matrices L C between channel estimation and detection and the blocks in the detector. The blocks that are pipelined are shown on the horizontal time axis while the blocks that have coarsegrained parallelism are shown along the vertical axis. The task decomposition is as shown in Figure 8. The figure shows that the correlation matrices can be formed in parallel and this can be pipelined with the iteration of the channel estimate matrix. The two multiplexers shown are for selecting between the known pilot and the received pilot signal during the training mode and the detected bits and the received data signal in the tracking phase. The tracking window is the history buffer and keeps the L most recent samples of the bits as well as the received signal. The sizes of the sub-blocks are shown along with their fixed point word lengths in Figure 8. The dynamic range of the input is dependent on Signal-to-Noise ratio (SNR), the Multiple Access Interference (MAI) and the number of users in the system. A detailed analysis is required to determine the word-length of the input. For our design, we assume that the received signal is quantized by an A/D converter to have a fixed precision word-length of 8 bits as a similar dynamic range analysis [4], [20] for detection shows that 8-bit precision is sufficient. However, DRAFT July 28, 2000

15 15 the analysis of the algorithm presented here is independent of the word-length. Also note that the blocks r, R br and ^A are complex-valued while b and R bb are real-valued. For the sake of convenience, we henceforth represent the current inputs b i, r i as b, r and b i;l, r i;l as b 0, r 0 respectively. A typical architecture specification has window length L = 150, spreading gain N = 32 and the number of users K = 32. All the architectures assume a single-cycle 8-bit multiplication and addition as both multiplication and addition can be implemented in log(n) type computations [25] where n is the number of bits and the single cycle assumption also helps us with the DSP comparisons. We assume that a Wallace or Dadda multiplier tree [25] is used for multiplication requiring O(n 2 ) 1-bit Full Adders for an n-bit multiplication. Since the multiplication by in equation (15) results in truncation of the output and need not be highly accurate for numerical stability, a truncated multiplication using significantly less hardware [26] can be used. The delays of blocks such as multiplexers and gates are assumed to be included in the single-cycle delay. For an area estimate of the architectures, we consider the number of 1-bit Full Adder cells in the design. We also assume all blocks can be pipelined effectively. It can be observed from Figure 7 that the bottlenecks in the pipeline are the matrix multiplications R bb ^A for channel estimation and the matched filter computations (equation (8)) for multiuser detection. B. Time-constrained channel estimation architecture The block diagram of a time-constrained architecture is as shown in Figure 9. In this architecture, the available parallelism in the algorithm is exploited to the maximum extent. Hence, all the elements needed to perform a parallel multiplication are computed simultaneously and are pipelined. The entire matrices R bb and ^A are multiplied using an array of multipliers. The entire product matrix is subtracted by the auto-correlation matrix, R br, shifted and a new channel estimate is formed. Thus, as the time taken by the other computations is pipelined with the time for the multiplication, the output matrix can be formed in parallel every log 2 (2K) +1or 7 cycles using 4K 2 N multipliers. This is because each element of a N N product matrix can be computed in log 2 (N )+1time using N 3 multipliers and using a tree structure to compute the inner products [27], in a time-constrained architecture. We also exploit the bit-level arithmetic and parallel structure of the correlation matrices to form the correlation matrices simultaneously within a cycle. The sub-blocks for the formation July 28, 2000 DRAFT

16 16 TABLE II HARDWARE REQUIREMENTS FOR A TIME-CONSTRAINED ESTIMATION ARCHITECTURE. THIS TABLE SHOWS THE NUMBER OF 1-BIT FULL ADDER CELLS AND THE TIME DELAY FOR A TIME-CONSTRAINED ARCHITECTURE. K-NUMBER OF USERS, N-SPREADING GAIN. Blocks Quantity Full Adder Complex Total Time Cells FA cells (Cycles) Multipliers 4K 2 N 8 256K 2 N *2 512K 2 N Counters 2K K 2-16K 2 Adders 2KN 16+2KN 8 48KN *2 96KN+ log 2 (2K) +1 +4K 2 N K 2 N 128K 2 N Total (N=K=32) 20,000,000 7 of the auto-correlation matrix and cross-correlation matrix are shown in Figures 10 and 11. Since the auto-correlation matrix update is a symmetric matrix and all the diagonal elements are 1 s (a a = 1), we need to compute only the strictly upper triangular (or lower triangular) part of the auto-correlation matrix (Figure 10). Also, as the updates are all +1 s or -1 s, this can be obtained from a simple single-bit XNOR gate structure. As the auto-correlation matrix is always updated and down-dated by 1 s, increment/decrement counters can be used in place of general adders in our design. Also, the elements in the cross-correlation update are +r or ;r and hence, the vector r could be directly added or subtracted with every column of the autocorrelation matrix based on the sign of the bit vector b. The hardware requirements for the timeconstrained architecture are as shown in Table II. For a typical architecture, the number of Full Adder Cells required is 20,000,000. This is a highly aggressive solution with today s technology and it is not feasible to devote so many FA cells just for channel estimation, which is only a part of the complete receiver. However, this states the theoretical minimum time requirements by exploiting the available parallelism as log 2 (2K) or 6 cycles, which is the time required to do the parallel multiplication and pipelined integration with the other blocks. We require 2KN(2K ;1) 16-bit adders for doing the recursive doubling [27] in log 2 (2K) time (adding 2K elements in log 2 (2K) time requires (2K ; 1) adders) and 2KN 16-bit adders for the subtraction following the multiplication. DRAFT July 28, 2000

17 17 C. Time-constrained multiuser detection architecture A detailed task partition of the blocks for multiuser detection are as shown in Figure 12. The blocks consist of a matched filter detector which provides the initial hard (^d) and soft estimates (y) to the parallel interference cancellation stages. A three-stage detector is chosen for implementation as it provides sufficient convergence [20]. An array of parallel multipliers is used for computing the entire matched filter estimate ^A H 0 r and ^A H 1 r vectors in parallel. As the imaginary parts of the products need not be computed, this requires 4KN 8-bit multipliers. To form the inner product addition in parallel for every row of ^A H and ^A H 0 1, we use an adder tree utilizing K(2N ; 1) 16-bit adders. The matched filter estimate can be computed in log 2 (N )+2time. The glue matrices, L, C, between the channel estimation and detection schemes require a significant amount of computation. Since ^A H ^A 0 0 and ^A H ^A 1 1 are symmetric and their diagonal elements and imaginary parts need not be computed (equations(16)-(17)), to compute the matrix products in a time-constrained architecture, we require 2K(K ; 1)N 8-bit multipliers and K(K ; 1)(4N ; 1)=2 16-bit adders to find the dot products in a tree fashion. This requires log 2 (K) +3time. Similarly, for the computation of ^A H ^A 1 0, we require 2K 2 N 8-bit multipliers and K 2 (2N ; 1)16-bit adders in log 2 (N )+2time. Each stage of the multiuser detector uses only adders as multiplication by single bits can be reduced to addition and subtraction. In order to form the various vectors such as C^d i in equation (18), we can use an adder tree as shown in Figure 13. The multiplication by the bits can be substituted by a 2 s complement representation in case the bit is -1 (shown as 2C with a circle in the figure) and left unchanged when the bit is 1. Then, 2K ; 1 16-bit adders are utilized for adding all the bits including the 2 s complement conversion. Thus, for computing L^d i;1, C^d i and L H ^d i+1, we need 3(2K ; 1) 16-bit adders followed by 3K more adders (for a 4 operand tree addition) to get the final soft decisions y. Each stage of the multistage detector can be computed in log 2 (K)+3 time, assuming 2 cycles for the final 4-operand addition and a single cycle for the 2 s complement calculation. The hardware requirements for the matched filter, the glue matrices and each stage of the detector are as shown in Table III. The detector architecture also takes 10,000,000 FA cells, which is not an efficient solution with today s technology but serves to reveal the parallelism and pipelining in the algorithm and determine the maximum data July 28, 2000 DRAFT

18 18 TABLE III HARDWARE REQUIREMENTS FOR A TIME-CONSTRAINED DETECTION ARCHITECTURE. THIS TABLE SHOWS THE NUMBER OF 1-BIT FULL ADDER CELLS AND THE TIME DELAY FOR THE MATCHED FILTER(MF) AND EACH STAGE OF PARALLEL INTERFERENCE CANCELLATION (PIC). K - NUMBER OF USERS, N-SPREADING GAIN. Blocks Quantity Full Adder Time Cells (Cycles) Multipliers 4KN 8 256KN log 2 (N )+2 MF Adders K(2N ; 1) 16 32KN ; 16K Total (N=K=32) 294,000 7 Multipliers 2K(K ; 1)N 8+2K 2 N 8 256K 2 N ; 128KN L,C Adders K(K ; 1)(4N ; 1)= K 2 N ; 24K 2 log 2 (N )+3 +K 2 (2N ; 1) 16 ;32KN +8K Total (N=K=32) 10,000,000 8 PIC Adders 3(2K ; 1) K K ; 48 log 2 (K) +3 Total per Stage (N=K=32) 4,500 8 rate. V. RESULTS AND COMPARISONS In this section, the computational savings due to the new algorithms and VLSI architectures are presented. Comparisons with software implementations of the algorithms on DSPs are also presented in this section. A. Computational Savings The newly proposed schemes for simplifying hardware implementation and complexity have negligible degradation in error rate performance over previous schemes as shown from the simulations. The computational advantages of the newly proposed schemes over the previous schemes are shown in Table IV. The original algorithm for channel estimation required a matrix inversion and a matrix mul- DRAFT July 28, 2000

19 19 TABLE IV COMPARISONS OF COMPUTATIONAL TIME SAVINGS. THIS TABLE SHOWS THE COMPUTATIONAL SAVINGS ACHIEVED BY THE ENHANCED SCHEMES FOR MULTIUSER ESTIMATION AND DETECTION OVER THE PREVIOUS SCHEMES. K-NUMBER OF USERS, N-SPREADING GAIN, D-DETECTION WINDOW, M-NUMBER OF STAGES Blocks Architecture Original Enhanced (Cycles) (Cycles) Channel Uni-processor O(6K 3 +4K 2 N ) O(4K 2 N ) Estimation Parallel - O(log 2 (2K) +1) Multiuser Uni-processor O(DNK + M (D +2)K 2 ) O(DNK + MDK 2 ) Detection Parallel - O(log 2 (N )+3) tiplication requiring O(6K 3 +4K 2 N ) cycles on a sequential uni-processor machine such as a DSP while estimation using the iterative method requires only a matrix multiplication O(4K 2 N ) on a sequential machine. As N and K are of the same order, this only implies a savings of the order of 2X. However, a fully parallel VLSI solution for implementation can accelerate the time requirements to O(log 2 (2K) +1). Similarly, for comparing the detection schemes, we assume that a window of D bits need to be detected. For every window, we save O(2MK 2 ) computations, assuming an M-stage detector as the edge bits do not need to be calculated. A fully pipelined time-constrained detector can reduce the time requirements to O(log 2 (N ) +3)by exploiting available parallelism. Note that the enhanced algorithms, as seen from Table IV do not have inherent computational savings but are designed to benefit from exploiting parallelism and pipelining in an architecture. Thus, significant benefits in performance can be achieved by enhancing the existing schemes for channel estimation and detection with schemes having an efficient hardware implementation and exploiting the available parallelism. B. Comparisons with DSPs Though DSPs and general purpose processors with MMX-enhanced instruction sets can exploit byte-length parallelism, they are inefficient for bit level parallelism. Storage of bits on such a processor is either inefficient as it is stored as bytes or a large overhead is involved in pack- July 28, 2000 DRAFT

20 20 ing and unpacking these bits. Also, the compiler may not take advantage of the fact that most multiplications are with bits and replace them with additions or subtractions. Using a control structure instead also limits the utilization of available parallelism. Formation of bit-level matrix updates is much more effective and simpler to build in hardware with XNOR gates, giving O(1) performance with O(K 2 ) or 1000 XNOR gates, while it may take O(K 2 ) or 1000 cycles on a DSP and takes O(K 2 ) or 1K bytes in memory. Assuming a 500 MHz clock for the VLSI architectures, the projected time required to compute the channel estimate along with the hardware required for 32 users and a spreading code of length 32 is as shown in Table V. This is compared with the implementation of the previously existing multiuser channel estimation and detection on a TI TMS320C6701 Evaluation Module, operating at 167 MHz. The computational savings due to the improved algorithms do not yield significant performance benefits for a sequential DSP implementation and hence, are not implemented. The DSP implementation of the multiuser channel estimation algorithm using the previously existing schemes is shown to require cycles [5], which corresponds to 4.73 ms for 15 users. Usually, the number of users are typically less than half the spreading gain for good error rate performance. However, for VLSI comparison purposes, extending the problem size to 32 users, the performance translates quadratically to ms or Kbps/user as the matrix inversion is a O(K 2 N ) algorithm. This low performance can be attributed to the computation of a matrix inversion per received bit, both in the training and the decision feedback mode. The frequency of updates to the channel estimates can be reduced for slow fading channels for better time performance. Similarly, for a 3-stage detector, the time required is cycles or ms for 15 users [5]. Extending the problem size for 32 users, the performance translates quadratically to 4.01 ms or Kbps/user as multiuser detection is (O(MK 2 )). The low data rate performance of the detector is because we consider a more realistic and complete system with continuous updating of channel estimates to the detector as compared to a static channel assumption and neglecting effects of channel estimation in other detector DSP implementations such as in [20]. The comparisons of the DSP solutions with the time-constrained VLSI architectures in Table V shows the advantages of exploiting parallelism and designing efficient reduced complexity algorithms. Though the current W-CDMA real-time requirements are easily surpassed, the area DRAFT July 28, 2000

21 21 TABLE V COMPARISONS BETWEEN DIFFERENT ARCHITECTURES. THIS TABLE COMPARES VLSI ARCHITECTURES AGAINST A DSP IMPLEMENTATION. Algorithm Architecture Transistors Clock Speed Data Rates/User Channel VLSI 560,000, MHz Mbps Estimation DSP N/A 167 MHz Kbps Multiuser VLSI 280,000, MHz 62.5 Mbps Detection DSP N/A 167 MHz Kbps Real-Time Requirements 128Kbps estimates can be reduced for an area-time efficient architecture, which meets the real-time requirements within the same order of magnitude [16]. The table shows the transistor count for the VLSI architectures, assuming 28 Transistors per 1-bit Standard Full Adder Cell [25], though lower transistor count Full Adder Cells have been proposed [28]. The extreme time difference between the DSP and the VLSI architectures is due to the improvements in the algorithm enhancements, the fact that bit-level parallelism is not exploited on the DSPs, and the additional memory references for storing and retrieving bits stored as bytes. The difference in the processor speed does not play a major role in the orders of magnitude time differences. VI. SUMMARY AND CONCLUSIONS We present computationally efficient algorithms and architectures to meet real-time requirements of multiuser channel estimation and detection in future wireless base-stations. Existing algorithms for multiuser channel estimation and detection are redesigned from an implementation perspective for a reduced complexity solution, without compromising on bit error rate (BER) performance. The maximum likelihood based channel estimation algorithm requiring matrix inversions, block-based computations and floating point accuracy is redesigned for an iterative gradient-based scheme which has a simpler fixed point VLSI architecture and reduced complexity. The existing multiuser detection scheme based on parallel interference cancellation is also redesigned for a highly pipelined and reduced complexity structure. We show that VLSI architectures for baseband signal processing in a wireless base-station July 28, 2000 DRAFT

22 22 receiver can be extremely efficient in meeting real-time requirements. We present fixed point, computationally effective VLSI architectures for multiuser channel estimation and detection. Time-constrained architectures are designed to reveal and exploit the available parallelism in the algorithm and determine the maximum data rates. The VLSI architectures are able to better exploit bit level computations and parallelism available in the algorithms to achieve a real-time solution with 3-4 orders of magnitude improvements as compared to a DSP implementation. The proposed VLSI architecture schemes can be integrated with DSP architectures as a coprocessor support [29]. Bit-level extensions for DSPs [30] can also be developed based on the VLSI architectures which can accelerate algorithms with bit-level parallelism. REFERENCES [1] M. Zeng, A. Annamalai, and V. K. Bhargava, Recent advances in Cellular Wireless Communications, IEEE Communications Magazine, vol. 37, no. 9, pp , September [2] F. Adachi, M. Sawahashi, and H. Suda, Wideband DS- CDMA for Next-Generation Mobile Communication Systems, IEEE Communications Magazine, vol. 36, no. 9, pp , September [3] T. Ojanpera and R. Prasad, Eds., Wideband CDMA for Third Generation Mobile Communications, Artech House Publishers, [4] I. Seskar and N. B. Mandayam, A Software Radio Architecture for Linear Multiuser Detection, IEEE Journal on Selected Areas in Communication, vol. 17, no. 5, pp , May [5] S. Das, S. Rajagopal, C. Sengupta, and J. R. Cavallaro, Arithmetic Acceleration Techniques for Wireless Communication Receivers, in 33rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, October 1999, pp [6] S. E. Bensley and B. Aazhang, Maximum Likelihood Synchronization of a Single User for CDMA Communication Systems, IEEE Transactions on Communications, vol. 46, no. 3, pp , March [7] S. Verdú, Minimum Probability of Error for Asynchronous Gaussian Multiple-access Channels, IEEE Transactions on Information Theory, vol. IT-32, no. 1, pp , [8] N. S. Correal, R. M. Buehrer, and B. D. Woerner, A DSP-Based DS-CDMA Multiuser Receiver Employing Partial Parallel Interference Cancellation, IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp , April [9] T. Long and N. R. Shanbhag, Low-Power CDMA Multiuser Receiver Architectures, in IEEE Workshop on Signal Processing Systems, Taipei, Taiwan, October [10] C. Teuscher, D. Lee, N. Zhang, and R. Brodersen, Design of a wideband spread spectrum radio using adaptive multiuser detection, in IEEE International Symposium on Circuits and Systems, May 1998, vol. 4, pp [11] R. L. Pickholtz, D. L. Schilling, and L. B. Milstein, Theory of Spread-Spectrum Communications - A Tutorial, IEEE Transactions on Communications, vol. 30, no. 5, pp , May [12] E. G. Strom, S. Parkvall, S. L. Miller, and B. E. Ottersen, DS-CDMA synchronization in time-varying fading channels, IEEE Journal on Selected Areas in Communication, vol. 14, no. 8, pp , October [13] C. Sengupta, S. Das, J. R. Cavallaro, and B. Aazhang, Efficient Multiuser Receivers for CDMA Systems, in IEEE Wireless Communications and Networking Conference (WCNC), New Orleans, LA, September 1999, pp DRAFT July 28, 2000