conditions or constant voltage with changing load conditions Here, the pulses applies to the semiconductor switch in

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1 ISSN: X CODEN: IJPTFI Available Online through Research Article PULSE SKIPPING MODULATED BUCK CONVERTER USING MATLAB SIMULINK Y.Apoorva [1], K.Suvarchala [2], R.Thangam [3] U.G.Students 1,2, Assistant Professor 3 Department of Electrical Engineering, Saveetha School of Engineering, Chennai. apoorvay2014@saveetha.com Received on: Accepted on: Abstract The design and analysis of a buck converter using a controller is explained in detail in this paper. The controller used here is a pulse skipping modulation (PSM). PFM mode is a common technique used for improving the efficiency of step down DC DC converters using light loads. PFM mode has less switching losses. In this paper PFM of discontinuous mode in an application. The application involves a source with constant load and changing voltage conditions or constant voltage with changing load conditions Here, the pulses applies to the semiconductor switch in buck converter is blocked at some point and released at some point depending upon the threshold values of output voltage of the converter. Keywords: Pulse skipping modulation, buck converter, discontinuous conduction mode. 1. Introduction DC DC buck converter are also called as step down converters as they step down the DC voltage to a predetermined level. These are type of switch mode power supplies. Figure 1: Basic model of Buck converter. These buck converters provide higher efficiency than linear regulators, which are simpler circuits that lower voltages by dissipating power as heat, but not stepping up the current. They are used in the places where losses due to their linear counterparts are not tolerated. A pre controlled buck converter is a buck regulator which maintaions it s output voltage at desired level by varying load and input voltage consstant or by varying input voltage and load constant. IJPT Dec-2016 Vol. 8 Issue No Page 20754

2 The oupt voltage of the buck converter is nearer to the desired value is well accepted and used widely. Based on the difference between the measured voltage and the reference voltage the duty cycle continuously chnages is a voltage mode PWM controller.in this type of circuits LC circuits filters the pulse width modulated signal.especially in energy limited sources applications it is not only necessary to maintain the line and load regulations low aand it also considerable to retain losses low. Higher efficiency should be maintained throughout the operating region.in general the efficiency of PWM switching devices is high but not constant for all loads.at light load conditions the efficiency of PWM is less than in full load conditions.various control methods and toplogies are introduces for low voltage portable applications. For minimizing switching losses ZVR technique is given along with synchronous buck topology.the free wheeling diode improves the efficiency of the buck converter even though there in increase in ON resistance.several techniques including the controllers with reduced conduction losses and switching losses like DPWM and PFM are introduced.at light loads pulse skipping modulation works with higher efficiency. there will be less switching losses due to the pulse skipping at too high or too low output voltages. Varying input and load conditions the performance of pulse skipping modulation with buck convereter is shown in this paper. 2. Pulse Skipping Modulation It works based on the pulse control logic.if the actual voltage is less than the reference voltage then only the pulse signals genrated by the pulse generator are allowed by the control logic otherwise it will sip the pulses during the period of time when actual voltage crosses the reference voltage.likewise, PSM control logic in boost converter alllows the pulses when the actual voltage becomes higher than the reference voltage., otherwise it skips the pulses. Figure 2: pulse skipping modulated buck converter model circuit. The pulse skip modualtion of buck converter circuit is shown in figure1.this circuit consists of an inductor L, a capacitor C, L and C filters the ripple, a diode, MOSFET switch, and they are designed in a way that the L-C IJPT Dec-2016 Vol. 8 Issue No Page 20755

3 circuit should be normally below thw switching frequency.the PSM circit is present in the feedback circuit.as it was explained in detail above that the actual voltage is below the the reference voltage,then only it allows the pulses generated by the pulse generator otherwise if the actual voltage is beyond the reference voltage (Vref). Te pulse generated by the clock pulse is with a constant frequency constant width pulse. When the clock pulse is given, the MOSFET switch is ON. The clock pulse is over a fixed duration of time. It equals the duty cycle of the clock. Here the inductor current increases linearly. During the remaining period of time the switch is in off state.during this period the inductor current drops down, then also its value is higher than the initial value of the cycle If upcoming pulses are also skipped then its value falls to a value less than the initial value.ther by the output voltage is mintained at a value nearer to the reference voltage by alternatley permitting pulses and skipping pulses. The waveforms are shown in Figure Design Equations for Buck Converter The voltage and current relationship in an inductor is: For a constant rectangular pulse: Here we can see that when the voltage is a constant pulse, the current is a linear ramp. If the transistor is switched on, the current is: If the transistor is switched off, the current is: Where, V D =voltage drop across diode V Trans =voltage drop across the transistor When i o is zero continuous and discontinuous mode occurs. Equating (4) & (5) we get V out Duty cycle can be calculated as follows: The voltage drops across transistor and diode is neglected then: IJPT Dec-2016 Vol. 8 Issue No Page 20756

4 4. Simulation Y.Apoorva* et al. /International Journal of Pharmacy & Technology Finally as shown in figure 3, buck converter is designed using a pulse skipping modulation. It provides delay using delay circuit. The actual voltage and the reference voltage in this circuit are compared with the help of a comparator designed in it. The clock ends the output in it. By using not gate, the SR flip-flop which is reset at the falling edge of the clock is sets by the output logic gate AND as it is shown in the circuit. To drive the comparator the output pulses of SR and JK flip-flops are used. The output of the flip-flops are given to the gate of the switch by this arrangement. The output is high when the reference voltage is higher than the actual voltage. The output of the AND gate sets the flip-flop then the clock goes high and it resets at the falling edge. In this case clock pulses are given to the switch. The voltage which is produced at the output side is a desired value. This period is known as charging period. The clock pulses are not given to the switch and the flip-flop is not set as the comparator output and the AND gate output are low when the Vref is lesser than the actual voltage or when the pulses are skipped, this is known as skipping period. The simulation results also shown in the figure 5 which are obtained from the simulation. When the actual voltage is less than the reference voltage the pulses are given to the gate signal otherwise the pulses are skipped. 5. Simulation Results Figure 4: Simulation circuit for pulse skipping modulated buck converter Figure 5: voltage and inductor current response for the pulse skipping modulated buck converter. IJPT Dec-2016 Vol. 8 Issue No Page 20757

5 Figure 6: output response for pulse skip modulation device. 6. Conclusion Pulse Skipping Modulated Buck converter was designed, simulated and verified analytically using Mat lab. Response of the pulse skipping modulated converter for source voltage and load step variation was studied. The switching frequency of PSM is high and the converter response for changes was quick and the PSM controlled converter regulates the output voltage over the entire input voltage needed for operation. 7. References 1. G. Y. Wei and M. Horowitz, A Fully Digital, Energy- Efficient Adaptive Power-Supply Regulator, IEEE Journal of Solid-State Circuits, Vol. 35, April A. P. Dancy, R. Amirtharajah and A. P. Chandrakasan, High-Efficiency Multiple-Output DC DC Conversion for Low-Voltage Systems, IEEE Transactions on VLSI, Vol. 8, June S. Pattnaik, A. K. Panda, K. Aroul and K. K. Mahapatra, A Novel Zero Voltage Transition Synchronous Buck Converter for Portable Application, International Journalof Electrical, Computer, and Systems Engineering, Vol. 2, No. 2, 2008, pp A. V. Peterchev and S. R. Sanders, Digital Loss Minimizing Multi-Mode Synchronous Buck Converter Control, 35th Annual IEEE Power Electronics Specialists Conference, Vol. 6, Aachen, 2004, pp IJPT Dec-2016 Vol. 8 Issue No Page 20758