FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM E F 2 MC-8L 8-BIT MICROCONTROLLER. MB89480/480L Series HARDWARE MANUAL

Transcription

1 FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM E F 2 MC-8L 8-BIT MICROCONTROLLER MB89480/480L Series HARDWARE MANUAL

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3 F 2 MC-8L 8-BIT MICROCONTROLLER MB89480/480L Series HARDWARE MANUAL Be sure to refer to the Check Sheet for the latest cautions on development. Check Sheet is seen at the following support page URL : Check Sheet lists the minimal requirement items to be checked to prevent problems beforehand in system development. FUJITSU LIMITED

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5 PREFACE Objective and Intended Readership of This Manual Trademark Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB89480/480L series has been developed as a general-purpose version of the F 2 MC-8L family consisting of proprietary 8-bit, single-chip microcontrollers applicable as application-specific integrated circuits (ASICs). The MB89480/480L series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. This manual describes the functions and operation of the MB89480/480L series and is aimed at engineers using the MB89480/480L series of microcontrollers to develop actual products. See "F 2 MC-8L MB89600 Series Programming Manual" for details on the MB89480/480L instruction set. Note: F 2 MC is the abbreviation of FUJITSU Flexible Microcontroller. Embedded Algorithm TM is a trademark of Advanced Micro Devices, Inc. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Configuration of This Manual This manual consists of the following 17 chapters and an appendix: CHAPTER 1 OVERVIEW Provides an overview of the features and functions of the MB89480/480L series. CHAPTER 2 HANDLING DEVICES Describes points to note when using the MB89480/480L series. CHAPTER 3 CPU Describes the functions of the MB89480/480L series CPU. CHAPTER 4 I/O PORTS Describes the function and operation of the MB89480/480L series I/O ports. CHAPTER 5 TIME-BASE TIMER Describes the function and operation of the MB89480/480L series time-base timer. CHAPTER 6 WATCHDOG TIMER Describes the functions and operation of the MB89480/480L series watchdog timer. CHAPTER 7 WATCH PRESCALER Describes the functions and operation of the MB89480/480L series watch prescaler. CHAPTER 8 8-BIT PWM TIMER Describes the functions and operation of the MB89480/480L series PWM timer. CHAPTER 9 PWC TIMER Describes the functions and operation of the MB90370 series PWC timer. CHAPTER 10 6-BIT PPG TIMER Describes the functions and operation of the MB89480/480L series 6-bit PPG. i

6 CHAPTER 11 8/16-BIT TIMER/COUNTER Describes the functions and operation of the MB89480/480L series 8/16-bit Timer/Counter. CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) Describes the function and operation of the MB89480/480L series external interrupt (edge). CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) Describes the function and operation of the MB89480/480L series external interrupt (level). CHAPTER 14 A/D CONVERTER Describes the functions and operation of the MB89480/480L series A/D converter. CHAPTER 15 UART/SIO Describes the function and operation of the MB89480/480L series UART/SIO. CHAPTER 16 BUZZER OUTPUT Describes the function and operation of the MB89480/480L series audible alarm output. CHAPTER 17 LCD CONTROLLER/DRIVER Describes the function and operation of the MB89480/480L series liquid crystal display (LCD) controller-driver circuit. APPENDIX The appendixes provide I/O maps, mask options, instruction summary, instruction list, instruction map and other information. ii

7 The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Copyright FUJITSU LIMITED All rights reserved iii

8 READING THIS MANUAL Page Layout Finding Information In this manual, an entire section is presented on a single page or spread whenever possible. The reader can thus view a section without having to flip pages. The content of each section is summarized immediately below the title. You can obtain a rough overview of this product by reading through these summaries. Also, higher level section headings are given in lower sections so that you can know to which section the text you are currently reading belongs. In addition to the standard table of contents and index, the following methods are available to find information in a particular section when required. Register index Information can be looked up in the register index by register name, by bit name, and by their respective abbreviations. Subheading index The sub-headings in each section (lines that start with ) are collected together in the subheading index. The subheading index provides a means of looking up information at a finer level of detail than the table of contents. Naming Conventions for Register Name and Pin Name Example for description of register name and bit name By writing 1 to the sleep bit (STBC: SLP) in the standby control register. Bit name Bit name abbreviation Register name abbreviation Disable the interrupt request output (TBTC: TBIE = 0) from the time-base timer. Setup data Bit name abbreviation Register name abbreviation Interrupt is accepted if the interrupt is enabled (CCR: I = 1). Register name abbreviation Bit name abbreviation Current status Register name Notations for shared pins Pin P14/SEG27/AN0 Many of the pins in the devices of this series are multi-function pins. (They can be switched between two or more functions under program control.) The multiple names of these pins (indicating their multiple functions) are separated by slant bars (/). iv

9 Facing Pages Organization and Notation Conventions Subheading Section summary Section title Higher level section Table title Figure title Chapter title Series title Reference Indicates an item or manual that should be referenced. Note Provides useful information for reference. Check Points requiring check and prohibited items. Always read checks. v

10 Development Tools and Other Resources Required for Development The following items are required for developing the MB89480/480L series. Contact FUJITSU sales representative for the required development tools and other resources. Manuals required for development Checklist F 2 MC-8L MB89480/480L Series Data Sheet (Provides electrical characteristics and various characteristic examples for the device.) F 2 MC-8L MB89600 Series Programming Manual (Describes the F 2 MC-8L family instruction set.) * F 2 MC-8L MB89600 Series C Compiler Manual (Only required when developing in C.) (Describes program development in C and how to run the compiler.) * F 2 MC-8L MB89600 Series Assembler Manual (Describes program development in assembly language.) * F 2 MC-8L MB89600 Series Support System Manual (Describes how to run the macro assembler, linker, and library manager.) * F 2 MC-8L MB89600 Series Software Simulator Manual (Only required when performing evaluation using the simulator.) (Describes how to operate the software simulator.) Manuals marked with * are provided with the products. In addition, manuals for products such as development tools are provided with the product. Software required for development Checklist C compiler (Only required when developing in C.) Assembler, linker, librarian Software simulator (Only required when performing evaluation using the simulator.) Emulator/debugger (Only required when performing evaluation using the MB2140A series.) The part number for each software package differs depending on the operating system. See the F 2 MC development tools catalog or product guide for details. Items required for evaluation using one-time PROM microcontrollers (when performing your own PROM programming) Checklist MB89P485 ROM programmer (a programmer able to program an MBM27C256A) See the data sheet for details of recommended programmers. vi

11 Development tool Checklist MB89PV480 (Piggyback/evaluation device) Evaluation tools (Main unit) (Pod) (Probe) MB2141A + MB MB Check with the supplier when using a third party development environment. Reference material F 2 MC development tools catalog Microcomputer product guide vii

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13 CONTENTS CHAPTER 1 OVERVIEW Features of MB89480/480L Series MB89480/480L Series Product Range Differences between Products Block Diagram of MB89480/480L Series Pin Assignment Package Dimensions Pin Functions CHAPTER 2 HANDLING DEVICES Notes on Handling Devices CHAPTER 3 CPU Memory Space Special Purpose Areas Storing 16-bit Data in Memory Dedicated Registers Condition Code Register (CCR) Register Bank Pointer (RP) General-purpose Registers Interrupts Interrupt Level Setting Registers (ILR1, ILR2, ILR3, ILR4) Interrupt Processing Multiple Interrupts Interrupt Processing Time Stack Operation during Interrupt Processing Stack Area for Interrupt Processing Resets Reset Flag Register (RSFR) External Reset Pin Reset Operation Pin States during Reset Clocks Clock Generator Clock Controller System Clock Control Register (SYCC) Clock Modes Oscillation Stabilization Wait Time Standby Modes (Low-Power Consumption) Operating States in Standby Modes Sleep Mode Stop Mode Watch Mode ix

14 3.7.5 Standby Control Register (STBC) State Transition Diagram Notes on Using Standby Modes Memory Access Mode CHAPTER 4 I/O PORTS Overview of I/O Ports Port Port 0 Registers (PDR0, DDR0, RDR0) Operation of Port Port Port 1 Registers (PDR1, DDR1) Operation of Port Port Port 2 Registers (PDR2, DDR2, PURC2) Operation of Port Port Port 3 Register (PDR3) Operation of Port Port Port 4 Registers (PDR4) Operation of Port Port Port 5 Register (PDR5) Operation of Port Program Example for I/O Ports CHAPTER 5 TIME-BASE TIMER Overview of Time-base Timer Block Diagram of Time-base Timer Time-base Timer Control Register (TBTC) Time-base Timer Interrupt Operation of Time-base Timer Notes on Using Time-base Timer Program Example for Time-base Timer CHAPTER 6 WATCHDOG TIMER Overview of Watchdog Timer Block Diagram of Watchdog Timer Watchdog Timer Control Register (WDTC) Operation of Watchdog Timer Notes on Using Watchdog Timer Program Example for Watchdog Timer CHAPTER 7 WATCH PRESCALER Overview of Watch Prescaler Block Diagram of Watch Prescaler x

15 7.3 Watch Prescaler Control Register (WPCR) Watch Prescaler Interrupt Operation of Watch Prescaler Notes on Using Watch Prescaler Program Example for Watch Prescaler CHAPTER 8 8-BIT PWM TIMER Overview of 8-bit PWM Timer Block Diagram of 8-bit PWM Timer Structure of 8-bit PWM Timer Registers of 8-bit PWM Timer PWM Control Register (CNTR) PWM Compare Register (COMR) bit PWM Timer Interrupts Operation of Interval Timer Function Operation of PWM Timer Function States in Each Mode during 8-bit PWM Timer Operation Notes on Using 8-bit PWM Timer Program Example for 8-bit PWM Timer CHAPTER 9 PWC TIMER Overview of Pulse Width Count Timer Block Diagram of Pulse Width Count Timer Structure of Pulse Width Count Timer Registers of Pulse Width Count Timer PWC Pulse Width Control Register 1 (PCR1) PWC Pulse Width Control Register 2 (PCR2) PWC Reload Buffer Register (PLBR) Pulse Width Count Timer Interrupts Operation of Interval Timer Function Operation of Pulse Width Measurement Function States in Each Mode during Pulse Width Count Timer Operation Notes on Using Pulse Width Count Timer Program Example for Timer Function of Pulse Width Count Timer Program Example for Pulse Width Measurement Function of Pulse Width Count Timer CHAPTER 10 6-BIT PPG TIMER Overview of 6-bit PPG Timer Block Diagram of 6-bit PPG Timer Pin of 6-bit PPG Timer Registers of 6-bit PPG Timer bit PPG Control Register 1 (PPGC1) bit PPG Control Register 2 (PPGC2) Operation of 6-bit PPG Timer Notes on Using 6-bit PPG Timer Program Example for 6-bit PPG Timer xi

16 CHAPTER 11 8/16-BIT TIMER/COUNTER Overview of 8/16-bit Timer/Counter Block Diagram of 8/16-bit Timer/Counter Pins of 8/16-bit Timer/Counter Registers of 8/16-bit Timer/Counter Timer 11/21 Control Register (T11CR/T21CR) Timer 12/22 Control Register (T12CR/T22CR) Timer 11/21 Data Register (T11DR/T21DR) Timer 12/22 Data Register (T12DR/T22DR) /16-bit Timer/Counter Interrupt Operation of Interval Timer Function Operation of Counter Function Operation of the Square Wave Output Initial Setting Function Operation of 8/16-bit Timer/Counter Stop and Restart States in Each Mode during 8/16-bit Timer/Counter Operation Notes on Using 8/16-bit Timer/Counter Program Examples for 8/16-bit Timer/Counter CHAPTER 12 EXTERNAL INTERRUPT 1 CIRCUIT (EDGE) Overview of the External Interrupt 1 Circuit Block Diagram of the External Interrupt 1 Circuit Pins of the External Interrupt 1 Circuit Registers of External Interrupt 1 Circuit External Interrupt Control Register 1 (EIC1) External Interrupt Control Register 2 (EIC2) External Interrupt 1 Circuit Interrupts Operation of the External Interrupt 1 Circuit Program Example for the External Interrupt 1 Circuit CHAPTER 13 EXTERNAL INTERRUPT 2 CIRCUIT (LEVEL) Overview of External Interrupt 2 Circuit (Level) Block Diagram of External Interrupt 2 Circuit Pins of External Interrupt 2 Circuit Registers of External Interrupt 2 Circuit External Interrupt 2 Control Register (EIE2) External Interrupt 2 Flag Register (EIF2) External Interrupt 2 Circuit Interrupt Operation of External Interrupt 2 Circuit Program Example for External Interrupt 2 Circuit CHAPTER 14 A/D CONVERTER Overview of A/D Converter Block Diagram of A/D Converter Pins of A/D Converter Registers of A/D Converter A/D Control Register 1 (ADC1) A/D Control Register 2 (ADC2) xii

17 A/D Data Registers (ADDL and ADDH) A/D Converter Interrupt Operation of A/D Converter Notes on Using A/D Converter Program Example for A/D Converter CHAPTER 15 UART/SIO Overview of UART/SIO Block Diagram of UART/SIO Pins of UART/SIO Registers of UART/SIO Serial Mode Control Register 1 (SMC1) Serial Mode Control Register 2 (SMC2) Serial Status and Data Register (SSD) Serial Input Data Register (SIDR) Serial Output Data Register (SODR) Serial Rate Control Register (SRC) UART/SIO Interrupts Operation of UART/SIO Operation of mode Operation of mode CHAPTER 16 BUZZER OUTPUT Overview of Buzzer Output Block Diagram of Buzzer Output Structure of Buzzer Output Buzzer Register (BUZR) Program Example for Buzzer Output CHAPTER 17 LCD CONTROLLER/DRIVER Overview of LCD Controller/Driver Block Diagram of LCD Controller/Driver LCD Controller/Driver Internal Dividing Resistors (Device without Voltage Booster) LCD Controller/Driver External Dividing Resistors (Device without Booster) LCD Controller/Driver Power Supply Voltage (Devices with Internal Voltage Booster) Structure of LCD Controller/Driver LCD Controller Register (LCR1) LCD Controller Register 2 (LCR2) Display RAM Operation of LCD Controller/Driver Output Waveforms during LCD controller/driver Operation (1/2 Duty Ratio) Output Waveforms during LCD Controller/Driver Operation (1/3 Duty Ratio) Output Waveforms during LCD Controller/Driver Operation (1/4 Duty Ratio) Program Example for LCD Controller/Driver xiii

18 APPENDIX APPENDIX A I/O MAP APPENDIX B Instructions B.1 Addressing B.2 Special Instructions B.3 F 2 MC-8L Instructions B.4 Instruction Map B.5 Bit Manipulation Instructions (SETB, CLRB) APPENDIX C Mask Options APPENDIX D Programming Specifications for one-time PROM and EPROM Microcontrollers D.1 Programming One-time PROM Microcontroller with serial programmer D.2 Programming One-time PROM Microcontroller parallel programmer D.3 Programming EPROM for Piggyback/Evaluation Device APPENDIX E MB89480/480L Series Pin States INDEX xiv

19 Main changes in this edition Page - Changed the terms (Port data direction register Port direction register) Changes (For details, refer to main body.) 8 Figure Block Diagram of MB89480/480L Series is changed. (Changed the arrow directions of X1, X1A) 49 Note is added. 60 Note is deleted Table Port Functions is changed. (The line of Port5 is added.) Figure PWC Pulse Width Control Register 2 (PCR2) Measured pulses are changed for the W2, W1, W0=110. (High level and rising to rising Both edges) Display RAM is changed. (Its contents are automatically read out to the segment outputs in sync with the timing of the selected common signal. Its contents are automatically read in sync with the timing of the selected common signal, and output from the segment outputs at the same time as writing the display RAM.) 385 Table B.3-4 Other Instructions is changed. (The instructions are added in operation.) 388 Note is added. The vertical lines marked in the left side of the page show the changes. xv

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21 CHAPTER 1 OVERVIEW This chapter describes the features and basic specifications of the MB89480/480L series. 1.1 Features of MB89480/480L Series 1.2 MB89480/480L Series Product Range 1.3 Differences between Products 1.4 Block Diagram of MB89480/480L Series 1.5 Pin Assignment 1.6 Package Dimensions 1.7 Pin Functions 1

22 CHAPTER 1 OVERVIEW 1.1 Features of MB89480/480L Series The MB89480/480L series has been developed as a general-purpose version of the F 2 MC-8L family consisting of 8-bit proprietary, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as 21-bit time-base timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, 6-bit PPG, LCD controller/driver, external interrupt 1 (edge), external interrupt 2 (level), 10-bit A/D converter, UART/SIO, buzzer, watchdog timer reset. The MB89480/480L series is designed suitable for LCD remote controller as well as in a wide range of applications for consumer product. Features of MB89480/480L Series Supports high speed operation Minimum instruction execution time: 0.32µs (source oscillation at 12.5MHz) Package used QFP package and SH-DIP package for MB89P485/L, MB89485/L MDIP package and MQFP package for MB89PV480 F 2 MC-8L CPU core Instructions set optimized for controller applications - Multiplication and division instructions - 16-bit operations - Bit-test branch instructions - Bit manipulation instructions, etc. Six timers sub-systems - PWC timer (also usable as an interval timer) - PWM timer - 8/16-bit timer/counter 2 ch - 21-bit time-base timer - Watch prescaler Programmable Pulse Generator (PPG) - 6-bit PPG with program -selectable pulse width and period External interrupts - Edge detection (Selectable edge) : 4 channels - "L" level interrupt (Wake-up function): 8 channels A/D converter (4 channels) - 10-bit successive approximation type UART / SIO - Synchronous/asynchronous data transfer capable 2

23 LCD controller/driver - max. 31 segments output 4 commons - Booster for LCD driving (selected by mask option) Buzzer - 7 frequency types are selectable by software Low-power consumption modes - Stop mode (Oscillation stops to minimize the current dissipation.) - Sleep mode (The CPU stops to reduce the current dissipation to approx. 1/3 of normal.) - Watch mode (Operation except the watch prescaler stops to reduce the power dissipation to an extremely low level.) - Sub clock mode Watchdog timer reset I/O ports - Max 42 channels 3

24 CHAPTER 1 OVERVIEW 1.2 MB89480/480L Series Product Range The MB89480/480L series contains 3 different models. Table lists the product range and Table lists the common specifications. MB89480/480L Series Product Range Table MB89480/480L Series Product Range Parameter Model MB89485L MB89485 MB89P485L MB89P485 MB89PV480 Class Mass Production Products (mask ROM product) OTP Piggy-back ROM capacity 16K 8 bits (internal ROM) 16K 8 bits (internal PROM) 32K 8 bits (external ROM)* RAM capacity bits 1K 8 bits Low-power consumption (standby modes) Process Operating voltage Sleep mode, stop mode, watch mode, sub clock mode CMOS 2.2V to 3.6V 2.2V to 5.5V 2.7V to 3.6V 3.5V to 5.5V 2.7V to 5.5V *: Use MBM27C256A as the external ROM. 4

25 Table Common Specifications for the MB89480/480L Series (1 / 2) Parameter CPU functions Ports Number of instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Minimum interrupt processing time I/O ports (CMOS) N-channel open drain I/O ports Output ports (N-channel open drain) Input port Total Specification : 136 instructions : 8-bit : 1 to 3 bytes : 1, 8, or 16-bit : 0.32µs/12.5 MHz : 2.88µs/12.5 MHz : 11 pins : 28 pins : 2 pins : 1 pins : 42 pins Time-base timer Watchdog timer 21-bit Interrupt period (0.66ms, 2.6 ms, 21.0 ms, ms) at 12.5 MHz Reset period (167.8 ms to ms) at 12.5 MHz Peripheral functions Pulse width count timer PWM timer 6-bit programmable pulse generator 1 channel 8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 t inst, external) 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 t inst, external) 8-bit pulse width measurement operation (supports continuous measurement, H width, L width, rising edge to rising edge, falling edge to falling edge measurement and both edge measurement) 8-bit reload timer operation (supports square wave output, operating clock period: 1, 8, 16, 64 t inst ) 8-bit resolution PWM operation Can generate square wave with programmable period. 8/16-bit timer/ counter 11, 12 8/16-bit timer/ counter 21, 22 External Interrupt Can be operated either as a 2-channel 8-bit timer/counter (Timer 11 and Timer 12, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 11 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable Can be operated either as a 2-channel 8-bit timer/counter (Timer 21 and Timer 22, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 21 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 4 independent channels (selectable edge, interrupt vector, request flag) 8 channels ("L" level interrupt) 5

26 CHAPTER 1 OVERVIEW Table Common Specifications for the MB89480/480L Series (2 / 2) Parameter A/D converter Specification 10-bit resolution 4 channels A/D conversion function (conversion time: 60 t inst ) Supports repeated activation by internal clock. Peripheral functions LCD controller/ driver UART/SIO Common output Segment output Bias power supply pins LCD display RAM size Internal dividing resistor ladder/ booster Synchronous/asynchronous data transfer capable (7 and 8 bits with parity bit; 8 and 9 bits without parity bit) : 4 (max.) : 31 (max.) (Select resistor ladder) /26 (max.) (Select booster) : 4 : 31 x 4 bits : selected by mask option Buzzer output 7 frequency types are selectable by software Low-power consumption modes Process Sleep mode, stop mode, watch mode, sub clock mode CMOS *: t inst is instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock. See "3.6.3 System Clock Control Register (SYCC)". 6

27 1.3 Differences between Products This section describes the differences between the 5 products in the MB89480/480L series and lists points to note in products selection. Differences between Products and Points to Note for Product Selection Table Package and corresponding products Package Classification MB89485/485L MB89P485/485L MB89PV480 DIP-64P-M01 O O X FPT-64P-M09 O O X MDP-64C-P02 X X O MQP-64P-P01 X X O O : Available X : Not Available For more information about each package, see section "1.6 Package Dimensions". Memory space Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: - The stack area, etc., is set at the upper limit of the RAM. Current dissipation - For the MB89PV480, add the current consumed by the EPROM mounted in the piggyback socket. - When operating at low speed, the current consumed by the one-time PROM products is greater than that for the mask ROM product. However, the current dissipation are roughly the same in sleep or stop mode. Reference: See " Electrical characteristics" in the data sheet for details. 7

28 CHAPTER 1 OVERVIEW 1.4 Block Diagram of MB89480/480L Series The block diagram of MB89480/480L series is shown in Figure Block Diagram of MB89480/480L Series Figure Block Diagram of MB89480/480L Series X0 X1 Main clock oscillator CMOS I/O port Clock control Buzzer output P07/INT27/BUZ X0A X1A RST Sub-clock oscillator Reset circuit (Watchdog timer) 21-bit time-base timer 6-bit PPG 8-bit PWC timer External interrupt 2 (level) 8 Port 0 P06/INT26/PPG P05/INT25/PWC P04/INT24 * 1 P03/INT23 * 1 P02/INT22 to P00/INT20 Watch prescaler AVcc AVss P20/PWM P21/SCK P22/SO P23/SI P24/C1/TO2 * 1 P25/C0/EC2 * 1 P26/V1/TO1 P27/V2/EC1 Port 2 * 4 CMOS I/O port * 4 8-bit PWM timer UART/SIO 8/16-bit timer/counter 21,22 8/16-bit timer/counter 11,12 Internal data bus 10-bit A/D converter N-ch open-drain I/O port External interrupt 1 (edge) Port P14/SEG27/AN0 * 1 to P17/SEG30/AN3 * 1 P10/SEG23/INT10 to P13/SEG26/INT13 P30/COM2 P31/COM3 Port 3 N-ch open-drain output port RAM (512 bytes/1 Kbyte) F 2 MC-8L CPU ROM (16 Kbytes/32 Kbyte) Other pins Vcc, Vss, MODE, C * 2 2 Booster 2 2 LCD controller/driver 32 4-bit display RAM (16 bytes) Port 4 and Port 5 * 4 N-ch open-drain I/O port 7 2 SEG1 to SEG7 COM0 COM1 V3 V0/SEG0 * 3 to 16 3 P56/SEG22 to P54/SEG20 *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P14/SEG27/AN0 to P17/SEG30/AN3 will be disabled. *2: For product other than MB89P485, C pin is N.C. pin. *3: If booster is selected, it serves as V0. If booster is not selected, it serves as SEG0. *4: P20 to P23 are CMOS I/O ports. P24 to P27 are N-ch open-drain I/O ports. P57 is input-only port P57 P53/SEG19 to P50/SEG16 P47/SEG15 to P44/SEG12 P43/SEG11 to P40/SEG8 8

29 1.5 Pin Assignment Figure to Figure show the pin assignment for the MB89480/480L series. DIP-64P-M01 Pin Assignment Figure DIP-64P-M01 Pin Assignment (TOP VIEW) COM0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57 P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A * 2 C VSS A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS VCC A14 A13 A8 A9 A11 OE/V pp A10 CE O8 O7 O6 O5 O Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 P26/V1/TO1 V0/SEG0 P25/C0/EC2 * 1 P24/C1/TO2 * 1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 * 1 P04/INT24 * 1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P17/SEG30/AN3 * 1 P16/SEG29/AN2 * 1 P15/SEG28/AN1 * 1 P14/SEG27/AN0 * 1 RST MODE X1 X0 (DIP-64P-M01) (MDP-64C-P02) *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 to P14/SEG27/AN0 will be disabled. *2: For product other than MB89P485, pin 31 is N.C. pin. *3: Pin assignment on package top. Pin no. Pin symbol Pin no. Pin symbol Pin no. Pin symbol Pin no. Pin symbol 65 A15 73 A1 81 O6 89 A8 66 A12 74 A0 82 O7 90 A13 67 A7 75 O1 83 O8 91 A14 68 A6 76 O2 84 CE 92 Vcc 69 A5 77 O3 85 A10 70 A4 78 VSS 86 OE 71 A3 79 O4 87 A11 72 A2 80 O5 88 A9 N.C. : As connected internally, do not use. 9

30 CHAPTER 1 OVERVIEW FPT-64P-M09 Pin Assignment Figure FPT-64P-M09 Pin Assignment (TOP VIEW) P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 P26/V1/TO1 V0/SEG P25/C0/EC2 * 1 P24/C1/TO2 * 1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 * 1 P04/INT24 * 1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A * 2 C Vss X0 X1 MODE RST * 1 P14/SEG27/AN0 * 1 P15/SEG28/AN1 * 1 P16/SEG29/AN2 * 1 P17/SEG30/AN3 (FPT-64P-M09) *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 to P14/SEG27/AN0 will be disabled. *2: For product other than MB89P485, pin 23 is N.C. pin. 10

31 MQP-64C-P01 Pin Assignment Figure MQP-64C-P01 Pin Assignment (TOP VIEW) SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 SEG P26/V1/TO1 P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57 P10/SEG23/INT10 P11/SEG24/INT P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A *2 C Vss X0 X1 MODE RST *1 P14/SEG27/AN0 *1 P15/SEG28/AN1 *1 P16/SEG29/AN V0/SEG0 P25/C0/EC2 * 1 P24/C1/TO2 * 1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 * 1 P04/INT24 * 1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P17/SEG30/AN3 * 1 (MQP-64C-P01) *1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 to P14/SEG27/AN0 will be disabled. *2: Pin 24 is N.C. pin. Pin assignment on package top Pin No. Pin Symbol Pin No. Pin Symbol Pin No. Pin Symbol Pin No. Pin Symbol 65 N.C. 73 A2 81 N.C. 89 OE 66 V pp 74 A1 82 O4 90 N.C. 67 A12 75 A0 83 O5 91 A11 68 A7 76 N.C. 84 O6 92 A9 69 A6 77 O1 85 O7 93 A8 70 A5 78 O2 86 O8 94 A13 71 A4 79 O3 87 CE 95 A14 72 A3 80 VSS 88 A10 96 VCC N.C.: As connected internally, do not use. 11

32 CHAPTER 1 OVERVIEW 1.6 Package Dimensions Three different packages are available for the MB89480/480L series. Figure to Figure show the package dimensions. DIP-64P-M01 Package Dimensions Figure DIP-64P-M01 Package Dimensions 64-pin plastic SH-DIP Lead pitch 1.778mm(70mil) Package width package length Sealing method mm Plastic mold Mounting height 5.65 mm MAX (DIP-64P-M01) 64-pin plastic SH-DIP (DIP-64P-M01) Note: Pins width and pins thickness include plating thickness INDEX-1 INDEX ±0.25 (.669±.010) (.0700) 0.47±0.10 (.019±.004) (.010) M 0.27±0.10 (.011±.004) (.750) 0~15 C 2001 FUJITSU LIMITED D64001S-c-4-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. 12

33 FPT-64P-M09 Package Dimensions Figure FPT-64P-M09 Package Dimensions 64-pin plastic LQFP Lead pitch 0.65 mm Package width package length Lead shape mm Gullwing Sealing method Plastic mold Mounting height Code (Reference) 1.70 mm MAX P-LQFP (FPT-64P-M09) 64-pin plastic LQFP (FPT-64P-M09) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder ±0.20(.551±.008)SQ 48 * 12.00±0.10(.472±.004)SQ ±0.055 (.0057±.0022) (.004) Details of "A" part (Mounting height) INDEX 0~8 0.25(.010) (.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) C 2003 FUJITSU LIMITED F64018S-c-3-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. 13

34 CHAPTER 1 OVERVIEW MDP-64C-P02 Package Dimensions Figure MDP-64C-P02 Package Dimensions 64-pin ceramic MDIP Lead pitch 1.778mm (70mil) Row spacing Motherboard material Mounted packing material 15.24mm (750mm) Ceramic Plastic mold (MDP-64C-P02) 64-pin ceramic MDIP (MDP-64C-P02) 56.90±0.64 (2.240±.025) 0 ~ (.600) TYP 18.75±0.30 (.738±.012) 19.05±0.30 (.750±.012) INDEX AREA 2.54±0.25 (.100±.010) 33.02(1.300)REF 0.25±0.05 (.010±.002) 10.16(.400)MAX 1.27±0.25 (.050±.010) 1.778±0.25 (.070±.010) (2.170)REF 0.90±0.13 (.035±.005) 3.43±0.38 (.135±.015) C 1994 FUJITSU LIMITED M64002SC-1-4 Dimensions in mm (inches). Note: The values in parentheses are reference values. 14

35 MQP-64C-P01 Package Dimensions Figure MQP-64C-P01 Package Dimensions 64-pin ceramic MQFP Lead pitch 1.00 mm Lead shape Motherboard material Mounted package material Straight Ceramic Plastic (MQP-64C-P01) 64-pin ceramic MQFP (MQP-64C-P01) 18.70(.736)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) (.472)TYP 1.00±0.25 (.039±.010) 1.00±0.25 (.039±.010) 1.27±0.13 (.050±.005) 24.70(.972) TYP 22.30±0.33 (.878±.013) 0.30(.012) TYP 10.16(.400) TYP 12.02(.473) TYP 14.22(.560) TYP 18.12±0.20 (.713±.008) 18.00(.709) TYP 1.27±0.13 (.050±.005) 0.30(.012)TYP 7.62(.300)TYP 0.40±0.10 (.016±.004) ± (.016±.004) (.373)TYP 11.68(.460)TYP 0.50(.020)TYP 10.82(.426) 0.15±0.05 MAX (.006±.002) C 1994 FUJITSU LIMITED M64004SC-1-3 Dimensions in mm (inches). Note: The values in parentheses are reference values. 15

36 CHAPTER 1 OVERVIEW 1.7 Pin Functions Table and Table list the MB89480/480L series I/O pins and their functions. Table lists the I/O circuit types. The letter in the I/O Circuit Type column of Table refers to the letter in the Circuit Class column of Table Pin Functions Table Pin Functions (1 / 3) SH- DIP*1 MDIP*4 Pin Number MQFP* 2 QFP*3 Pin Name X X X0A X1A I/O Circuit Type MODE B RST C 50 to to to 40 P00/INT20 to P02/INT P03/INT23 D P04/INT24 D P05/INT25/ PWC P06/INT26/ PPG P07/INT27/ BUZ A A D D D D Function Connection pins for a crystal or other oscillator. An external clock can be connected to X0. In this case, leave X1 open. Connection pins for a crystal or other oscillator of sub clock. An external clock can be connected to X0A (for low-speed: kHz). In this case, leave X1A open. Input pins for setting the memory access mode. Connect directly to V SS. Reset I/O pin. The pin is a N-ch open-drain type with pull-up resistor and a hysteresis input. The pin outputs a "L" level when an internal reset request is present. Inputting an "L" level initializes internal circuits. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/ counter 21, 22 input when booster is selected. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/counter 21, 22 output when booster is selected. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and PWC input. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and 6-bit PPG output. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input and buzzer output. 16

37 Table Pin Functions (2 / 3) SH- DIP*1 MDIP*4 25 to to to to to to 32 P10/SEG23/ INT10 to P13/SEG26/ INT13 P14/SEG27/ AN0 to P17/SEG30/ AN3 F / K G / K P20/PWM E P21/SCK E P22/SO E P23/SI D P24/C1/TO2 H P25/C0/EC2 F P26/V1/TO1 H P27/V2/EC1 F P30/COM2 I / K P31/COM3 I / K 9 to 16 2 to 9 1 to 8 17 to to 16 9 to 15 P40/SEG8 to P47/SEG15 P50/SEG16 to P56/ SEG22 H / K H / K General-purpose N-ch open-drain output port. A hysteresis input. The pin is shared with external interrupt 1 input and LCD segment output. General-purpose N-ch open-drain output port. An analog input. The pin is shared with A/D converter input and LCD segment output. LCD segment output will be disabled when booster is selected. General-purpose CMOS I/O port. The pin is shared with PWM output. General-purpose CMOS I/O port. The pin is shared with UART/SIO clock I/O. General-purpose CMOS I/O port. The pin is shared with UART/SIO data output. General-purpose CMOS I/O port. The pin is shared with UART/SIO data input. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 21,22 output (It is redirected to P04/INT24 when booster is selected), and operates as a capacitor connecting pin when booster is selected. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with 8/16-bit timer/counter 21,22 input (It is redirected to P03/ INT23 when booster is selected), and operates as a capacitor connecting pin when booster is selected. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer 11,12 output, and LCD power driving pin. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with 8/16-bit timer 11,12 input, and LCD power driving pin. General-purpose N-ch open-drain output port. The pin is shared with the LCD common output General-purpose N-ch open-drain output port. The pin is shared with the LCD common output General-purpose N-ch open-drain I/O port. The pin is shared with LCD segment output. General-purpose N-ch open-drain I/O port. The pin is shared with LCD segment output P57 J General-purpose CMOS input port 2 to 8 Pin Number MQFP* 2 59 to 64, 1 QFP*3 58 to 64 1, 63 58, 56 57, 55 Pin Name SEG1 to SEG7 COM0, COM1 I/O Circuit Type K K LCD segment output only pins LCD common output only pins Function 17

38 CHAPTER 1 OVERVIEW Table Pin Functions (3 / 3) SH- DIP*1 MDIP*4 Pin Number MQFP* 2 QFP*3 Pin Name I/O Circuit Type V3 LCD driving power supply pin V0/SEG0 / K LCD driving power supply pin when booster is selected. LCD segment output only pin when booster is not selected C When MB89P485 is used, connect this pin to an external 0.1µF capacitor to ground. When MB89485/L, MB89P485L or MB89PV480 is used, this pin will become a N.C. pin VCC Power supply pin (+3V or +5V) VSS Power supply pin (GND) AVCC A/D converter power supply pin AVSS A/D converter power supply pin. Use at the same voltage level as V SS. Function *1: DIP-64P-M01 *2: MQP-64C-P01 *3: FPT-64P-M09 *4: MDP-64C-P02 18

39 Table Pin Functions for the External EPROM Socket (MB89PV480 only) MDIP* Pin Number MQFP* Pin Name I/O Function A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O8 O7 O6 O5 O4 O3 O2 O1 O I Address output pins Data input pins N.C. Internally connected pins. Always leave open Vpp O "H" level output pin VSS O Power supply pin (GND) CE O Chip enable pin for the EPROM. Outputs "H" in standby mode OE O Output enable pin for the EPROM. Always outputs "L" VCC O Power supply pin for the EPROM *1: MDP-64C-P02 *2: MQP-64C-P01 19

40 CHAPTER 1 OVERVIEW Table I/O Circuit Types (1 / 2) Circuit Class Circuit Remarks X1 (X1A) N-ch P-ch A X0 (X0A) P-ch N-ch Main and sub clock circuit oscillation feedback resistor High-speed side = approx. 500kΩ Low-speed side = approx. 5MΩ Stop mode control signal B Hysteresis input Pull-down resistor Approx. 50kΩ. (Available in MB89485/485L/ PV480 only) R C P-ch N-ch Pull-up resistor (P-ch) Approx. 50 kω. Hysteresis input R Pull-up resistor register D P-ch N-ch Port Resources CMOS output CMOS input Hysteresis input Selectable pull-up resistor Approx. 50 kω. R Pull-up Resistor register E P-ch N-ch CMOS output CMOS input Selectable pull-up resistor Approx. 50 kω. Port 20

41 Table I/O Circuit Types (2 / 2) Circuit Class Circuit Remarks F N-ch Port N-ch open-drain output CMOS input Hysteresis input Resources G N-ch Port N-ch open-drain output CMOS input Analog input Analog input H N-ch N-ch open-drain output CMOS input Port I N-ch N-ch open-drain output J Port CMOS input K P-ch N-ch P-ch N-ch LCD segment output 21

42 CHAPTER 1 OVERVIEW 22

43 CHAPTER 2 HANDLING DEVICES This chapter describes points to note when using the general-purpose single-chip microcontroller. 2.1 Notes on Handling Devices 23

44 CHAPTER 2 HANDLING DEVICES 2.1 Notes on Handling Devices This section lists points to note regarding the power supply voltage, pins, and other device handling aspects. Notes on Handling Devices Take great care not to exceed the maximum rated voltage (prevent latch-up). Latch-up may occur on CMOS IC if voltage higher than V CC or lower than V SS is applied to input and output pins other than medium- to high-withstand voltage pins, or if voltage higher than the ratings is applied between V CC and V SS. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the maximum ratings. Also, take care to prevent the analog power supply (AV CC ) and analog input from exceeding the digital power supply (V CC ) when the analog system power supply is turned on and off. Stabilizing supply voltage is important. A rapid fluctuation of V CC power supply voltage could cause malfunctions, even if it occurs within the operation assurance range of the voltage. The voltage must therefore be stabilized. As stabilization guidelines, it is recommended to stabilize the voltage so that V CC ripple fluctuations (peak to peak value) will be less than 10% of the standard V CC value at the commercial frequency (50Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. Treatment of unused input pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. Treatment of N.C. pins Be sure to leave (internally connected) N.C. pins open. Treatment of power supply pins on microcontroller with A/D converter Connect to be AV CC = V CC and AV SS = V SS even if the A/D converter is not in use. Precautions when using an external clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset and wake-up from stop mode. MB89480/480L series C pin handling Table lists the connection of C pin: Table Connection of C pin C pin connection MB89485/485L/P485L/PV480 MB89P485 N.C. pin This pin must be connected to an external 0.1µF capacitor to ground. 24

45 CHAPTER 3 CPU This chapter describes the functions and operation of the CPU in MB89480/480L series. 3.1 Memory Space 3.2 Dedicated Registers 3.3 General-purpose Registers 3.4 Interrupts 3.5 Resets 3.6 Clocks 3.7 Standby Modes (Low-Power Consumption) 3.8 Memory Access Mode 25

46 CHAPTER 3 CPU 3.1 Memory Space The microcontrollers of the MB89480/480L series offer a memory space of 64 Kbytes. The memory space contains the I/O area, RAM area, ROM area, and external area. The memory space contains areas used for special purposes such as the general-purpose registers and vector table. Structure of Memory Space I/O area (addresses: 0000 H to 007F H ) - Control registers and data registers for the internal peripheral functions are allocated in this area. - As the I/O area is allocated within the memory space, I/O can be accessed in the same way as memory. High-speed access using direct addressing is available. RAM area - Internal static RAM is provided as an internal data area. - The internal RAM size differs between products. - Addresses between 80 H and FF H support high-speed access using direct addressing. - Addresses between 100 H and 1FF H can be used as the general-purpose register area. - The contents of RAM becomes undefined after a reset. ROM area - Internal ROM is provided as an internal program area. - The internal ROM size differs between products. Set the memory access mode to internal ROM mode. - Addresses between FFC0 H and FFFF H are used for the vector table, etc. 26