DATA SHEET. TDA8927 Power stage 2 80 W class-d audio amplifier INTEGRATED CIRCUITS. Preliminary specification Supersedes data of 2001 Dec 11

Transcription

1 INTEGRATED CIRCUITS DATA SHEET Power stage 8 W class-d audio Supersedes data of Dec Oct

2 CONTENTS FEATURES APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8. Power stage 8. Protection 8.. Overtemperature 8.. Short-circuit across the loudspeaker terminals 8.3 BTL operation 9 LIMITING VALUES THERMAL CHARACTERISTICS QUALITY SPECIFICATION DC CHARACTERISTICS 3 AC CHARACTERISTICS 4 SWITCHING CHARACTERISTICS 4. Duty factor 5 TEST AND APPLICATION INFORMATION 5. BTL application 5. Package ground connection 5.3 Output power 5.4 Reference design 5.5 Reference design bill of materials 5.6 Curves measured in reference design 6 PACKAGE OUTLINES 7 SOLDERING 7. Introduction to soldering through-hole mount packages 7. Soldering by dipping or by solder wave 7.3 Manual soldering 7.4 Suitability of through-hole mount IC packages for dipping and wave soldering methods 8 DATA SHEET STATUS 9 DEFINITIONS DISCLAIMERS Oct

3 FEATURES High efficiency (>94%) Operating voltage from ±5 to ±3 V Very low quiescent current High output power Short-circuit proof across the load, only in combination with controller TDA899T Diagnostic output Usable as a stereo Single-Ended (SE) or as a mono in Bridge-Tied Load (BTL) Electrostatic discharge protection (pin to pin) Thermally protected, only in combination with controller TDA899T. 3 GENERAL DESCRIPTION The is the switching power stage of a two-chip set for a high efficiency class-d audio power system. The system is split into two chips: J; digital power stage in a DBS7P package TDA899T; analog controller chip in a SO4 package. With this chip set a compact 8 W audio system can be built, operating with high efficiency and very low dissipation. No heatsink is required, or depending on supply voltage and load, a very small one. The system operates over a wide supply voltage range from ±5 up to ±3 V and consumes a very low quiescent current. APPLICATIONS Television sets Home-sound sets Multimedia systems All mains fed audio systems Car audio (boosters). 4 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT General; V P = ±5 V V P supply voltage ±5 ±5 ±3 V I q(tot) total quiescent current no load connected ma η efficiency P o =3W 94 % Stereo single-ended configuration P o output power R L =4Ω; THD = %; V P = ±5 V 6 65 W R L =4Ω; THD = %; V P = ±7 V 74 8 W Mono bridge-tied load configuration P o output power R L =4Ω; THD = %; V P = ±7 V 9 W R L =8Ω; THD = %; V P = ±5 V 5 W 5 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION J DBS7P plastic DIL-bent-SIL power package; 7 leads (lead length mm) SOT43- Oct 3

4 6 BLOCK DIAGRAM handbook, full pagewidth V DD V DD J BOOT EN SW REL STAB DIAG POWERUP CONTROL AND HANDSHAKE temp current DRIVER HIGH DRIVER LOW TEMPERATURE SENSOR AND CURRENT PROTECTION 7 V SS V DD OUT BOOT EN SW REL CONTROL AND HANDSHAKE DRIVER HIGH DRIVER LOW OUT 8 V SS V SS MGW38 Fig. Block diagram. Oct 4

5 7 PINNING SYMBOL PIN DESCRIPTION SW digital switch input; channel REL digital control output; channel DIAG 3 digital open-drain output for overtemperature and overcurrent report EN 4 digital enable input; channel V DD 5 positive power supply; channel BOOT 6 bootstrap capacitor; channel OUT 7 PWM output; channel V SS 8 negative power supply; channel STAB 9 decoupling internal stabilizer for logic supply V SS negative power supply; channel OUT PWM output; channel BOOT bootstrap capacitor; channel V DD 3 positive power supply; channel EN 4 digital enable input; channel POWERUP 5 enable input for switching on internal reference sources REL 6 digital control output; channel SW 7 digital switch input; channel SW REL DIAG EN V DD BOOT OUT V SS STAB V SS OUT BOOT V DD EN POWERUP REL SW J MGW4 Fig. Pin configuration. Oct 5

6 8 FUNCTIONAL DESCRIPTION The combination of the and the TDA899T produces a two-channel audio power system using the class-d technology (see Fig.3). In the TDA899T controller the analog audio input signal is converted into a digital Pulse Width Modulation (PWM) signal. The power stage is used for driving the low-pass filter and the loudspeaker load. It performs a level shift from the low-power digital PWM signal, at logic levels, to a high-power PWM signal that switches between the main supply lines. A nd-order low-pass filter converts the PWM signal into an analog audio signal across the loudspeaker. For a description of the controller, see data sheet TDA899T, Controller class-d audio. 8. Power stage The power stage contains the high-power DMOS switches, the drivers, timing and handshaking between the power switches and some control logic. For protection, a temperature sensor and a maximum current detector are built-in on the chip. For interfacing with the controller chip the following connections are used: Switch (pins SW and SW): digital inputs; switching from V SS to V SS + V and driving the power DMOS switches Release (pins REL and REL): digital outputs to indicate switching from V SS to V SS + V, follow pins SW and SW with a small delay Enable (pins EN and EN): digital inputs; at a level of V SS the power DMOS switches are open and the PWM outputs are floating; at a level of V SS + V the power stage is operational and controlled by the switch pin if pin POWERUP is at V SS +V Power-up (pin POWERUP): must be connected to a continuous supply voltage of at least V SS + 5 V with respect to V SS Diagnostics (pin DIAG): digital open-drain output; pulled to V SS if the temperature or maximum current is exceeded. 8. Protection Temperature and short-circuit protection sensors are included in the power stage. The protection circuits are operational only in combination with the TDA899T. In the event that the maximum current or maximum temperature is exceeded the diagnostic output is activated. The controller has to take appropriate measures by shutting down the system. 8.. OVERTEMPERATURE If the junction temperature (T j ) exceeds 5 C, then pin DIAG becomes LOW. The diagnostic pin is released if the temperature is dropped to approximately 3 C, so there is a hysteresis of approximately C. 8.. SHORT-CIRCUIT ACROSS THE LOUDSPEAKER TERMINALS When the loudspeaker terminals are short-circuited this will be detected by the current protection. If the output current exceeds the maximum output current of 7.5 A, then pin DIAG becomes LOW. The controller should shut down the system to prevent damage. Using the TDA899T the system is shut down within µs, and after ms it will attempt to restart the system again. During this time the dissipation is very low, therefore the average dissipation during a short-circuit is practically zero. Oct 6

7 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be... Oct 7 V SSA V i() V MODE V i IN IN+ SGND R OSC OSC MODE SGND IN+ IN V SSA SGND SGND V SS V SS(sub) mute mute V DDA 3 INPUT STAGE MODE INPUT STAGE V SSA V DD TDA899T OSCILLATOR V DDA R fb PWM MODULATOR PWM MODULATOR V DD R fb STABI MANAGER 8 3 PWM REL 4 SW EN 9 STAB DIAGCUR 5 DIAGTMP V SSD EN SW REL PWM handbook, full pagewidth REL STAB DIAG POWERUP 5 EN SW REL SW EN J CONTROL AND HANDSHAKE DRIVER HIGH DRIVER LOW TEMPERATURE SENSOR AND CURRENT PROTECTION CONTROL AND HANDSHAKE DRIVER HIGH DRIVER LOW V DDD V DD V DD 3 5 V SS V SSD 6 7 V SS V DD 8 V SS OUT BOOT V DDA BOOT Fig.3 Typical application schematic of the class-d system using TDA899T and the J. OUT V SSA +5 V 5 V MGU388 SGND ( V) Philips Semiconductors

8 8.3 BTL operation BTL operation can be achieved by driving the audio input channels of the controller in the opposite phase and by connecting the loudspeaker with a BTL output filter between the two PWM output pins of the power stage (see Fig.4). In this way the system operates as a mono BTL and with the same loudspeaker impedance a four times higher output power can be obtained. For more information see Chapter 5. handbook, full pagewidth V DD V DD J BOOT EN SW REL STAB DIAG POWERUP CONTROL AND HANDSHAKE temp current DRIVER HIGH DRIVER LOW TEMPERATURE SENSOR AND CURRENT PROTECTION 7 V SS V DD OUT SGND ( V) BOOT EN SW REL CONTROL AND HANDSHAKE DRIVER HIGH DRIVER LOW OUT 8 MGU386 V SS V SS Fig.4 Mono BTL application. Oct 8

9 9 LIMITING VALUES In accordance with the Absolute Maximum Rate System (IEC 634). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V P supply voltage ±3 V V P(sc) supply voltage for ±3 V short-circuits across the load I ORM repetitive peak current in 7.5 A output pins T stg storage temperature C T amb ambient temperature C T vj virtual junction temperature 5 C V es(hbm) electrostatic discharge note voltage (HBM) all pins with respect to V DD (class a) 5 +5 V all pins with respect to V SS (class a) 5 +5 V all pins with respect to each other (class a) 5 +5 V V es(mm) electrostatic discharge note voltage (MM) all pins with respect to V DD (class B) 5 +5 V all pins with respect to V SS (class B) 5 +5 V all pins with respect to each other (class B) 5 +5 V Notes. Human Body Model (HBM); R s = 5 Ω; C = pf.. Machine Model (MM); R s =Ω; C = pf; L =.75 µh. THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT R th(j-a) thermal resistance from junction to ambient in free air 4 K/W R th(j-c) thermal resistance from junction to case in free air. K/W QUALITY SPECIFICATION In accordance with SNW-FQ6-part D if this type is used as an audio (except for ESD, see also Chapter 9). Oct 9

10 DC CHARACTERISTICS V P = ±5 V; T amb =5 C; measured in test diagram of Fig.6; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply V P supply voltage note ±5 ±5 ±3 V I q(tot) total quiescent current no load connected ma outputs floating 5 ma Internal stabilizer logic supply (pin STAB) V O(STAB) stabilizer output voltage 3 5 V Switch inputs (pins SW and SW) V IH HIGH-level input voltage referenced to V SS V STAB V V IL LOW-level input voltage referenced to V SS V Control outputs (pins REL and REL) V OH HIGH-level output voltage referenced to V SS V STAB V V OL LOW-level output voltage referenced to V SS V Diagnostic output (pin DIAG, open-drain) V OL LOW-level output voltage I DIAG = ma; note. V I LO output leakage current no error condition 5 µa Enable inputs (pins EN and EN) V IH HIGH-level input voltage referenced to V SS 9 V STAB V V IL LOW-level input voltage referenced to V SS 5 V V EN(hys) hysteresis voltage 4 V I I(EN) input current 3 µa Switching-on input (pin POWERUP) V POWERUP operating voltage referenced to V SS 5 V I I(POWERUP) input current V POWERUP =V 7 µa Temperature protection T diag temperature activating diagnostic V DIAG =V DIAG(LOW) 5 C T hys hysteresis on temperature diagnostic V DIAG =V DIAG(LOW) C Notes. The circuit is DC adjusted at V P = ±5 to ±3 V.. Temperature sensor or maximum current sensor activated. Oct

11 3 AC CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Single-ended application; note P o output power R L =4Ω; V P = ±5 V THD =.5% 5 55 W THD = % 6 65 W R L =4Ω; V P = ±7 V THD =.5% 6 65 W THD = % 74 8 W THD total harmonic distortion P o = W; note 3 f i = khz..5 % f i = khz. % G v(cl) closed-loop voltage gain db η efficiency P o = 3 W; f i = khz; note 4 94 % Mono BTL application; note 5 P o output power R L =8Ω; V P = ±5 V THD =.5% W THD = % 8 4 W R L =4Ω; V P = ±7 V THD =.5% 8 87 W THD = % W THD total harmonic distortion P o = W; note 3 f i = khz..5 % f i = khz. % G v(cl) closed loop voltage gain db η efficiency P o = 3 W; f i = khz; note 4 94 % Notes. V P = ±5 V; R L =4Ω;f i = khz; f osc = 3 khz; R s =. Ω(series resistance of filter coil);t amb =5 C; measured in reference design (SE application) shown in Fig.7; unless otherwise specified.. Indirectly measured; based on R ds(on) measurement. 3. Total Harmonic Distortion (THD) is measured in a bandwidth of Hz to khz. When distortion is measured using a low-order low-pass filter a significantly higher value will be found, due to the switching frequency outside the audio band. 4. Efficiency for power stage; output power measured across the loudspeaker load. 5. V P = ±5 V; R L =8Ω;f i = khz; f osc = 3 khz; R s =. Ω(series resistance of filter coil);t amb =5 C; measured in reference design (BTL application) shown in Fig.7; unless otherwise specified. Oct

12 4 SWITCHING CHARACTERISTICS V P = ±5 V; T amb =5 C; measured in Fig.6; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PWM outputs (pins OUT and OUT); see Fig.5 t r rise time 3 ns t f fall time 3 ns t blank blanking time 7 ns t PD propagation delay from pin SW (SW) to ns pin OUT (OUT) t W(min) minimum pulse width note 7 ns R ds(on) on-resistance of the output transistors..3 Ω Note. When used in combination with TDA899T controller, the effective minimum pulse width during clipping is.5t W(min). 4. Duty factor For the practical useable minimum and maximum duty factor (δ) which determines the maximum output power: t W(min) f osc % < δ < t W(min) f osc % Using the typical values: 3.5% < δ < 96.5%. Oct

13 handbook, full pagewidth /f osc V DD PWM output (V) V V SS t r t f t blank t PD V SW (V) V STAB V SS V REL (V) V STAB V SS ns MGW45 Fig.5 Timing diagram PWM output, switch and release signals. Oct 3

14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be... Oct 4 V V EN V SW V nf V V V REL V STAB kω V V DIAG V SW V EN SW REL DIAG POWERUP V STAB EN SW REL V REL andbook, full pagewidth J CONTROL AND HANDSHAKE temp current Fig.6 Test diagram. DRIVER HIGH DRIVER LOW TEMPERATURE SENSOR AND CURRENT PROTECTION CONTROL AND HANDSHAKE DRIVER HIGH DRIVER LOW V DD V DD 3 5 V SS V SS 6 7 V DD 8 V SS BOOT OUT BOOT OUT V OUT 5 nf V OUT 5 nf V V MGW84 V DD 5 TEST AND APPLICATION INFORMATION Philips Semiconductors

15 5. BTL application When using the system in a mono BTL application (for more output power), the inputs of both channels of the PWM modulator must be connected in parallel; the phase of one of the inputs must be inverted. In principle the loudspeaker can be connected between the outputs of the two single-ended demodulation filters. 5. Package ground connection The heatsink of the J/ST is connected internally to V SS. 5.3 Output power The output power in single-ended applications can be estimated using the formula P o(%) = R L ( R L + R ds(on) + R s ) V ( t f ) P W(min) osc R L [ V The maximum current I P ( t W(min) f osc )] O(max) = should not exceed 7.5 A. R L + R ds(on) + R s The output power in BTL applications can be estimated using the formula P o(%) = R L R L + ( R ds(on) + R s ) V ( t f ) P W(min) osc R L [ V The maximum current I P ( t W(min) f osc )] O(max) = should not exceed 7.5 A. R L + ( R ds(on) + R s ) Where: R L = load impedance R s = series resistance of filter coil P o(%) = output power just at clipping The output power at THD = %: P o(%) =.5 P o(%). 5.4 Reference design The reference design for a two-chip class-d audio for J and TDA899T is shown in Fig.7. The Printed-Circuit Board (PCB) layout is shown in Fig.8. The bill of materials is given in Table. Oct 5

16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be... Oct 6 C5 47 nf D (5.6 V) input V DDA GND R9 39 kω C4 47 nf R5 kω C8 nf J QGND on mute off V SS mode select V SSA J5 J6 R 39 kω S C6 47 nf R4 kω J J3 3 MODE 6 7 PWM C44 nf 3 SW 4 REL R OSC 6 EN 7 U 7 kω C3 nf SGND GND SGND C 33 pf C3 33 pf C7 47 nf R6 kω C9 nf input J4 QGND inputs C V DDA C V DD V DD IN+ 5 IN 4 IN+ 8 IN 9 R7 kω GND R4 V DD TDA899T kω TDA896J 5 9 STAB POWERUP 5 or V DD C4 D 3 nf (7.5 V) J C5 STAB C7 8 V SSD V SSA V SSD 9 nf C43 nf V SS 8 pf R DIAG 3 V DIAGCUR kω SS CONTROLLER POWER STAGE 8 +5 V 5 V 5 n.c. nf nf V SSA V SS V SS C3 nf V DD 3 V SS C3 nf EN REL 3 SW 4 PWM QGND QGND L5 bead R kω R 9. kω bead L6 C3 nf C33 nf L7 bead SW 7 REL 6 EN 4 V DDD EN 4 REL SW V DDD C34 5 µf (35 V) C35 5 µf (35 V) V SSD handbook, full pagewidth C36 nf C38 nf power supply OUT C37 nf C39 nf BOOT BOOT OUT 7 R and R are necessary only in BTL applications with asymmetrical supply. BTL: remove R6, R7, C3, C6 and C7 and close J5 and J6. C and C3 influence the low-pass frequency response and should be tuned with the real load (loudspeaker). Inputs floating or inputs referenced to QGND (close J and J4) or referenced to V SS (close J and J3) for an input signal ground reference. U C 56 pf R 5.6 Ω V DDD C8 5 nf C9 5 nf R3 5.6 Ω C 56 pf C4 47 µf (35 V) C4 47 µf (35 V) V DDD V DDA GND V SSA V SSD Sumida 33 µh CDRH7-33 V DDD C6 nf V SSD Sumida 33 µh CDRH7-33 L4 R4 5.6 Ω V SSD C 56 pf R 5.6 Ω MLD633 L C3 56 pf C4 47 nf C6 47 nf Fig.7 Two-chip class-d audio application diagram for J and TDA899T. 6 R5 4 Ω C5 nf C7 nf R6 4 Ω C8 nf C9 nf C nf C nf QGND QGND GND QGND QGND OUT OUT+ OUT OUT+ OUT OUT+ outputs 4 or 8 Ω SE 8 Ω BTL 4 or 8 Ω SE Philips Semiconductors

17 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be... Oct 7 C6 C4 Out Out L4 TDA896J/7J & TDA899T C34 C35 D V DD L5 U GND V SS L6 L7 In Silk screen top, top view In Silk screen bottom, top view D C4 C4 state of D art Version 3- R9 C C6 R C44 C43 C38 C9 R6 C3 R C3 C C36 R3 R4 C7 U C C5 C3 J5 C5 R C33 R J6 R5 C C37 C C4 C8 C3 C7 C39 R C R4 In In L R5 R7 R R Out Out C8 R4 R6 V C9 C C9 DD VSS GND J J3 J J4 C C8 C3 C3 QGND S C4 C5 C6 C7 ON MUTE OFF Fig.8 Printed-circuit board layout for J and TDA899T. andbook, full pagewidth Copper top, top view Copper bottom, top view MLD634 Philips Semiconductors

18 5.5 Reference design bill of materials Table Two-chip class-d audio PCB (Version.; 3-) for J and TDA899T (see Figs 7 and 8) COMPONENT DESCRIPTION VALUE COMMENTS In and In Cinch input connectors Farnell: Out, Out, V DD, GND and V SS supply/output connectors Augat 5KEV-; Augat 5KEV-3 S on/mute/off switch PCB switch Knitter ATE E M-O-M U power stage IC TDA896J/7J DBS7P package U controller IC TDA899T SO4 package L and L4 demodulation filter coils 33 µh Sumida CDRH7-33 L5, L6 and L7 power supply ferrite beads 3 Murata BLRN-A6 C and C supply decoupling capacitors for nf/63 V SMD6 V DD to V SS of the controller C3 clock decoupling capacitor nf/63 V SMD6 C4 V decoupling capacitor of the nf/63 V SMD6 controller C5 V decoupling capacitor of the power nf/63 V SMD6 stage C6 and C7 supply decoupling capacitors for nf/63 V SMD6 V DD to V SS of the power stage C8 and C9 bootstrap capacitors 5 nf/5 V SMD85 C, C, snubber capacitors 56 pf/ V 4 SMD85 C and C3 C4 and C6 demodulation filter capacitors 47 nf/63 V MKT C5 and C7 resonance suppress capacitors nf/63 V SMD6 C8, C9, common mode HF coupling capacitors nf/5 V 4 SMD85 C and C C and C3 input filter capacitors 33 pf/5 V SMD6 C4, C5, input capacitors 47 nf/63 V 4 MKT C6 and C7 C8, C9, common mode HF coupling capacitors nf/5 V SMD85 C3 and C3 C3 and C33 power supply decoupling capacitors nf/63 V SMD6 C34 and C35 power supply electrolytic capacitors 5 µf/35 V Rubycon ZL very low ESR (large switching currents) C36, C37, analog supply decoupling capacitors nf/63 V 4 SMD6 C38 and C39 C4 and C4 analog supply electrolytic capacitors 47 µf/35 V Rubycon ZA low ESR C43 diagnostic capacitor 8 pf/5 V SMD6 C44 mode capacitor nf/63 V SMD6 D 5.6 V Zener diode BZX79C5V6 DO-35 D 7.5 V Zener diode BZX79C7V5 DO-35 R clock adjustment resistor 7 kω SMD6 Oct 8

19 COMPONENT DESCRIPTION VALUE COMMENTS R4, R5, input resistors kω 4 SMD6 R6 and R7 R diagnostic resistor kω SMD6 R, R, snubber resistors 5.6 Ω; >.5 W 4 SMD6 R3 and R4 R5 and R6 resonance suppression resistors 4 Ω SMD6 R9 mode select resistor 39 kω SMD6 R mute select resistor 39 kω SMD6 R resistor needed when using an kω SMD6 asymmetrical supply R resistor needed when using an 9. kω SMD6 asymmetrical supply R4 bias resistor for powering-up the power stage kω SMD6 Oct 9

20 5.6 Curves measured in reference design THD+N (%) MLD67 THD+N (%) MLD68 () () (3) 3 3 P o (W) f i (Hz) 5 8 Ω SE; V P = ±5 V. () khz. khz. (3) Hz. 8 Ω SE; V P = ±5 V. () P o =W. P o =W. Fig.9 Total harmonic distortion plus noise as a function of output power. Fig. Total harmonic distortion plus noise as a function of input frequency. THD+N (%) MLD69 THD+N (%) MLD63 () () (3) 3 3 P o (W) f i (Hz) 5 4 Ω SE; V P = ±5 V. () khz. khz. (3) Hz. 4 Ω SE; V P = ±5 V. () P o =W. P o =W. Fig. Total harmonic distortion plus noise as a function of output power. Fig. Total harmonic distortion plus as a function of input frequency. Oct

21 THD+N (%) MLD63 THD+N (%) MLD63 () () (3) 3 3 P o (W) f i (Hz) 5 8 Ω BTL; V P = ±5 V. () khz. khz. (3) Hz. 8 Ω BTL; V P = ±5 V. () P o =W. P o =W. Fig.3 Total harmonic distortion plus noise as a function of output power. Fig.4 Total harmonic distortion plus noise as a function of input frequency. 5 P (W) MLD69 η (%) 8 (3) () MLD6 5 () (3) 3 P o (W) P o (W) V P = ±5 V; f i = khz. () 4 Ω SE. 8 Ω BTL. (3) 8 Ω SE. Fig.5 Power dissipation as a function of output power. V P = ±5 V; f i = khz. () 4 Ω SE. 8 Ω BTL. (3) 8 Ω SE. Fig.6 Efficiency as a function of output power. Oct

22 P o (W) 6 MGU893 P o (W) 6 MGU894 () 8 () (3) 8 (3) 4 (4) 4 (4) V P (V) V P (V) 35 THD+N=.5%; f i = khz. () 4 Ω BTL. 8 Ω BTL. (3) 4 Ω SE. (4) 8 Ω SE. Fig.7 Output power as a function of supply voltage. THD + N = %; f i = khz. () 4 Ω BTL. 8 Ω BTL. (3) 4 Ω SE. (4) 8 Ω SE. Fig.8 Output power as a function of supply voltage. α cs (db) MLD63 α cs (db) MLD () 6 () f i (Hz) f i (Hz) 8 Ω SE; V P = ±5 V. () P o =W. P o =W. Fig.9 Channel separation as a function of input frequency. 4 Ω SE; V P = ±5 V. () P o =W. P o =W. Fig. Channel separation as a function of input frequency. Oct

23 45 G (db) MLD65 45 G (db) MLD () 35 () 3 3 (3) 5 (3) f i (Hz) f i (Hz) V P = ±5 V; V i = mv; R s =kω/c i = 33 pf. () 8 Ω BTL. 8 Ω SE. (3) 4 Ω SE. Fig. Gain as a function of input frequency. V P = ±5 V; V i = mv; R s =Ω. () 8 Ω BTL. 8 Ω SE. (3) 4 Ω SE. Fig. Gain as a function of input frequency. SVRR (db) MLD67 SVRR (db) MLD () 6 () (3) 6 (3) f i (Hz) V ripple(p-p) (V) V P = ±5 V; V ripple(p-p) =V. () Both supply lines in antiphase. Both supply lines in phase. (3) One supply line rippled. Fig.3 Supply voltage ripple rejection as a function of input frequency. V P = ±5 V. () f ripple = khz. f ripple = Hz. (3) f ripple =Hz. Fig.4 Supply voltage ripple rejection as a function of ripple voltage (peak-to-peak value). Oct 3

24 I q (ma) 8 MLD69 38 f clk (khz) 37 MLD V P (V) V P (V) R L = open-circuit. R L = open-circuit. Fig.5 Quiescent current as a function of supply voltage. Fig.6 Clock frequency as a function of supply voltage. 5 V ripple (V) 4 MLD6 5 SVRR (%) 4 MLD6 3 3 () () P o (W) 3 f i (Hz) 4 V P = ±5 V; 5 µf per supply line; f i =Hz. () 4 Ω SE. 8 Ω SE. Fig.7 Supply voltage ripple as a function of output power. V P = ±5 V; 5 µf per supply line. () P o = 3 W into 4 Ω SE. P o = 5 W into 8 Ω SE. Fig.8 Supply voltage ripple rejection as a function of input frequency. Oct 4

25 THD+N (%) MLD63 5 P o (W) 4 MLD64 () 3 (3) f clk (khz) f clk (khz) V P = ±5 V; P o = W in 8 Ω. () khz. khz. (3) Hz. Fig.9 Total harmonic distortion plus noise as a function of clock frequency. V P = ±5 V; R L = 8Ω; f i = khz; THD +N=%. Fig.3 Output power as a function of clock frequency. 5 I q (ma) MLD65 V r(pwm) (mv) 8 MLD f clk (khz) f clk (khz) V P = ±5 V; R L = open-circuit. V P = ±5 V; R L = 8Ω. Fig.3 Quiescent current as a function of clock frequency. Fig.3 PWM residual voltage as a function of clock frequency. Oct 5

26 6 PACKAGE OUTLINES DBS7P: plastic DIL-bent-SIL power package; 7 leads (lead length mm) SOT43- D non-concave x Dh E h view B: mounting base side d A B j E A L 3 L Q c v M 7 Z e e b p w M m e 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A b p c D () d D E () e e Z () h e E h j L L 3 m Q v w x mm Note. Plastic or metal protrusions of.5 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT Oct 6

27 7 SOLDERING 7. Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our Data Handbook IC6; Integrated Circuit Packages (document order number ). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 7. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 6 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg(max) ). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 7.3 Manual soldering Apply the soldering iron (4 V or less) to the lead(s) of the package, either below the seating plane or not more than mm above it. If the temperature of the soldering iron bit is less than 3 C it may remain in contact for up to seconds. If the bit temperature is between 3 and 4 C, contact may be up to 5 seconds. 7.4 Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL suitable suitable () WAVE Note. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Oct 7

28 8 DATA SHEET STATUS LEVEL DATA SHEET STATUS () PRODUCT STATUS (3) DEFINITION I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Notes. Please consult the most recently issued data sheet before initiating or completing a design.. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 9 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 634). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Oct 8

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32 a worldwide company Contact information For additional information please visit Fax: For sales offices addresses send to: sales.addresses@ Koninklijke Philips Electronics N.V. SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 75353//pp3 Date of release: Oct Document order number: