16-channel analog multiplexer/demultiplexer. The HEF4067B is suitable for use over the full industrial ( 40 C to +85 C) temperature range.
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1 Rev March 2010 Product data sheet 1. General description The is a with four address inputs (A0 to A3), an active LOW enable input (), sixteen independent inputs/outputs (Y0 to Y15) and a common input/output (). The device contains sixteen bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y15) and the other side connected to the common input/output (). With LOW, one of the sixteen switches is selected (low-impedance ON-state) by A0 to A3. All unselected switches are in the high-impedance OFF-state. With HIGH all switches are in the high-impedance OFF-state, independent of A0 to A3. The analog inputs/outputs (Y0 to Y15 and ) can swing between as a positive limit and as a negative limit. to may not exceed 15 V. The is suitable for use over the full industrial ( 40 C to +85 C) temperature range. 2. Features and benefits 3. Applications Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range 40 C to +85 C Complies with JDC standard JSD 13-B 4. Ordering information Industrial and automotive Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating Table 1. Ordering information Type number Package Temperature range Name Description Version P 40 C to +85 C DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1 T 40 C to +85 C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
2 5. Functional diagram 9 Y0 8 Y1 A Y2 6 Y3 A Y4 4 Y5 A Y6 2 Y7 A OF-16 DCODR 23 Y8 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y Y aag123 Fig 1. Functional diagram 001aag126 Fig 2. Schematic diagram (one switch) _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
3 Y0 Y1 Y2 Y3 A0 Y4 Y5 Y6 A1 Y7 Y8 Y9 A2 Y10 Y11 Y12 A3 Y13 Y14 Y15 001aag125 Fig 3. Logic diagram _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
4 6. Pinning information 6.1 Pinning 1 24 Y Y8 Y Y9 Y Y10 Y Y11 Y3 Y Y12 Y13 Y Y14 Y Y15 A A A A3 001aag124 Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description 1 common input/output Y0 to Y15 9, 8, 7, 6, 5, 4, 3, 2, 23, 22, 21, 20, 19, 18, 17, 16 independent input/output A0 to A3 10, 11, 14, 13 address input 12 ground (0 V) 15 enable input (active LOW) 24 supply voltage _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
5 7. Functional description Table 3. Function table [1] Control Address Channel ON A3 A2 A1 A0 L L L L L Y0 = L L L L H Y1 = L L L H L Y2 = L L L H H Y3 = L L H L L Y4 = L L H L H Y5 = L L H H L Y6 = L L H H H Y7 = L H L L L Y8 = L H L L H Y9 = L H L H L Y10 = L H L H H Y11 = L H H L L Y12 = L H H L H Y13 = L H H H L Y14 = L H H H H Y15 = H X X X X none [1] H = HIGH voltage level; L = LOW voltage level; X = don t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IC 60134). Voltages are referenced to = 0 V (ground). Symbol Parameter Conditions Min Max Unit supply voltage V I IK input clamping current pins An and ; - ±10 ma V I < 0.5 V or V I > +0.5 V V I input voltage V I I/O input/output current [1] - ±10 ma I DD supply current - 50 ma T stg storage temperature C T amb ambient temperature C _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
6 Table 4. Limiting values continued In accordance with the Absolute Maximum Rating System (IC 60134). Voltages are referenced to = 0 V (ground). Symbol Parameter Conditions Min Max Unit P tot total power dissipation T amb = 40 C to +125 C DIP24 [2] mw SO24 [3] mw P power dissipation per output mw [1] To avoid drawing current out of terminal, when switch current flows into terminals, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal, no current will flow out of terminals, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and may not exceed or. [2] For DIP24 packages: above T amb = 70 C, P tot derates linearly at 12 mw/k. [3] For SO24 packages: above T amb = 70 C, P tot derates linearly at 8 mw/k. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit supply voltage 3-15 V V I input voltage 0 - V T amb ambient temperature in free air C Δt/ΔV input transition rise and fall rate = 5 V μs/v = 10 V μs/v = 15 V μs/v 10. Static characteristics Table 6. Static characteristics = 0 V; V I = or ; unless otherwise specified. Symbol Parameter Conditions T amb = 40 C T amb = +25 C T amb = +85 C Unit V IL V IH I I I O LOW-level input voltage HIGH-level input voltage input leakage current OFF-state output current Min Max Min Max Min Max I O < 1 μa V O = 0.5 V or 4.5 V 5 V V V O = 1.0 V or 9.0 V 10 V V V O = 1.5 V or 13.5 V 15 V V I O < 1 μa V O = 0.5 V or 4.5 V 5 V V V O = 1.0 V or 9.0 V 10 V V V O = 1.5 V or 13.5 V 15 V V V I =0Vor15V 15 V - ±0.3 - ±0.3 - ±1.0 μa output at 15 V μa output at 15 V μa _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
7 Table 6. Static characteristics continued = 0 V; V I = or ; unless otherwise specified. Symbol Parameter Conditions T amb = 40 C T amb = +25 C T amb = +85 C Unit I S(OFF) OFF-state leakage current port; all channels OFF; see Figure 5 port; per channel; see Figure 6 Min Max Min Max Min Max 15 V na 15 V na I DD supply current all valid input combinations; 5 V μa I O =0A 10 V μa 15 V μa C I input capacitance digital inputs 15 V pf 10.1 Test circuits or A0 to A3 IS VO VI 001aal616 Fig 5. Test circuit for measuring OFF-state leakage current port or A0 to A3 Y0 1 2 switch IS VI VO 001aal617 Fig 6. Test circuit for measuring OFF-state leakage current port _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
8 10.2 On resistance Table 7. ON resistance T amb = 25 C; I SW =200μA; = 0 V. Symbol Parameter Conditions Typ Max Unit R ON(peak) ON resistance (peak) V I = 0 V to ; see Figure 7 and 5 V Ω Figure 8 10 V Ω 15 V Ω R ON(rail) ON resistance (rail) V I = 0 V; see Figure 7 and Figure 8 5 V Ω 10 V Ω 15 V Ω V I = ; see Figure 7 and Figure 8 5 V Ω 10 V Ω 15 V Ω ΔR ON ON resistance mismatch between channels V I = 0 V to ; see Figure 7 5 V 25 - Ω 10 V 10 - Ω 15 V 5 - Ω On resistance waveform and test circuit aae648 R ON (Ω) 300 = 5 V VSW V 200 or A0 to A V 15 V ISW VI 001aag V I (V) R ON =V SW /I SW. I is = 200 μa; = 0 V. Fig 7. Test circuit for measuring R ON Fig 8. Typical R ON as a function of input voltage _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
9 11. Dynamic characteristics Table 8. Dynamic characteristics T amb = 25 C; = 0 V; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit t PHL HIGH to LOW propagation delay, to, ; see Figure 9 5 V ns 10 V ns 15 V ns An to, ; see Figure 10 5 V ns 10 V ns 15 V ns t PLH LOW to HIGH propagation delay, to, ; see Figure 9 5 V ns 10 V ns 15 V ns An to, ; see Figure 10 5 V ns 10 V ns 15 V ns t PH HIGH to OFF-state propagation delay to, ; see Figure 11 5 V ns 10 V ns 15 V ns t PL LOW to OFF-state propagation delay to, ; see Figure 11 5 V ns 10 V ns 15 V ns t PH OFF-state to HIGH propagation delay to, ; see Figure 11 5 V ns 10 V ns to, ; see Figure V ns t PL OFF-state to LOW propagation delay 5 V ns 10 V ns 15 V ns _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
10 11.1 Waveforms and test circuit V I or input An input 0 V V OH or output V OL t PLH t PHL 001aag199 V O or output V X t PLH switch OFF switch ON switch OFF 001aal618 V Y t PHL Measurement points are given in Table 9. V OL and V OH are typical output voltage levels that occur with the output load. Measurement points are given in Table 9. Fig 9., to, propagation delays Fig 10. Sn to, propagation delays V I input 0 V t PL t PL or output V OL V X t PH t PH V OH V Y or output 0 V switch ON switch OFF switch ON 001aag198 Fig 11. Measurement points are shown in Table 9. V OL and V OH are typical output voltage levels that occur with the output load. nable and disable times Table 9. Measurement points Supply voltage Input Output V CC V I V X V Y 5 V to 15 V 0.5 GND to % 90% _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
11 PULS GNRATOR VI DUT VO S1 open RT CL 001aag183 Fig 12. Test data is given in Table 10. Definitions test circuit: R T = termination resistance should be equal to output impedance o of the pulse generator C L = load capacitance including jig and probe capacitance R L = load resistor S1 = test selection switch Test circuit for measuring switching times Table 10. Test data Input Load S1 position, An and t r, t f C L R L t [1] PHL t PLH t PH, t PH t PL, t PL other or or 20 ns pf 10 kω or [1] For to or to propagation delays use. For An or to or propagation delays use. _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
12 11.2 Additional dynamic parameters Table 11. Additional dynamic characteristics = 0 V; T amb = 25 C. Symbol Parameter Conditions Typ Max Unit THD total harmonic distortion see Figure 13; R L =10kΩ; C L =15pF; 5 V [1] % channel ON; V I =0.5 (p-p); 10 V [1] % f i =1kHz 15 V [1] % f ( 3dB) 3 db frequency response see Figure 14; R L = 1 kω; C L = 5 pf; 5 V [1] 13 - MHz channel ON; V I =0.5 (p-p) 10 V [1] 40 - MHz 15 V [1] 70 - MHz α iso isolation (OFF-state) see Figure 15; f i = 1 MHz; R L = 1 kω; C L = 5 pf; channel OFF; V I =0.5 (p-p) 10 V [1] 50 - db V ct crosstalk voltage digital inputs to switch; see Figure 16; R L = 10 kω; C L =15pF; or An = (square-wave) Xtalk crosstalk between switches; see Figure 17; f i = 1 MHz; R L =1 kω; V I =0.5 (p-p) [1] f i is biased at 0.5 ; V I =0.5 (p-p). 10 V 50 - mv 10 V [1] 50 - db Table 12. Dynamic power dissipation P D P D can be calculated from the formulas shown; = 0 V; t r = t f 20 ns; T amb = 25 C. Symbol Parameter Typical formula for P D (μw) where: P D dynamic power 5V P D = 1000 f i + Σ(f o C L ) V 2 DD f i = input frequency in MHz; dissipation 10 V P D = 5500 f i + Σ(f o C L ) V 2 DD f o = output frequency in MHz; 15 V P D = f i + Σ(f o C L ) V 2 DD C L = output load capacitance in pf; = supply voltage in V; Σ(C L f o ) = sum of the outputs Test circuits or A0 to A3 or A0 to A3 fi CL D fi CL db 001aag aag235 Fig 13. Test circuit for measuring total harmonic distortion Fig 14. Test circuit for measuring frequency response _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
13 or A0 to A3 Y0 1 2 switch CL db fi 001aal619 Fig 15. Test circuit for measuring isolation (OFF-state) 0.5 A0 to A3 Y0 1 2 switch or CL V VO G 001aag128 a. Test circuit logic input (An, ) off on off V O Vct 001aal620 b. Input and output pulse definitions Fig 16. Test circuit for measuring crosstalk voltage between digital inputs and switch or A0 to A3 Y0 or A0 to A3 Y0 VI VO VO VI 001aag aag131 a. Switch closed condition b. Switch open condition Fig 17. Test circuit for measuring crosstalk between switches _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
14 12. Package outline DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1 seating plane D A 2 A M L A 1 24 e b b 1 13 w M c (e ) 1 M H pin 1 index mm scale DIMNSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. A 1 A 2 (1) (1) min. max. b b 1 c D e e 1 L M M H w (1) max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLIN VRSION RFRNCS IC JDC JITA UROPAN PROJCTION ISSU DAT SOT G02 MO-015 SC Fig 18. Package outline SOT101-1 (DIP24) _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
15 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D A X c y H v M A Q A 2 A 1 (A ) 3 A pin 1 index L L p θ 1 e b p 12 w M detail X mm scale DIMNSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max A 1 A 2 A 3 b p c D (1) (1) e H (1) L L p Q v w y Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLIN VRSION RFRNCS IC JDC JITA UROPAN PROJCTION ISSU DAT SOT MS Fig 19. Package outline SOT137-1 (SO24) _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
16 13. Abbreviations Table 13. Acronym DUT Abbreviations Description Device Under Test 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes _ Product data sheet - _4 _ Product data sheet - _CNV_3 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Family specifications included. _CNV_ Product specification - _CNV_2 _CNV_ Product specification - - _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
17 15. Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at U Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer s third party customer(s) (hereinafter both referred to as Application ). It is customer s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. xport control This document as well as the item(s) described herein may be subject to export control regulations. xport might require a prior authorization from national authorities Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
18 16. Contact information For more information, please visit: For sales office addresses, please send an to: _5 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev March of 19
19 17. Contents 1 General description Features and benefits Applications Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Test circuits On resistance On resistance waveform and test circuit Dynamic characteristics Waveforms and test circuit Additional dynamic parameters Test circuits Package outline Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 25 March 2010 Document identifier: _5
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Rev. 9 21 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a fully synchronous edge-triggered with eight synchronous parallel
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Rev. 3 3 November 2016 Product data sheet 1. General description 2. Features and benefits The is a triple 3-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 9 30 ugust 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an (parallel-to-serial converter) with a synchronous serial data input (DS), a clock
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More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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Rev. 2 7 December 2016 Product data sheet 1. General description The provides the non-inverting buffer. The output of this device is an open drain and can be connected to other open-drain outputs to implement
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Rev. 9 15 December 2016 Product data sheet 1. General description The provides two non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply
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More information74HC04; 74HCT04. Temperature range Name Description Version 74HC04D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 74HCT04D
Rev. 5 27 November 2015 Product data sheet 1. General description 2. Features and benefits The is a hex inverter. The inputs include clamp diodes that enable the use of current limiting resistors to interface
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Rev. 1 19 December 2016 Product data sheet 1. General description The is a hex buffer with open-drain outputs. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low
More information2-input NAND gate; open drain. The 74LVC1G38 provides a 2-input NAND function.
Rev. 8 7 December 2016 Product data sheet 1. General description The provides a 2-input NAND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device
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Rev. 3 25 April 2018 Product data sheet 1 General description is a. It consists of a chain of 10 flip-flops. Each flip-flop divides the frequency of the previous flip-flop by two, consequently the counts
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Rev. 3 26 October 2016 Product data sheet 1. General description The is a dual non-retriggerable monostable multivibrator. Each multivibrator features edge-triggered inputs (na and nb), either of which
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Rev. 1 21 ugust 212 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. This product has been qualified to the utomotive Electronics
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Rev. 8 3 November 20 Product data sheet. General description The high-performance Bipolar CMOS (BiCMOS) device combines low static and dynamic power dissipation with high speed and high output drive. The
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Rev. 11 28 November 2016 Product data sheet 1. General description The provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Rev. 7 16 November 011 Product data sheet 1. General description. Features
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