Jayaprakash et al., International Journal of Advanced Engineering Technology E-ISSN

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1 Research Paper LOW POWER AND AREA EFFICIENT MULTIPLIER-ACCUMULATOR UNIT FOR FIR FILTER Dr. M. Jayaprakash 1, Dr. V. V. Karthikeyan 2, M. Peermohamed 3 Address for Correspondence 1 Associate Professor, 2 Professor, Dept. Of EEE,Karpagam College of Engineering, 3 Asst. Prof., Dept. Of ECE, SCAD Institute of Technology ABSTRACT In the research field, the amplify demand of portable devices formulate Low power device design. Among the integrated circuits, Power dissipation is one of the primary design objectives, after speed. In VLSI system design, Design of low area, delay and power forms the foremost systems. These three strictures i.e. power, area and speed are always traded off. Though, area and speed are typically conflicting constraints, so that improving speed results mostly in larger areas. In microprocessors, digital signal processors, and data-processing application-specific integrated circuits, addition and multiplication of two binary numbers are the basic and most recurrently used arithmetic operation. Accumulator unit addition and multiplication forms the main blocks in Multiplier. The applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc, a high speed and low power MAC units are necessitated. In MAC unit, area and speed are the most significant aspects, but occasionally, increasing speed also boosts the power consumption, accordingly there is an upper bound of speed for specified power criteria. As the various filter designs found in the Digital Signal Processing applications, entail computationally efficient multiply and Accumulate operations, thus the blocks with the desired traits have to be chosen carefully. To design and analysis various adder and multiplication ideas for high-speed, area efficient and low power operation Multiplier Accumulator unit is the main intent of this paper. In Verilog, all Adders and Multipliers are depicted and synthesized using Xilinx Spartan-3E trainer kit and subsequently the 8-tap FIR filter is executed with the proposed MAC unit using Virtex-4 FPGA board. The Virtex-4 board is utilized while it has plentiful DSP slices. KEYWORDS VLSI, MAC, FPGA, Virtex-4, FIR, Xilinx. I. INTRODUCTION In current scenario, Digital Signal Processing (DSP) with its new applications is receiving prominence in the commercial processors. It has diverse architectures and features than general purpose processors, and the performance gains of these features largely resolve the performance of the whole processor. The demand for these unique features roots from algorithms that necessitate complete computation and to map to these algorithms, the hardware is often designed. Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter, and Fast Fourier Transform (FFT) are broadly used with DSP algorithms. Efficient computation of these algorithms is a direct result of the efficient design of the primary hardware. Digital signal processing such as filtering, convolution, and inner products, the multiplier and multiplier- accumulator (MAC) are the essential elements. This unit can calculate the running sum of products, which is at the heart of algorithms such as the FIR and FFT. The capability to compute with a fast MAC unit is vital to achieve high performance in many DSP algorithms, and is why there is at least one obsessive MAC unit in all of the modern commercial DSP processors. In most of the digital signal processing methods, nonlinear functions such as discrete cosine transform (DCT) or discrete wavelet transform (DWT) is used [7]. On considering that, they are vitally carry out by monotonous application of multiplication and addition, the speed of the multiplication and addition arithmetic s settle on the carrying out speed proceedings and performance of the integral calculation. In general, the critical path is dogged by the multiplier, while the multiplier entails the greatest delay among the basic operational blocks in digital system. The hub of every microprocessor, DSP and dataprocessing ASIC is its data path. Statistics showed that more than 70% of the instructions perform additions and multiplications in the data path of RISC machines [1]. At the heart of data-path and addressing units in turn are arithmetic units, such as comparators, adders, and multipliers. Digital multipliers are the most commonly used components in any digital circuit design. Multiplication based operations such as Multiply and Accumulate and inner product are among some of the frequently used Computation Intensive Arithmetic Functions, currently implemented in many DSP applications such as convolution, fast Fourier transform, filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications [6]. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications. The MAC unit resolves the speed of the overall system; it always lies in the critical path. There are two major tailbacks that need to be considered, so as to improve the speed of the MAC unit. The first one is the partial products reduction network that is used in the multiplication block and the second one is the accumulator. Both stages require toting up of large operands that engross long paths for carry propagation. To speed up the multiplication process implements both the multiplication and the accumulation operations within the same functional block by assimilating the accumulator with the multiplication circuit using tree architectures for the partial products reduction network[12]. The wide-ranging construction of the MAC operation can be presented by this equation Z= A x B + Z Where, the multiplier A and multiplicand B are assumed to have n bits each and the addend Z has

2 (2n+1) bits. The basic MAC Unit is made up of a multiplier and an accumulator as shown in Figure 1. Fig. 1 MAC unit The multiplier can also be divided into the partial products generator, summation tree, and final adder. This construct leads to four basic blocks to implement. The summation network represents the core of the MAC unit. This block inhabits most of the area and consumes most of the circuit power and delay. Several algorithms and architectures are developed in attempt to optimize the implementation of this block. It executes the multiplication operation by multiplying the input multiplier and the multiplicand. This is added to the previous multiplication result as the accumulation step. The basic MAC operation comprises of a multiplication which can be divided into three operational steps. The first is radix-2 Booth encoding in which a partial product is generated from the multiplicand and the multiplier. The second is adder array or partial product compression to add all partial products and convert them into the form of sum and carry. The last is the final addition in which the final multiplication result is produced by adding the sum and the carry. II. ADDER TOPOLOGIES The design of high-speed and low-power VLSI architectures needs proficient arithmetic processing units, which are optimized for the performance parameters, namely, speed and power consumption. In general, for purpose microprocessors and digital signal processors Adders are the key components. It is also used in various functions such as subtraction, multiplication and division. Accordingly, it is very important that its performance s is well for their speed performance. Besides, for the applications such as the RISC processor design, where single cycle execution of instructions is the key measure of performance of the circuits, use of an efficient adder circuit becomes obligatory, to realize efficient system performance [6]. Additionally, in the design of fast adders, the area is an essential factor and it is taken for consideration. To the extreme, for highperformance processors and systems, high-speed, low power and area efficient addition and multiplication has always been a primary constraint. The major speed restraints of adders arise from the huge carry propagation delay encountered in the conventional adder circuits, such as ripple carry adder and carry save adder. The subsequent adder topologies are simulated and analysis is made for proposed MAC unit. Ripple Carry Adder Block Carry Look-Ahead Adder Ripple block Carry Look-Ahead Adder Carry Increment adder Carry Skip Adder with fixed block size Carry Skip Adder with variable block size Carry Select Adder Conditional Sum Adder A. Simulation Results of Adder Topologies The choices of adders pointed out above are synthesized and simulated using FPGA board. The FPGA board used here is Spartan- 3E XC3S500E, PQ208 configuration. Table I illustrates the simulated output of the adders such as Area, Delay and Power dissipation. TABLE I: AREA, DELAY AND POWER COMPARISON OF ADDER TOPOLOGIES Adders Area Delay Power Dissipation Block Carry Look ahead adder (BCLA) 33.29% ns 85.83mW Carry Select Adder (CSA) 39.73% ns 83.88mW Carry Skip adder with fixed block size (CSFBA) 33.29% ns 85.83mW Carry Skip adder with Variable block size (CSVBA) 36.51% ns 83.85mW Conditional Sum Adder (CoSA) 55.84% ns 88.72mW Ripple block carry look ahead adder (RBCLA) 33.92% ns 85.83mW Ripple Carry Adder (RCA) 33.29% ns 84.2mW Carry Increment Adder (CIA) 42.29% ns 92.35mW Fig 2. Area comparison of adder topologies Fig 3. Delay comparison of adder topologies

3 In the area assessment, it is observed that the maximum area is required for Conditional sum adder and next comes Carry increment adder. The slightest area required for Block Carry look ahead adder, Carry skip adder with fixed block size, Ripple block carry look ahead adder and Ripple carry adder. From the delay comparison shown in Table I and Fig 3 it is observed that the maximum delay take place for Carry increment adder. The least delay occurs for Conditional sum adder and Carry select adder and it is somewhat varied to Conditional sum adder. Together with the adders analysed, the Carry increment adder is having larger power dissipation. Among these adders, power dissipation is almost same and compared to these entire adders carry select adder is having reasonable power dissipation and area with high speed. The overall contrast presents the trade-off between area, delay and power consumption. By analysing various adder topologies, Conditional sum adder has nominal delay but greatest area consumption. Correspondingly, the adders such as Block carry look ahead adder, Carry skip adder with fixed block size, Ripple block carry look ahead adder and Ripple carry adder are having minimal area requirement from Fig 2 but having maximum delay, when related to Conditional sum adder. When match up to all the above four adders, Carry select adder is having a maximum area consumption but having minimum delay. Next by analysing the Carry select adder with conditional sum adder, the delay of Conditional sum adder is lower than carry select adder. In the same way, the area consumption of Carry select adder is lower than Conditional sum adder. According to the available outcome, the adder topology which has the best cooperation between area, delay and power dissipation from Fig 4 is Carry select adder which is suitable for high performance and low-power circuits. III. MULTIPLIER TOPOLOGIES The basic function used in digital signal processing is Multiplication. More than addition and subtraction it Fig 4. Power dissipation comparison of adder topologies entails more hardware resources and processing time. In actual fact, 8.72% of all instructions in a typical processing are multiplier [2]. A typical central processing unit allocates a sizeable amount of processing time in implementing arithmetic operations, particularly multiplication operations in computers. Most high performance digital signal processing systems rely on hardware multiplication to attain high data throughput. The element which contributes substantially to the total power consumption of the system is none other than the Multiplier. Multiplication is the main function in multiply and accumulate (MAC) unit, thus there is a need of high speed multiplier.[5] Currently, in determining the instruction cycle time of a DSP chip, multiplication time is still an overriding factor. The amount of circuitry involved is directly proportional to square of its resolution i.e., a multiplier of size of n bits has O(n 2 ) gates [8]. In this effort the following multiplier structures are synthesized and analyzed for proposed MAC unit. Booth Multiplier Modified Booth Multiplier Wallace tree multiplier Booth Encoded Wallace Tree Multiplier. A. Simulation Results of Multiplier Topologies The design of the above four 16x16 bit multipliers have been implemented on Spartan 3E (XC3S 500E). The table II shows the simulated output of preferred multipliers. All association based on the synthesis signifies keeping one common base for comparison which means, targeting the same FPGA device with same design constraints disguised for the synthesis of each multiplier. From Table II, the booth multiplier is having an area of 50.47% which is less when compared to other three multipliers. When coming to delay the Wallace tree is having ns which is less when compared to other multipliers. TABLE II: AREA, DELAY AND POWER DISSIPATION OF MULTIPLIER TOPOLOGIES Multipliers Area Delay Power Dissipation Booth Multiplier (BM) 45.32% mw Modified Booth Multiplier (MBM) 51.43% mw Wallace tree Multiplier (WTM) 73.23% mw Wallace tree Multiplier (MBWTM) 54.87% mw Fig 5. Area comparison of multiplier topologies

4 But the Wallace tree has an area of 54.87% which is slightly higher than Booth and Modified Booth multiplier. Fig 7 Power dissipation comparison of multiplier topologies Fig 6 Delay comparison of multiplier topologies But when comparing delay the Modified Booth Encoded Wallace tree is having ns which are lower than Booth and Modified Booth multiplier and higher than Wallace tree multiplier. As there is tradeoff between area, delay and power consumption, the Wallace tree multiplier is elected for designing low power and high speed MAC Unit. After selecting the optimized multiplier i.e., Modified booth encoded Wallace tree multiplier, the different adders are combined with this multiplier and simulated. The Table III shows the comparison of the multiplier and adder combination. TABLE III: AREA, DELAY AND POWER DISSIPATION COMPARISON OF MODIFIED BOOTH ENCODED WALLACE TREE MULTIPLIER WITH VARIOUS ADDERS Multipliers Area Delay Power Dissipation Wallace tree Multiplier with Carry look ahead adder (MA1) 31% mw Wallace tree Multiplier with carry skip fixed block adder (MA2) 37% mw Wallace tree Multiplier with carry skip variable block adder (MA3) 31% mw Wallace tree Multiplier with Ripple Carry adder (MA4) 34% mw Wallace tree Multiplier with carry select adder (MA5) 35% mw From the comparison the area is approximately same for all the combinations. But the delay for carry select adder combination is less, when compared to all other combination. So modified booth encoded Wallace tree multiplier with carry select adder for partial product generation is chosen for proposed multiply and accumulate unit. Fig 8 Area comparison of modified booth encd. wallace tree multiplier with various adder topologies Fig 9 Delay comparison of modified booth encd. wallace tree multiplier with various adder topologies Fig 10 Power Dissipation comparison of modified booth encd. wallace tree multiplier with various adder topologies In Spartan 3E (XC3S 500E) the design of various multiplier and multiplier/ adder combination have been executed. Of all the multipliers bestowed in this paper, the modified booth encoded Wallace tree multiplier is selected for MAC unit. Scrutiny made using multiplier with diverse adders exhibit that, carry select adder combination is having maximum speed and competence. Although carry select adder combination is having little area overhead, modified booth encoded Wallace tree multiplier with carry select adder can be chosen for designing the MAC unit because there is a trade-off between area, delay and power. IV. PROPOSED MAC UNIT FOR DIGITAL FILTERS In signal processing applications, Digital filters are the most repeatedly used elements. Amongst digital filters, FIR filters are favoured due to their stability, easily achievable linear-phase property, and low

5 quantization word length sensitivity. All these desirable properties come with a drawback compared to their recursive counterparts IIR filters: increased computational workload, hence power. This, in turn, leads to extreme amount of power dissipation which is a bottleneck for today s low power demanding applications. In the majority of digital signal processing (DSP) applications the critical operations are the multiplication and accumulation. Multiplier- Accumulator (MAC) unit that devours low power is always a key to achieve a high performance digital signal processing system. Finite impulse response (FIR) filters are widely used in various DSP applications. Optimized area and delay MAC unit for FIR filter is analysed in this paper. The adders and multipliers are analysed and comparison is made on the basics of power consumption, area and delay. Commencing the analysis, the Carry select adder and Wallace tree multiplier is elected for proposed MAC unit. The Figure 11 shows the MAC unit with selected adders and multipliers. Fig 11 MAC Unit with proposed Adder and Multiplier The MAC unit is divided into three pipe stages so it has the ability to be clocked at a faster rate. The latency is three cycles for a MAC or multiplies instruction, but the throughput is one operation per cycle. Figure 5.1 shows a block diagram of the MAC unit with the proposed adder and multiplier. The first pipe stage is for spawning the partial products and the second pipe stage prolongs accumulation of the partial products. The third and final pipe stage restrains accumulator to complete the MAC. This stage is the critical pipeline stage of the MAC unit. The adder is to be chosen which gives optimized power, area and delay for the accumulator. The selected adder and multiplier fabrication is synthesized with other adder for analyzing whether the selected adder and multiplier combination with an adder for accumulator is best among all the adders with proposed adder and multiplier combination. The Table IV gives the comparison of different adders with selected adder and multiplier combination for MAC unit. Commencing the comparison, the MAC unit is chosen with area efficient, low power and delay. TABLE IV: COMPARISON OF DIFFERENT ADDERS WITH SELECTED ADDER AND MULTIPLIER COMBINATION MAC Area Delay Carry select adder Combination with Block Carry look ahead adder (MAC 1) Carry select adder with carry look ahead adder (MAC 2) Carry select adder combination with carry select adder (MAC 3) carry select adder combination with fixed block size carry skip adder Power Dissipation 6% ns mw 6% ns mw 6% ns mw 6% ns mw (MAC 4) By synthesizing the selected adder and multiplier combination with other adders, the analysis is made for different MAC unit. From the comparison, the area for all the MAC unit is 6% and the power dissipation is almost similar. Subsequently, the carry select adder is having the lowest delay with all the adders by comparing the delay of each MAC unit. The carry select adder is chosen for accumulation hitherto. Figure 12 shows the graph for the MAC unit comparison based on area, delay and power consumption. Fig 12 Area, Delay and Power Consumption comparisons

6 The MAC unit determines the speed of the overall system; it always lies in the critical path. Many researchers have attempted in designing MAC architecture with high computational performance and low power consumption. In order to improve the speed of the MAC unit, there are two major bottlenecks that need to be considered. The first one is the partial products reduction network that is used in the multiplication block and the second one is the accumulator. Both of these stages require addition of large operands that involve long paths for carry propagation [10]. The carry select adder and Modified booth encoded Wallace tree multiplier is chosen for partial product reduction and for accumulation carry select adder. From the selected adders and multiplier, pipelining is introduced for further reduction in area, power and delay [9]. The Figure 13 shows the proposed MAC unit (pipelined MAC unit). Fig 13 Proposed MAC unit The speed of the MAC unit can further increased by pipelining. The speed of the MAC unit is greatly improved by proper deciding the number of pipeline stages and the positions for the pipeline registers to be inserted as discussed [3]. Pipelines are widely used to improve the performance of digital circuits, since they provide a simple way of implementing parallelism from streams of sequential operations. In a pipelining system, the maximum operating frequency is limited by slowest stage which has the longest delay. As more stages are inserted in the pipeline, each stage becomes shorter and ideally presents a smaller delay. Theoretically, the pipeline depth can be pushed to a level of using a single gate between two registers as discussed [4] But usually, there is a compromise between performance improvements obtained with increased pipeline depth and the penalties imposed by the additional memory elements inserted in between the stages. So trade-off between the reduction in delay due to pipelining and increase in area must always be considered. The Table V gives the area, power and delay values after synthesizing the proposed MAC unit with pipelining. Speed increases by the factor of 2.1 with penalty on the area increasing by the factor of 0.85 by means of utilizing pipelining. TABLE IV: PROPOSED MAC UNIT AREA, DELAY AND POWER DISSIPATION VALUES Proposed Lut Delay Power MAC unit 7% ns mw Though, speed improvement ratio is larger than the area increase ratio, and it is concluded that pipelining develops performance of MAC unit. Power dissipation also reduces by a factor of All comparison for adders, Multipliers and MAC unit based on the synthesis reports keeping one common base for comparison. To facilitate the same FPGA device is besieged (part number and speed grade) with the same design restrained implied for the synthesis of each multiplier. A. Proposed MAC Unit for FIR Filter Finite impulse response (FIR) filters are extensively used in various DSP applications.this section depicts an approach to the implementation of low power digital FIR filter using proposed MAC unit. For arithmetic circuits, a large portion of the dynamic power is wasted on un-productive signal glitches. Glitches are due to converging combinatorial paths with different propagation delays. Signal glitching refers to the transitory switching activity within a circuit as logic values propagate through multiple levels of combinational logic [11]. Pipelining is a simple and effective way of reducing glitching, and hence minimizing power consumption. It is found that, at a given clock speed, pipelining can reduce the amount of energy per operation by between 40% and 90% for applications such as integer multiplication, CORDIC, triple DES, and FIR filters [10]. The Figure 14 shows the synthesis output of FIR filter with proposed MAC unit. The target board used for simulating and synthesizing the 8 tap FIR filter is Virtex 4. Figure 14 Synthesis output for FIR with proposed MAC unit

7 V. CONCLUSION This paper gives a general conclusion and some recommended new directions are accessible in this paper. To design suitable low power MAC unit for FIR filters is the intent of this paper. This thesis investigates and examines fast adder and multiplication schemes, and utilizes them in the design and implementation of a MAC unit. In this paper, a low power, area efficient and high speed bit MAC unit has been presented. The basic building blocks for the MAC unit are identified and each block is analysed for its recital. Using Spartan- 3E XC3S500E, PQ208 trainer kit using Xilinx 13.2 software and Xilinx ISIM simulator for simulation, the designs of various adders and multipliers have been executed on FPGA board. On different techniques for low power and efficient adders and multipliers for MAC unit, a swot up has done. As of the cram, the pipelining technique is used for proposed MAC unit, where its adder and multiplier for partial product generation and it has been synthesized and analysed. Additionally, by various performance measures, appraisal of different adders and multipliers is done. Deliberations made in adder topologies exemplifies that the carry select adder along with all the adders is having the optimized power and delay, with increase in smaller area. Carry select adder has comparatively low value of critical path length hence less combinational path delay but it has higher number of leaf cell count and combinational path area. From multiplier topologies modified booth encoded Wallace tree multiplier is analyzed as the optimized one, as there is a swap between area, delay and power. The pipelining is the most broadly used method to get better performance of digital circuits. The speed increases by the factor of 50% with penalty on area increasing by factor of 1% by utilizing the pipelining technique for proposed MAC unit. It is fulfilled that pipelining progresses performance of multiplier even if; speed improvement ratio is superior to the area increase ratio. Comparisons are based on the synthesis reports keeping one common base for comparison specifically, the same FPGA device with same design constraints cloaked for the synthesis of each adder, multiplier and MAC unit. In this paper, Design for low power FIR filter using proposed MAC unit has been accessed. Proposed MAC unit on Virtex-4 board is implemented with the 8 tap FIR Filter. The power reduction is achieved through the usage of a proposed MAC unit inside the filters that diminish the total activity and consequently the dynamic power. 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