AVI AUTOMATIC VEHICLE IDENTIFICATION SERVICE MANUAL 6042 IUNION SWITCH & ANS ALDO Trasporti JJECEMBER, 1978 A

Transcription

1 UNON SWTCH & SERVCE MANUAL 6042 A member of lhe ANSAl.00 Gn>up 5800 Corporala Drive. Pilllburgh. PA AV AUTOMATC VEHCLE DENTFCATON JJECEMBER, 1978 A CCPYRGT 19111, UNON SWm:1-1 & SGNM. NC. PRNT:O N USA ANS ALDO Trasporti

2 UNON SWTCH & SGNAL [ml SERVCE MANUAL 6042 A member of lhe ANSALOO Group 5800 Corporate Drive, Pittsburgh, PA AV AUTOMATC VEHCLE DENTFCATON JJECEMBER, 1978 A-3/ COPYRGHT 1991, UNON SWTCH & SGNAL NC. PRNTED N USA ANSALDO Trasporti

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4 CONTENTS Section NTRODUCTON 1.1 GENERAL 1.2 PRNCPLES OF OPERATON 1.3 FUNCTONAL DESCRPTON 1.3.l Car-Carried Equipment Transponder Coil Programmer Wayside Equipment Wayside Coil nterrogator Decoder/Logic Unit Specifications l Functional Specifications Equipment Specifications Data Capacity CAR-CARRED EQUPMENT 2.1 GENERAL 2.2 DESCRPTON 2.2.l Programmer Transponder Coil Cable Assembly 2.3 THEORY OF OPERATON (Basic) 2.4 THEORY OF OPERATON (Detailed) 2.4.l Signal Name Description WAYSDE EQUPMENT 3.1 GENERAL 3.2 DESCRPTON 3.2.l nterrogator Wayside Coil Decoder Logic Unit l Decoder Logic Unit (Basic) Decoder Logic Unit (Route Buffer) Decoder Logic Unit (ASC nterface) 3.3 THEORY OF OPERATON (Basic) 3.4 NTERROGATOR. 3.4.l Theory of Operation (Detailed) 3.5 DECODER LOGC UNT 3.5.l Receiver PCB N Description Theory of Operation Decoder Logic Panel Description Basic Theory of Operation Detailed Theory of Operation Route Buffer Panel (Option #1) ASC nterface Panel (Option #2) Page ' S i

5 Contents cont'd. Section V Power Distribution and nterface PCB Description Theory of Operation Decoder Wire Wrap Panel Connections AV Decoder Wiring NSTALLATON 4.1 CAR-CARRED EQUPMENT Required Equipment Transponder Coil Programmer Cable Assembly nterface Wiring (Programmer) Car Number nsertion 4.2 WAYSDE EQUPMENT Required Equipment Wayside Procedure Equipment Room Procedure 4.3 SYSTEM ADJUSTMENTS AND TUNNG nterrogator Adjustments Power Output and Tuning Adjustments Received Signal Level Adjustments V MANTENANCE - TROUBLESHOOTNG 5.1 NTRODUCTON Maintainer Capabilities 5.2 GENERAL ALGNMENT 5.3 BASC SYSTEM TROUBLESHOOTNG Recommended Equipment General Basic System Failures Wayside Malfunction Symptoms 5.4 SHOP MANTENANCE Required AV Equipment Suggested Test Equipment Optional Test Equipment Accessory Test Components Miscellaneous Accessories 5.5. PERODC MANTENANCE 5.6 CAR-CARRED EQUPMENT TROUBLESHOOTNG (With Flow Charts) General AV Equipment Required Basic Test and Programmer Troubleshooting Transponder Cable Assembly Test Transponder Coil Test Page / ii.

6 Contents cont'd. Section NTERROGATOR TROUBLESHOOTNG Physical nspection Required AV Equipment Suggested Test Equipment Suggested Test Accessories Notes/Cautions/Warnings nterrogator Transmitter Test Power Output and Tuning Adjustments nterrogator Return Signal Test Received Signal and Level Adjustments WAYSDE COL Physical nspection Suggested Test Equipment Test Accessories Test Procedure DECODER LOGC UNT TROUBLESHOOTNG General Malfunction Symptoms Fault solation Power Supply Troubleshooting Power Distribution and nterface PCB Test General nitial Procedure Power Supply Test EA Data Channel Test Track Signal Test Cab Signal Test Continuity Tests Rceiver PCB Troubleshooting General Suggested Test Equipment Power Supply Test Clock Test Test Mode Test Demodulator and Carrier Detect Tests Receiver PCB Tuning Adjustments Decoder Logic Panel Troubleshooting Basic Troubleshooting Detailed Troubleshooting. s4o ,.: V DRAWNGS AND PARTS LSTS 6-1 iii

7 LST OF LLUSTRATONS Figure nterconnections of TWC Carborne Elements AV Transponder Coil Details of Transponder Coil Assembly and Mounting Constraints Minimum Transponder Spacing AV Programmer Physical Location of TWC Carborne Elements Block Diagram of TWC Wayside Equipment AV Wayside Coil AV nterrogator With Cover TWC Decoder/Logic Unit TWC Message Format AV Programmer With Cover Removed Block Diagram of AV Vehicle Mounted Programmer AV nterrogator Without Cover Decoder/Logic Unit Cover Removed Receiver Block Diagram Decoder Logic Panel Block Diagram AV/TWC System, Test and Troubleshooting Guide AV/TWC Wayside System, Testing, and Troubleshooting Guide Relay Room, AV/TWC Testing and Troubleshooting Guide nterrogator, Testing and Troubleshooting Guide ncorrect Response, Testing and Troubleshooting Guide Cab Signal Missing External ndication, Test and Troubleshooting Guide Route nformation ncorrect, Test and Troubleshooting Guide Car-Carried Equipment Troubleshooting Flow Chart Status nput Test Cable Assembly Transponder Coil Circuit Resonant Frequency Test Circuit Wayside Test nterconnections AV System Test Circuit Decoder Logic Unit Test Circuit nterrogator (Transmitter) TP2 Waveform nterrogator (Transmitter) TP3 Waveform nterrogator (Transmitter) Al and A2 Waveforms Typical Message Format TP5 Waveform Typical Message Format (Expanded) Zero Crossing Waveform nterrogator (Return Signal) TPll Waveform nterrogator (Return Signal) TP15 Waveform nterrogator (Return Signal) TP18 and TP16 Waveforms nterrogator Troubleshooting Flow Chart Wayside Coil Test Set-Up Wayside Coil Test Circuit Decoder Logic Unit Major Component Location Page / thru thru 5-19/ / J / / / / iv

8 List of llustrations cont'd. Figure Page Power Supply and Cab Signal Troubleshooting Guide EA Data Channel Troubleshooting Guide Track Signal Troubleshooting Guide Receiver PCB Pins 1-2 Waveform Receiver PCB TP7 Waveform Receiver PCB TP8 and TP9 Waveform Receiver PCB TP8 and TP9 (Expanded) Waveform Receiver PCB Bandpass Filter Test Circuit Receiver PCB Sensitivity and Phase Locked Loop Test Circuit Basic Decoder Logic Unit Troubleshooting Guide Basic Decoder Logic Panel Troubleshooting Guide Detailed Decoder Logic Panel Troubleshooting Guide AV Programmer Assembly Progranuner Logic Diagram Programmer Logic Diagram (cont'd.) Programmer Timing Diagram Programmer PCB Component Location Transponder Coil Assembly AV Car-Carried Cable Assembly nterrogator Assembly Amplifier PCB Schematic Amplifier PCB Component Location Control PCB Schematic Control PCB Component Location nterrogator nterconnection Wiring Diagram Decoder Logic Unit With/Without Route Buffer Assembly Decoder Logic Unit With ASC nterface Panel Assembly Receiver PCB Schematic Receiver PCB Component Location Decoder Logic Panel Logic Diagram Decoder Logic Panel Logic Diagram (cont'd.) Decoder Logic Panel Logic Diagram (cont'd.) Decoder Logic nput Timing Chart Decoder Logic nput_timing Chart (cont'd.) Decoder Logic Output Timing Chart(cont'd.) Decoder Test Error Message Timing Chart Decoder Test Good Message Timing Chart Decoder Error Detection Timing Chart Decoder Logic Unit Panels Component Location Power Distribution and nterface PCB Schematic Power Distribution and nterface PCB Component Location Wayside Junction Box Assembly Wayside Coil Assembly / / / /4 6-5/6 6-7/8 6-9/ / / / / / / / / / / / / / / / / / / / / / / / / / / /64 v

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10 SECTON NTRODUCTON 1.1 GENERAL The function of WABCO's Automatic Vehicle dentification (AV) System is to provide a means for transmitting data from a moving object to a fixed location. Data transmission is in the form of high-speed digital data. The transmission.medium is inductive coupling. The signal is transmitted from the car via a small loop coil on board and received by a similar loop coil located on the wayside. The signal is then transmitted via a wire to decoding equipment-at a convenient nearby location. The information is available at this location to perform desired functions, to provide desired information, or for retransmission of the message to a central office location for additional functions or data logging. 1.2 PRNCPLES OF OPERATON The AV system works on the passive/active transponder principle. The vehicle carried equipment contains a means of encoding information and a signal source for transmission of the information to the wayside via the carborne coil. This electronic circuitry is not powered by the car battery and, consequently, is normally inactive. A high frequency signal (at KHz.) is continuously transmitted by the Wayside Coil. The carborne circuitry derives its operating power and timing signals from this wayside signal. When the carborne coil is positioned over the Wayside Coil, the carborne electronics is activated and caused to transmit its encoded information back to the Wayside Coil. The carborne signal consists of a 76.8 KHz. carrier, phase modulated by the encoded data. The Wayside Coil is connected to decoding equipment which recovers the carborne data for further processing. Once this data has been received on the wayside, it is utilized in a number of ways. nformation, such as a run number, is utilized locally at the wayside to select routes in advance of a vehicle or for train identity on station sign qisplays. nformation as to car status, run number, and car number can be transmitted from the wayside to a central office via standard digital data transmission (i.e., carrier) equipment to provide for display of train identification or train status information. 6042, p. 1-1

11 Present WABCO specifications call for a system that will identify uniquely and simultaneously 9,999 transit cars, 20 run designations, and provide indications of train cab signal status. The car numbers are programmed on each car, the cab signal information is provided by external contact closures, while the run designation is operator programmed utilizing thumb-wheel type switches. The Train to Wayside Communication (TWC) system normally operates at a maximum vehicle velocity of 68 MPH. The TWC system was designed to provide a maximum operating speed of 84 MPH given a 48 bit message length, a 2400 bit per second data rate, and a Wayside coil longitudinal dimension of 42". (This provides for one complete message at 84 MPH.) 1.3 FUNCTONAL DESCRPTON Car-Carried Equipment The TWC equipment, located on each car, consists of two units. These units are the Transponder Coil and the Programmer. Refer to Figure 1-1 for a pictorial diagram of the car-carried TWC equipment. These units are interconnected by means of a 40 foot cable. This cable length is standard and must not be shortened Transponder Coil The Transponder Coil assembly is located under the car on the longitudinal centerline and contains the passive components (two tuned LC circui.ts) necessary to receive the activation signal from the Wayside coil and couple the data signal back to the wayside. Physically, this unit is 15" x 15" x 3" thick, constructed of molded fiberglass resin. The unit is weatherproof and resilient.to normal impact damage. Refer to Figure 1-2 for a view of the T.ransponder. Figure 1-3 provides a view of the application limitations for mounting of this. unit. t must not be physically located too close to metallic surfaces. The nominal detection range is 12" to 14". The Transponder Coil must be mounted centered to within ±1" of the centerline of the car. A minimum spacing between transponders on adjacent cars must be maintained as shown in Figure 1-4.,, , p. 1-2

12 CAB SGNAL NPUT LEAD CAR NPUT {_ {-----f SPAflE SPA RE.. CONNECTOR MS- TRAN DESTNATON DATA ENTRY BY TWO THUMB-WHEEL SWTCHES PROGRAMMER CONNECTOR,A MS-2 '\ TRANSPONDER COL ASSEMBLY : CABLE ASS EM BL y ' _..J SHELD NOTE: MAXMUM LENGTH OF THE MS-2 CABLE NOT TO EXCEED 40 FEET. Figure 1-1. nterconnections of TWC Carborne Elements 6042, p. 1-3

13 Figure 1-2 AV TRANSPONDER COL 6042, p. 1-4

14 SUPPORT BRACKET FOR COL ASSEMBLY TO BE SO DESGNED THAT CONDUCTVE PARTS DO NOT FORM A SHORTED TURN (61 MOUNTNG HOLES 7 /16 DA. WTHN AREA ENCLOSED BY DASHED LNES ABSOLUTELY NO CONOUCTVE MATERAL\:TiA LEAO TO COL r f', 6"R \ l f/ // l, / ;...,, / -c ' / o '\. / 2 ' / a ' : z ' / N ' / ' ' TOP OF RAL " ----Ja.f i " :,,-.j Figure 1-3 Details of Transponder Coil Assembly and Mounting Constraints 6042, p. 1-5

15 0\ 0 ti:.. \.)... "O... 0\ "A" Car Transponder x -»J< Y' "B" car Transponder -,,.,. L Z' X' = 20 Feet Minimum Y' = 40 Feet' Minimum z = 20 Feet Minimum Figure 1-4. Minimum Transponder Spacing,:... r

16 Programmer ' J.. The programmer is normally located in the motorman's cab. Two thumb-wheel type switches, located on the front panel, allow entry of variable route data (refer to Figure 1-5). Physically, this unit is 2.5" x 7.25" x 4.5" deep in dimension. t is suitable for mounting in an existing panel. Two MS style connectors are located on the back of the Programmer. one of these provides for interconnections to the Transponder Coil. The second connector provides for the input of variable contact closure information from the motorman's key switch and other equipment. The interface to the auxiliary inputs, if utilized, is by optical isolators. The car battery must supply a current for this interface. Figure 1-6 illustrates the interconnection of the Programmer with the transponder and the auxiliary data inputs Wayside Equipment The wayside equipment at each location where information is to be received is comprised of three elements; (1) Wayside Coil, (2) nterrogator and (3) Decoder/Logic. These units taken together constitute a complete wayside location. Refer to Figure 1-7 for a block diagram of a wayside location Wayside Coil The Wayside Coil is suitable for mounting between the running rails. This unit is 48" x 16" x l" thick and is made of molded fiberglass sufficiently strong to resist normal operating use. The actual coil. winding is 42" x 14". Refer to Figure nterrogator {See Figure 1-9)..., The nterrogator provides the actuation signal required to power the vehicle mounted transponder. Additionally, the nterrogator receives the data transmitted from the vehicle and couples this signal into the Decoder/Logic Unit. Refer to Figure 1-7 for a block diagram of the nterrogator. The power amplifier provides the actuation signal for the transponder. The amplifier operates at 153,600 Hz, providing a power output of 120 watts maximum into the Wayside Coil. The Transponder, when activated, transmits to the wayside a 76,800 Hz. phase modulated data signal. This signal is coupled into the Wayside Coil and fed into a line driver. This driver feeds the 76,800 Hz. signal directly as received into a 135 ohm balanced line, that is terminated in the Decoder Logic Unit receiver. 6042, p. 1-7

17 ;....! \' ifli'j ":;, \,. Figure 1-5 AV PROGRAMMER 6042, p. 1-8

18 4 JC '" PROGRAMMER UNT MS-1, DATA NPUTS(CABLNG NOT FURNSHED) MS-2 CABLE, PROGRAMMER TO TRANSPONDER FXED LENGTH 40'. (THS CABLE FURNSHED WTH CONNECTORS). 0\ 0.a::,. N... l'{j -' ' Figure 1-6. TRANSPONDER COL- MOUNTED UNDER CAR BODY Physical Location of TWC Carborne Elements

19 117 VAC or Hz. Wayside Coil Power Supply coupling Unit NTERROGATOR 135 Ohm Balanced Line J Receiver!4--.. Decoder..., _. Cab Signal ndication --- Data Set Output (EA) Track Ckt. nput 117 VAC@ 60 Hz. L Power Supply DECODER/LOGC UNT nterface J Figure 1-7. Block Diagram of TWC Wayside Equipment 6042 P _ 1-10

20 Figure 1-8. AV WAYSDE COL 6042, P. 1-11

21 y :2 Figure 1-9. AV NTERROGATOR WTH COVER 6042, p. 1-12

22 Decoder/Logic Unit (See Figure 1-10) The receiver demodulates the 76.8 KHz. signal and recovers the digital data. The data from the receiver is fed into the decoder. The decoder checks the received data for errors, assures that the track circuit over the loop is occupied, and outputs the decoded message when an indication is received that a transponder is no longer over the loop. The data output is available in two forms--parallel and serial. The parallel output provides all the received bits at logic levels (0 VDC and +12 VDC). The serial output is fed through a buffer, making this output compatible with RFL, WABCO, or any standard EA interface data set. The output data rate is jumper selectable. (The decoder also contains space for an "applications" circuit card.) This applications card provides 20 separate reed contacts corresponding to routes, or an ASC compatible communication interface. r ' ON TWC DECODER LOGC UNT UN45l465- Figure , p. 1-13

23 1.3.3 Specifications Functional Specifications Transmission Range--18" (45cm) nominal Between Coils--Absolute Range Limits--0" to 24" (0 cm-61 cm) Data Capacity--28 binary data bits (see programmer specifications for standard bit assigent) Operating Temperature Range/-40 F to +158 F (-4o 0 c to +7o 0 c) Equipment Specifications Carborne Equipment.. Transponder Coil: Dimensions--12" x 12" x 2" (0.3m x 0.3m x 5.0 cm) exclusive of mounting brackets (15 x 15 x 3 with bracket) Weight--7 lb-11 oz (3.5 kg) Furnished with integral MS type connector for cable connection to progammer Cable Assembly--2 twisted pairs with shield and MS connectors. Fixed length 40' (12.19m) but can be supplied in other lengths upon request. Programmer: Dimensions--Approximately 2.5" x 4" x 7" (6.5 cm x 10 cm x 18 cm) exclusive of mounting brackets Weight--1 lb-4 oz (0.6 kg) Terminations--one MS connector for interconnection to transponder and one MS connector for external data entry Power Consumption--none* Data Format--28 bits, standard configuration as follows (other configurations can be supplied upon request) 1st and 2nd 4 bit words--bcd encoded numbers (0-2; 0-9) accessible via thumbwheel switches on front panel ("tens" and "units" route request) 3rd, 4th, 5th, 6th 4 bit words--provides four (0-9) independently BCD encoded numbers. Digits each setable by means of internal switches. These digits may be programmed in the field to comprise a four digit ( ) number or any other combination of four 0-9 digits. *External battery %5 ma@ 36V each external status input. 6042, p. 1-14

24 7th 4 bit word--provides four independently programmable bits, accessible via an MS connector. Each bit is interfaced to the external environment via an electrooptical interface. External battery is required to activate these data*. Message Security and Synchronization--BCH error detection 6 bits plus additional parity are transmitted as an integral part of the message. Twelve bit synchronization message. Modulation--Bi-polar phase shift keying, 76.8 KHz. carrier. Wayside Equipment nterrogator: Dimensions--Case mounted weatherproof unit 16-1/2" x 20 x 8-3/4" (42 cm x 51 cm x 22 cm) in depth. Nineteen inch rack mounted unit 12" x 19" x 5" (30 cm x 48 cm x 13 cm) in depth. Power Consumption--120 watts at 117 or 240 VAC, 60 Hz. Output Frequency KHz. Wayside Coil--(Fiberglass encapsulated assembly intended for tie mounting): Dimensions--48" x 16" x 1-1/2" (l.22m x 0.4m x 3.8 cm in height). Decoder-Logic Unit: Dimensions--(19" rack mounted unit) 3" x 19" x 12" (8 cm x 48 cm x 30 cm) in depth. Power Consumption--12 watts at 117 VAC, 60 Hz. Data nputs--accepts 76.8 KHz. serially encoded PSK message from car-carried transponder. Data outputs--(1) Serial message format replicating valid carborne message EA standard RS232C electrical interface. Message keying speed variable from 1so to 1200 baud. (2) Parallel data output through connector (optional). (3) ASC serial interface (optional). 20 or 60 ma. current loop and EA standard RS232C electrical interface. Message keying speed variable from 75 to 9600 baud. *External battery %5 36V each external status input. 6042, p. 1-15

25 1.3.4 Data Capacity The AV message provides for 28 bits of binary data. The assignment of these bits can be varied, depending upon the application,using a fixed message or a programmed message or combination of both. At present, these bits are encoded into six groups of 4 bits {complement BCD encoding) to provide for 6 decimal diqits of capacity, and 4 additional spare bits. A typical system has the following information assignments: Digits A, B Digits C, D, E, F Spare Auxiliaf Digit Status ndication Two digit train destination numbers for routing and run number identification. These digits can be varied by thumb-wheel switch entry. Car serial number. These 4 digits are field programmable by means of switches not accessible to the operator. Capacity - 9,999 vehicles. This digit is used to provide for 4 bits of external status data entry. The four spare data bits can be used as four individual indications such as cab signal activated, lead car, express/ local, etc. The actual final message format consists of 48 bits, of which the first 12 bits produce synchronization, the next 28 bits are the data bits described above, the next bit is fixed "ON", and the remaining 7 bits provide error detection based upon use of a BCH cyclic redundancy polynomial check code. The message format is shown in Figure , p. 1-16

26 ... SYNC BT STRUCTURE / 12SYNCBTS / / / / / / / / / / / / DGT DGT DGT DGT DGT./ A B c D e F 29 DATA BTS (SEE BELOW) \. '\. '\. ' 7CHECK BTS ' ' ' ' " ' AUXLARY DGT /,----DGT ----, '\. ' '\. ' TENS UNTS THOUSANDS HUNDREDS TENS UNTS \ 4BTS 4BTS \ 4BTS 4BTS 4BTS 4BTS v TRAN DESTNATON v CAR SERAL NUMBER LEAD CAR NDCATON ("1" JNDCA TES LEAD CAR CAB SGNAL BT l"o" NDCATES NO CAB SGNAL) 2SPARE BTS DEDCATED BNARY "1" Figure TWC Message Format 6042, p. 1-17/18

27 ......

28 SECTON CAR-CARRED EQUPMENT 2.1 GENERAL The carborne AV system consists of three basic components that generate and transmit a data message to the wayside. These three interconnecting elements are: 1. The Programmer that contains the electronic components to generate the message A Transponder Coil that provides for an inductive transmission coupling path to the Wayside Coil 3. A 40 foot cable with connections to interconnect elements 1 and 2. The Programmer is normally mounted in the console panel in the motorman's cab. The Transponder Coil is mounted on the underbody of the car. The carborne equipment is activated only when the Transponder Coil is within the field of the Wayside Coil. The maximum spacing of the carborne-to-wayside coil is 24". The nominal spacing is 18" (12" - 14" above the railhead). Some advantages of this transponder system are: 1. No power nor power wiring is required by the carborne elements. This minimizes installation costs and results in a high mean-time between failure performance level since the car-carried equipment is only powered for very small time intervals. 2. Timing and carrier frequency information is derived from the wayside, and the car-carried electronics is minimized, enhancing equipment reliability and resuiting in a comparatively small mechanical package. 2.2 DESCRPTON Programmer (Refer to Figure 2-1) The programmer is a self-contained logic unit mounted in a 2.5" x 7" x 4" deep metallic enclosure desgned for panel mounting. 6042, p. 2-1

29 Figure AV PROGRAMMER WTH COVER REMOVED 6042 P 2-2

30 The box contains a printed circuit board that holds all of the Programmer electronics. Two Thumbwheel switches are -provided on the front panel to allow the -operator -to -input a two-digit train destination (route number) from 1 to 20. Four BCD encoded rotary switches are mounted internally on the PCB to store the fixed car serial number. Access to these switches is possible through four holes in the side of the enclosure, only after the cover has been removed. This permits authorized personnel to change the serial number data, but will prevent tampering by unauthorized personnel. Connections to the Programmer are provided via two MS type connectors. One connector has provisions to accept inputs and outputs associated with the Transponder Coil. The second connector accepts inputs from external equipment to.allow control of the four auxiliary data bits if required. No connections are required between the Programmer and car battery or other carborne power source, except for determining the status. of the external data lines (auxiliary bits) and only when these auxiliary bits are used. The auxiliary bits are activated by supplying car battery voltage to the auxiliary inputs on the Programmer Programmer Technical Data Specifications Physical Dimension, Complete Unit: W = 4"; L = 7"; H = 2.5" Weight, Complete Unit: 1 lb., 4 oz./567 G. Electrical* nput Voltage (A.C.): Power Consumption (Maximum): Frequency Range: Temperature Range: Frequency Stability: R.F. Power Output (Maximum): Spurious and Harmonics: Modulation: 19.5 VAC, RMS at KHz 625 Watts KHz. ±15 Hz. over temperature range -4o 0 c to +10 c C-4ooF to +1600F) ±.0097% of assigned frequency.365 Watts -16 db PSK (Phase Shift Keying) *All specifications indicated with Transponder (N ) positioned directly above J Wayside Coil. (Maximum energy transfer.) 6042, p. 2-3

31 2.2.2 Transponder Coil The Transponder Coil assembly consists of two 4 x 8 inch coils of litz wire encapsulated in fiberglass. These two coils provide an inductive reception and transmission path to and from the wayside Coil. The receiver coil is composed of 12 turns of litz wire and is tuned by a capacitor to KHz. to provide the pickup of that signal transmitted from the wayside. Tuning the coil provides maximum signal pickup. The transmitter coil, also located in the transponder assembly, is composed of 16 bifiliar wound.turns of litz wire (32 turns center tapped). t is tuned by a capacitor to 76.8 KHz. to provide maximum gain and coupling of the data signal into the Wayside Coil. The two tuning capacitors are located on a printed circuit board in the 2-1/2" x _2-1/2" x 1-1/2" aluminum box mounted on the center of the fiberglass assembly A waterproof connector. on this box provides input/output connections to the Programmer via the cable assembly._ The Transponder Coil must be mounted on the longitudinal centerline of the underbody of the car. ts only electrical connection is to the Programmer assembly. The Transponder Coii is mounted in a metal protective-framework with provisions for mounting the bracket assembly to the car underbody. However, additional mounting brackets (not supplied by WABCO) are required to mount the coil assembly to the car. Note that the protective framework of the coil has an opening on one side. This opening prevents the bracket from becoming a shorted turn iron coil, which would block reception and transmission of signal to the transponder. This gap must be maintained and must n9t be shunted by any metallic objects when installed under the car body. The transponder must be mounted such that there is a 12 to 14 inch nominal maximum spacing between the bottom of the mounted coil and the railhead. A minimum spacing of a 6_inch (12" nominal) radius must be maintained between the coil assembly and any metallic surface of the car (excluding mounting brackets). The Transponder Coil assembly, including connector housing, is approximately 12 x 12 x 2 inches, less mounting brackets. When installed in the mounting bracket, the dimensions increase to 15-1/2". x 15-1/2" x 3". The weight of the coil assembly is approximately 7 lb. 11 oz. (3.5 Kg.) P 2-4

32 2.2.3 Cable Assembly The cable assembly provides a direct wire connection between the AV Programmer and Transponder Coil assembly to carry the received and transmitted signals between those units. t consists of two individual twisted pair cables with an overall shield. This cable is terminated with a MS style waterproof connector at each end. The cable length is fixed at 40 feet ±1 foot. The cable must not be lengthened or cut, as the capacitance of this cable affects the tuning of the tuned circuit. Any excess cable should be coiled in a convenient manner. NOTE: (Other specified cable lengths are possible, but this would require factory retuning of the Transponder Coils.) 2.3 THEORY OF OPERATON (Basic) The AV carborne electronics is essentially comprised of a scanning system that scans the status of the route and car number switches, and converts that information into a serial data stream. This output, amplified through a power amplifier, drives the transmitting coil that couples the data into the wayside. A block diagram of the carborne system is shown in Figure 2-2. When the Transponder Coil is excited by the field of the Wayside Coil, a KHz. signal is induced into the receiving coil on the transponder. With the coil placed approximately 14 inches above the railhead, this induced KHz. signal is approximately 30 volts peak-to-peak. This voltage is fed via the cable (connector pins A and B) to the Programmer, where it is full-wave rectified and also used as a timing reference to the logic unit. The output of the rectifier is rectified and limited by a 24 volt zener diode. Nominal DC voltage is 13 volts DC. However, if the coil were placed directly on the Wayside Coil, a larger voltage would be induced into the receiving coil, and without the clamping action of the zener diode, the excessive voltage would destroy the electronics. A further regulation of the DC input is performed to provide +10 to a +12 volt supply for the remaining logic hardware. When power is first applied, a reset circuit initializes the logic unit to the beginning time period of the message. The received clock signal then clocks the timing logic that generates strobe signals to scan the status of the six switches and four auxiliary inputs. The switch status is dumped into a data shift register in groups of 8 bits and serially shifted out of the data register into both the BCH register and phase modulator at a rate of 2400 bits per second. The phase modulator converts the data from a binary. one and zero string to a 76.8 KHz. modulated signal that changes phase at the beginning of each data bit when the bit is a logic 1. (Phase is not changed for logic zero data bits.) 6042, p. 2-5

33 ' 0.c:,. t,.,) ' "Cl. (6), 8 Bit Words t,.,) ' KHz Divide/2 Bit Counter Word Counter llll Rect. & ,Filter nput. f Sw1.tch Word Decoder M Matrbtt-1.A.rray Power Up Reset 76.8 KHz 2.A J<Hz 8 Bit Shift Reg. BCH Register 76.8 KHz Phase Encoder Figure 2-2 Block Diagram of AV Vehicle Mounted Programmer "

34 The BCH register generates a 7 bit check character that is outputted to the phase modulator after all of the switch and auxiliary bit information has been serially shifted out of the data register. The modulator drives a pair of transistors that alternately switch (at the modulated signal rate) enerqy into the transmitter coil, setting up a modulated na:gnetic field, coupling the 76.8 KHz. modulated signal into the Wayside Coil. 2.4 THEORY OF OPERATON (Detailed) This explanation refers to Figures 6-2, 6-3 and timing chart Figure 6-4. The carrier signal received by the Transponder Coil is fullwave rectified by the diode bridge 037 through 040 and filtered by capacitor C2 to provide +13 volts to power the logic unit. Another zener regulator and filter (R3, D33 and Cl) provides approximately a +10 volt power supply to power all of the complementary metal oxide semiconductor logic devices (CMOS logic) in the Programmer. n normal operation the Zener diode is not conducting. When power is initially induced into the unit, the discharged RC network, R2 and C7, causes a momentary logic O pulse to appear at pin 11 of C8. The two sections of C8 (output pins 6 and 10) comprise an RS flip-flop, that produces a logic 1 reset signal at pin 10 of C8. This reset pulse is maintained until capacitor C7 charges to about 6 volts (approximately 1 millisecond) and prevents counters (Cl and C2) from counting. After the capacitor C7 is charged, the next cycle of the KHz. input signal clears the reset flip-flop through C7, pin 6, and C8, pin- The 12 bit binary counter, C2, now begins to count the pulses of the KHz. input signal. The output of the first stage of the counter (Ql) divides the clock input by two, producing a 76.8 KHz. signal at pin 9 of C2. This signal is used as the carrier in the phase modulator. The remaining stages of C2 generates a shift pulse (Q6 - pin 2) at a 2.4 KHz. rate, and counts the bits in groups of 8 (from Oto 7) at outputs Q7 through Q9. The third section of gate C8 (pin 9) decodes the count of 7 and produces a dump pulse to the shift register (C5, pin 9) during the eighth bit time. The bit count 4 output of the bit counter advances another counter (Cl). This frame counter is advanced one count every 6042, p. 2-7

35 8 bit times (so each frame is 8 bits).!cl also contains a decoder which decodes its count into a separate output for each count state. The decoded frame signals are used to strobe switches sequentially such that at most two switches are activated during any frame. The individual switch output lines (complementary BCD encoded) are fed through a diode matrix (Dl through D31) into the shift register parallel inputs (!CS). This diode matrix appears as 8 diode "OR gates" with a maximum of four inputs on each gate. The switch matrix is driven by a logical 1 frame signal from the frame counter decoder; only 1 input of any "diode OR" gate is activated at any time. Thus, as the frame counter advances from frame Oto frame 4, the various switches and the auxiliary inputs (from C14) are scanned sequentially. Resistor network C6 provides pull-down reference for the data register inputs. The output of the data register is fed through a one of two input multiplexer (C4, pin 11) into the modulator composed of C12 and one-half of D flip-flop C13. Modulator flip-flop (C13, pin 1) changes state only when the "Data Out" signal into pin 1 of C12 is a logic 1. f, for example, C13, pin 1, is at a logic O {also C12, pin 2) and "Data Out" appearing at C12, pin 1, is a logic 1, then the output of exclusive OR gate C12, pin 3, is a logic 1 and the D flip-flop C13, pin 1, will set to a logic 1 on the next positive excursion of the clock signal at C13, pin 3. C12, pin 2, now becomes a logic 1. f the next "Data out" bit is also a logic 1, the output of exclusive OR gate C12, pin 3, will be a logic O, and the flip-flop will reset to a logic O on the next positive excursion of the clock to te flip-flop. So a series of logic 1 data bits will cause the modulator flip-flop to change state every shift pulse. f, however, the data out line is a logic 0, the output of the flip-flop will not be inverted through the exclusive OR gate. The "D" input to the flip-flop will remain in the same state as the flip-flop output, preventing the flip-flop from changing state. The exclusive OR gate in the application cn be considered as a controlled inverter; i.e., if one input is held at a logic 1, the output of the exclusive OR will be the inversion of the logic level of the other remaining input. f the control input is held at a logic O, the output of the exclusive OR gate will be the same as the remaining input. The output of the modulator flip-flop is combined with the 76.8 KHz. clock signal with another exclusive OR gate C12, pin 4. This exclusive OR gate acts as the controlled inverter described above. When the output of the modulator flip-flop changes phase, the KHz. signal als o changes phase. The remaining two sections of XOR gate provides inverting pin 11 and non-inverting pin 10 outputs (180 degrees out of phase) to drive the final switching amplifier (transistors Ql and Q2). 6042, p. 2-8

36 Ql and Q2 switch the ends of the transmit coil to the power supply common (VSS) at the 76.8 KHz. rate. The center of the transmit coil is fed by the positive supply through resistor RlO. The current through RlO is alternately switched into one side or the other of the coil, creating a changing field in the transmitting coil, phas modulated at a 7.8 KHz. rate. The output of the data register also feeds the BCH character generator (ClO, Cll, and one-half of C13). This circuit produces a 7 bit check word that is shifted out into the power amplifier after the 28 data bits are transmitted. The check character is sequentially generated as the remainder of a division of two polynomials. The data used can be constructed as a dividend of the form: x7 (A x28 + A x27 + A x26 + +A2X2 + A1Xl + Aoxo) where A is bits value, A 28 most significant or first bit, A 0 = 1 = Fixed bit. A= 0 or l. and the divisor.is x 7 + x 6 + x The BCH register performs that division sequentially, and after the 28 data bits and fixed "l bit" are transmitted, the BCH register contains the remainder, that-is then transmitted out as the check character. The timing logic gates the data to and from the various registers to process the data word into the proper format. During the first 8 bit word (frame 0) of the message, the modulator flip-flop is not clocked. (The shift pulses are gated off through AND gate C9.) Since the modulator flip-flop does not change state, the first 8 transmitted bits appear as logic Obits and no phase changes occur in the modulated signal. This 8 bit string of zero bits is the first portion of the synchronization code. The count 7 (8th bit) decoder (C8, pin 9) and frame O signal, dump the start code (1010) and the first four bits of data (route number tens) into the data register at the middle of the last bit time of frame 0, and these bits are shifted into the modulator and transmitted during the 8 bit times of frame 1. Note, the clock is applied to the modulated flip-flop after frame 0. At bit time 4 of frame 1, BCH reset, generated by flip-flop C3, pin 14, is removed from the BCH register, allowing the BCH register to start computing its check word. Note that since reset was applied to the BCH generator previous to this, the sync word ( ) is not entered into the BCH generator and thus does not enter into the computation of the BCH check word. 6042, p. 2-9

37 At bit time 7 of frame 1, at the same time the last data bit is shifted out of the data register, the next 8 bits of data (route number units and car number thousands) are loaded into the data shift register by the bit count 7 signal. This data is shifted out to the modulator and BCH register, and the next two character numbers (car number hundreds and tens) are dumped into the data register at bit count 7 of the next frame. The operation continues as above until all the data is dumped into the data register and shifted out. At bit count 7 of frame 4, the fixed 1 bit and 7 zeros are loaded into the shift register. This fixed 1 bit is shifted out during the first bit time (bit time 0) of frame 5. At bit count 1 of frame 5, flip-flop C3, pin 1, sets and, through data multiplexer C4, disconnects the data register from the modulator flip-flop, connects the BCH register output to the modulator, and serially loads zeros into the BCH registers. By loading zeros into the BCH register, the data is shifted out without any further computation. Note that the fixed 1 bit is fed.into the BCH register and used in the check character computation. At the end of frame 5, data {all zeros) is dumped into the data register but it is ignored. The frame counter decoder momentarily counts into frame 6. The frame 6 signal sets the reset flip-flop {C8) and the process repeats itself again starting at frame O, as long as the Transponder Coil is receing energy om th_ Wayside_ Ci1:_... _ Figure 6-4 is a timing chart indicating the time interval operation of the transponder circuitry. The four auxiliary bits are interfaced into the transponder circuitry through opto-isolators. Each.opto-isolator is individually connected. An RC "T" style filter limits the current into each of the opto-isolators to about 5 milliamperes {assuming a nominal battery voltage of 36 VDC), and filters out any extraneous noise from the DC input lines. A reverse connected diode across the input of the optical isolator prevents damage due to_ reverse _connec'!:ions on the polari;ed inputs. " The output transistors of the isolators are interfaced to the data register through the diode matrix and C14, such that DC voltage applied to an auxiliary input will activate the optoisolator and cause a logic 1 bit to be loaded into the data register, in the appropriate portion of the data message Signal Name Description 60:42, p Bit 1 through Bit 8 The eight parallel inputs to the data shift register. Bit 1 is the most significant bit and is the first bit to be transmitted in each group of 8 bits.

38 Signal Name Description cont'd. Bit Count 1 Bit Count 2 Bit Count 4 Bit Count 7 BCH N BCH Circulate BCH Reset Data Data Out Dump Pulse The output of stage Q7 of the bit counter C2. Nominally a 1.2 KHz. squarewave. This signal is logic 1 on every odd bit count. A logic O on even bit counts. The output of stage Q8 of the bit counter. Nominally a 600 hertz squarewave. The output stage Q9 of the bit counter. Nominally a 300 hertz squarewave. The ANDed combination of bit counts 1, 2, and 4. Logic zero signal occurring at the last (8th) bit ime of a frame. A part of the input signal to the BCH register. Generated by exclusive OR of data and parity signals. Signal to the various stages of the BCH register. BCH circulate is equivalent to BCH N during the interval when data is being transmitted, and is a logic O when the BCH word is being transmitted. A logic 1 signal during frame O and the first 4 bit times (0-3) of frame 1, which prevents the BCH register from computing during transmission of the 12 bits of synchronization time. The serial output of information bits 1 through 8 from the data shift register. The information input to the modulator flip-flop. Data Out is the serial ordering of data and parity signals. The inversion of Bit Count 7, that loads bits 1 through 8 into the data shift register P 2-11

39 Signal Name Description cont'd. FRO through FR 6 Out Parity Reset Output Shift Pulse Shift Pulse 2.4 KHz KHz KHz. The logic 1 decoded outputs of the frame counter C!. FRO (frame 0) is the first frame. These signals drive the switch matrix to produce data bits 1 through 8. The complementary phase modulated 78.6 KHz. signals out of the modulator that drives the power switching amplifier. The output of the BCH register. A logic 1 pulse at the beginning of each message that resets the bit and frame counters. The shift signal into the modulator flip-flop. This signal is coincident with shift pulse, - except during frame 0, when it is a constant logic O. The 2.4 KHz. squarewave output of stage Q6 of counter C2. The logic 1 going edge of this pulse occurs exactly in the middle of each bit time and shifts the data through the various registers. The output of the first stage of counter C2 used as the transmitted modulation signal. The input clock signal received from the wayside. 6042, p. 2-12

40 SECTON WAYSDE EQUPMENT 3.1 GENERAL The AV wayside equipment consists of three component assemblies that generate a signal source to inductively power the carborne equipment, and receive and decode the message transmitted from the vehicle. These three assemblies are: 1. An nterrogator that contains electronic components to generate the signal that inductively powers the carborne equipment and to receive, separate, and amplify the return message signal and couple it to decoding equipmen. 2. A Wayside Coil that provides for an inductive transmission path to and from the carborne Transponder qoil. 3. A Decoder Logic Unit that receives the return message signal from the nterrogator and demodulates, decodes, checks and outputs the message data to external equipment. n addition, a fixed thirty foot length of direct burial cable is provided by WABCO to interconnect items 1 and 2. A suitable length of 135 ohm twisted pair, shielded signal cable, is required to interconnect items. and 3. These units constitute a complete wayside location. The Wayside Coil is mounted between the running rails. The nterrogator is mounted in a wayside case along the right of way within 30 ft. of the Wayside Coil. The Decoder Logic Unit is normally mounted in a standard 19 inch-equipment rack in a nearby equipment room that may be located up to 5000 ft. from the nterrogator. The Wayside Coil and nterrogator are activated at all times. The Decoder Logic Unit is powered at all times, but will only decode data when enabled by an external track circuit input. 3.2 DESCRPTON nterrogator (N ) (Refer to Figure 3-1) The nterrogator unit is an electronic amplifier consisting of two electronic printed circuit boards, power supply components and power output transistors, all mounted on an 11" x 14" aluminum chassis panel. Power and signal connections are made to the nterrogator via 2 MS style connectors. A 16" x 21" x 11-3/4" wayside mounting case includes cabling from mating MS cable connectors which terminate on standard 6042, p. 3-1

41 ...J..:. 1 Figure 3-1. AV nterrogator Without Cover , p

42 AAR terminals. Threaded studs provide convenient means of mounting the nterrogator panel inside the wayside case and the cable connections permit easy installation and removal without disturbing external connections. The transmitter electronics in the nterrogator consists of a crystal controlled KHz.oscillator and power amplifier stages that drive the Wayside Coil. Capacitors installed in the nterrogator provide a means of tuning the Wayside Coil to provide maximum power transfer to the coil. The return signal electronics consists'of filters to separate the returned message information from the transmitted signal and a 135 ohm balanced line driver, capable of driving up to 5000 ft. of cable, to deliver the return signal to the Decoder Logic Unit. The nterrogator power supply is transformer coupled to permit operation from either 115 or 230 Volts AC depending upon application requirements. The nterrogator AC input is controlled locally by an ON-OFF switch and fused at 3 amperes _to. prtect 8:gc3:inst overloads nterrogator Technical Data Specifications Physical including wayside case N Dimensions Complete Unit: W = 15.5"; L = 22"; H = 8" Weight, Complete Unit: 90 lb./40.9 Kg. including case Electrical.. nput Voltage Power Consumption(Max.): Frequency Range: Temperature Range: Frequency Stability: R.F. Power Output: Spurious and Harmonics: Modulation: 120/220 VAC/60 Hz. 120 watts 153,600 ±15 Hz. over temperature range -4o 0 c to +7o 0 c (-40 F to +160 F) ±.0097% of assigned frequency Oto 116 watts {adjustable) -16 db Afl continuous 6042, p. 3-3

43 3.22 Wayside Coil (J ) The Wayside Coil is composed of 3 turns of 14 AWG stranded wire in a loop 42" x 14" that is encapsulated in a molded fiberglass assembly 48" x x l" to withstand normal roadbed environment. The assembly is provided with 4 mounting holes to permit installation to the ties between the running rails. A 3 ft. lead-in is provided for attachment to the direct burial cable to the nterrogator Decoder Logic Unit (N )(Refer to Figure 3-2) The Decoder Logic Unit consists of a receiver, interface board, decoder panel and power supply, mounted in a 19" wide x 12" deep, x 3" high drawer equipped with slide mounts to fit a standard 19" enclosure. Signal connections and power inputs are provided by two 37 pin "D style" connectors and a MS Connector. The connectors and slide mounting feature provides a convenient means of installation and removal when required without disturbing internal rock wiring. The decoder power supply is transformer coupled to operate from a 115 volt 60 cycle line. An On-OFF switch and AC line fuse (\ amp) are conveniently located on the front panel of the unit. Three types of Decoder Logic Units are available, depending upon application requirements. 1. Decoder N (Basic) 2. Decoder wi.th Routa..Buffer N S l Decoder with ASC nterface N Decoder Logic Unit (Basic) The basic decoder receives and demodulates the signal returned from the carborne equipment via the nterrogator, and decodes and checks the message for validity while the carborne Transponder Coil is over the Wayside Coil. The complete decoder message is re-transmitted in a binary format, after the input signal disappears, indicating that the vehicle has passed. This serial output is provided as an EA RS232C level interface via optical couplers at selectable bits rates from 150 thru 2400 bits per second. The basic decoder also provides a relay contact output indicating the state of the cab status bit received from the carborne equipment. The Decoder requires a voltage input to monitor the track 7 ircit associated with the Wayside Coil location. Decoder operation is enabled only when the track circuit is occupied. 6042, p. 3-4

44 "P.' ' ;. v..... " -\. " al.. i- ;.,,.,,. Figure 3-2. Decoder/Logic Unit Cover Removed 6042, p. 3-5

45 Decoder Logic Unit (Route Buffer} The decoder with Route Buffer consists of a basic decoder with an optional route interface that provides a decoded output of the 20 possible route numbers (1-20) programmed in the carcarried equipment. A route number is decoded and outputted over an individual contact for each route from the first message received after the track circuit is occupied Decoder Logic Unit (ASC nterface) The decoder with ASC nterface consists of a basic decoder with an optional ASC compatible communication interface. This serial ASC output is available in two forms, an optically isolated EA RS232-C interface and an optically isolqted 20 or 60 milliampere current loop compatible with standard teletypes. Selectable data rates from 75 to 9600 bits/ second are available, along with formats for hardcopy printouts. The optional Route Buffer and ASC nterface physically mount in the same location in the decoder drawer. Either output option, but not both, is available in a given decoder drawer. 3.3 THEORY OF OPERATON (Basic) The nterrogator generates a KHz. sinusoidal signal with a crystal controlled oscillator that is power amplified to feed approximately 100 watts of energy into the Wayside Coil. Fixed and variable tuning capacitors in the nterrogator are used to resonate the Wyside Coil at KHz.to provide maximum energy transfer to the coil. Variable gain adjustment on the nterrogator amplifier allows signal level adjustment. Nominal level is 200 Volts AC RMS output to the coil. Test points incorporating a rectifier and 10 to 1 voltage divider, permit reading the AC output level on a DC meter at 1/10 scale (20 volts DC= 200 VAC RMS). The electric field present in the Wayside Coil induces energy at KHz. into the carborne AV Transponder Coil whenever the carborne coil is over the Wayside Coil. The carborne equipment generates a message and transmits back to the wayside using a phase shift keyed 76.8 KHz.carrier. The carrier is inductively coupled to the Wayside Coil and fed back into the nterrogator via the same coil which transmits the KHz. signal. At the nte.rrogator, the KHz. return signal is separated from the KHz.signal, filtered and amplified. The amplifier output is tra..!lsformer cpled J:o _ the oecoder Logic unit over 135 ohm twisted pair cable. The amplifier gain is adjustable to drive up to 5000 feet of cable. 6042, p. 3-6

46 A receiver printed circuit board, located in the decoder logic drawer, filters, detects, and demodulates the 76.8 KH carrier to recover the phase shift keyed data. This phase shift keyed data signal and a carrier detect signal are routed to the Decoder Logic Panel. The Decoder Logic Unit converts the serial phase encoded data into a binary data signal, stores and checks the data for content and format. Three tests are performed on incoming data to insure validity. These checks are: 1. sync detection 2. zero string detection 3. BCH check The incoming message is checked for a sync word (1010 bit pattern} that must occur at the beginning of a message. Failure to detect the sync word results in a sync error. The data is also checked to insure that no more than 8 successive logic "0" bits are present in the message. Otherwise an excess zero string error is generated. A BCH check word is generated from the incoming data bits and compared to the check word contained at the end of a message. f the words compare, the data is valid. Otherwise a BCH error is generated. f the incoming.data message is received without error, the logic unit is inhibited and the valid data is stored in a shift register until the vehicle passes. When the 76.8 KHz. carrier is no longer received and detected, a good message indication is stored and the data.in the shift register is outputted. f either a sync, excess zero or BCH error occurs because of improper data, the logic unit is reset and it begins to again scan the incoming data. This process may be repeated continually as long as data is being received. f a valid message is not received and the incoming data signal is removed, an error message indication is stored. A special error message format is outputted in this event. While either the valid good message data, or the special error message is being outputted, the logic unit is.prevented from receiving another message input. After the last data bit has been outputted, the logic unit is enabled to receive further data. The logic unit is enabled only while the track occupancy input is activated. When the track circuit is unoccupied, no data is processed or outputted by the Decoder Logic Unit, regardless of carrier inputs. 6042, p. 3-7

47 3.4 NTERROGATOR Theory of Operation (Detailed) The Amplifier PCB N and the Control PCB N are the two printed circuit boards in the AV nterrogator Unit. Figure 6-9 and 6-11 are the schematic diagrams of these boards and Figure 6-13 provides a diagram of their connection into the system. The Amplifier PCB is powered by 36 voe applied to the plus and minus Fasten terminals on the board. Light emitting diode LD2 provides visual indication when power is applied to the board. Transistors Ql and Q2, along with resistors R2-R7 and capacitors C2-C4 form an oscillator circuit. The frequency of oscillation (153.6 KHz) is determined by crystal CRl. Capacitor C3 provides for frequency adjustment and is factory set to the frequency stamped on crystal CRl. Zener diode Dl provides a 20 volt voltage level for the oscillator's power. Transistor Q3 is an emitter follower stage. Ferrite beads L8 and L9 on the base lead of Q3 prevent emitter follower oscillation. The output oscillation should be KHz. at TP2. This waveform is a clipped sinewave %12 volts peak-to-peak. The output of the oscillator is capacitively coupled by CS to a pi network composed of LS-L7 and C6 and C7. The pi network suppresses spurious and harmonic frequencies other than the carrier frequency ( KHz}. The 12V peak-to-peak sinewave output of the pi network at TP3 is capacitively coupled by ca through variable resistor R8 to a class "A" amplifier stage. Transistors Q4 and Q9, along with resistors R9-Rl4, R25 and capacitors ClO and C26, make up the components of this class "A" amplifier. The 65 volt peak-to-peak maximum output at TPS is coupled by transformer Tl to form a push/pull output drive to the bases of the 2NS039 output transistors. Note: The 2N5039 transistors are mounted on heat sinks attached to the aluminum panel of the nterrogator Unit. Connection to the bases of the output transistors is made at Fasten terminals Al and A2, while Fasten terminal Gl is connected to ground. The collectors of the output transistors are connected to Faston terminals Bl and B3, with Fasten terminal B2 connected to+ volts. The collectors drive transformer T2. The amount of output drive is controlled by R8 and must be set to provide an output of 200 volts RMS to the Wayside Coil (TP8 to TPlO}. The output coil and tuning network is connected to the secondary of T2 at Fasten terminals Cl and C2, with the shield connected to terminal Sl. The tuning network and output connector are mounted on the Control PCB N Also connected to the secondary of T2 is a KHz. trap, consisting of variable inductor Ll and capacitors Cl7 and C27. The trap removes the KHz. output signal, allowing tuned circuit L2 and Cl8 to recover the return data signal at KHz. ( KHz/2). The 2 volt peak-to-peak signal at TP12 is capacitively coupled by Cl2 through variable resistor Rl8 to a class "A" line driver stage. Transistors Q7 and Q8, along with 6042, p. 3-8

48 resistors Rl9-24 and capacitors Cl3 and C25, make up the class "A" line driver stage. Resistor Rl8 provides adjustment of the output level of the line driver. The output signal at TP15 (12V P-P at -10 db maximum) is transformer coupled by T3 to form a balanced line output at Faston terminals Dl, D2 and S2. Light emitting diode LDl provides visual indication of the presence of an output.signal. Diode 02, a 47 volt zener diode, protects output transistor Q8 from any line surges. 3.5 DECODER LOGC UNT The following section includes descriptions of the hardware in the Decoder Logic Unit. 1. Receiver PCB N Decoder Logic Panel N Power: Distribution and nterface PCB N Receiver PCB N Description The AV decjder drawer receiver printed circuit board has two functions. First, it generates a clock for the decoder. Second, the receiver demodulates the input signal from the nterrogator to recover the phase encoded data and provide a carrier detect. A block diagram of the Receiver is shown in Figure Theory of Operation (Refer to Figure 6-16).. Clock A KHz. clock frequency is generated by utilizing one section of C6 as the active element to excite the crystal, XTAL 1. Frequency adjustment is achieved by means of c29. Note: C20 has been adjusted at the factory for precise frequency calibration. The oscillations at the output of C6 are buffered by Q6, then outputted to pin 13 (clock output). This reference frequency is present when power is applied to the board. Demodulator and Carrier Detect The board receives phase shift keyed modulated data from the nterrogator via pins 1 and 2. The carrier frequency is 76.8 KHz. After passing through an isolation transformer, Tl, the signal crosses a switch, Sl (normal position), to a matching pad. The signal passes through a three pole Butterworth band pass filter. 6042, p. 3-9

49 The filter removes any KHz. signal and passes only the 76.8 KHz. signal. At the output of the filter, the signal is similar to the one transmitted by the car-carried equipment. This signal contains phase changes at the times when the signal level approaches zero. The sensitivity of the receiver is adjusted by resistor R4 and the signal is applied to an amplifier. Two sections of Cl form the two stage amplifier. The output of the amplifier goes to two places. First it is supplied to the demodulator and phase locked loop, and second, the signal is supplied to the carrier detect circuitry. The 76.8 KHz. signal excites a synchronous oscillator, Q4, that produces a constant phase/frequency clock signal (153.6 KHz.) for the phase locked loop. The phase locked loop, C4, will "lock" on to the incoming signal. The output of the phase locked loop is divided down to 76.8 KHz. by C5. This constant phase signal then turns oh and off the analog switch in one section of C3. The switch is used to change the gain of the amplifier in the third section of Cl from a gain of one to a gain of zero. This amplifier switches the gain at a constant phase and frequency, (76.8 KHz.), regardless of the phase of the input signal.and produces a signal in which only half of each cycle is passed. Depending on the phase, it passes the positive half or the negative half of the data signal. Since the input is changing phase, the output of this stage is alternating groups of positive half cycles or negative half cycles. This phase detected data is applied to C2, a window detector, that produces a constant level for a series of half waves. Thus one has a positive level for one phase and a zero level for the other phase. The phase encoded data is then buffered by Ql and outputted at pin 14. The carrier detector indicates when data is being received. The system uses this signal to enable decoder circuits. The phase shift keyed modulated data from the amplifier (Cl) is amplified by C6 and rectified by diode D4. Capacitor C15 filters the signal and a DC level is applied to level detector C7. A turn-off delay is provided in the carrier detect circuit to assure the "capture" of the last bit. This delay.. is accomplished by applying a DC level to C7 through transistor Q3 and the discharge of Cl5 through resistors R36 and R31. This level (thus the delay time) is adjustable by R35. The carrier detect is buffered by Q2 and outputted by pin 15. Power Supply Decoupling TWC power supply voltages, +12 VDC unregulated, and +12 VDC regulated, are applied to pins 16 and 17, with pin 18 utilized as a common reference for both. The unregulated 12 VDC from pin 16 is applied to the junction of R38, C26 and the cathode of a 1N4001 reverse polarity protection diode. This is designed as point +Vin the power supply decoupling networks. Two other decoupled +12 VDC voltages, labeled "A" and "B" are taken from the junction of R30, Cl6 and R40, C17. At point "C", there is a 10 VDC source that is regulated and filtered by D9 and 6042, ':' 3-10

50 Test Circuits Switch Sl is a double pole, three-position rotary switch located on the Receiver PCB, which selects the various modes of operation as follows: Position When will will Test Decoder Normal Operation Test Receiver Switch Sl is placed in either test position 1 or 3, LED 1 light to indicate the switch is in the test mode. LED 1 be dark in the normal mode of operation (Position 2). When Sl is placed in the "test decoder" position, the following circuit functions will be placed.into operation: 1. LED 1 will light. 2. Pin 5 will be connected to the O volt (ground) reference. 3. Any signal coming from the input (pin 1 and pin 2), will be disconnected from the input matching pad Rl, R2, and R3. - When Sl is placed in the "test receiver" position, the following circuit functions will be placed into operation: 1. LED 1 will light. 2. Pin 7 will be connected to the O volt (ground) reference. 3. The input matching pad, Rl, R2, and R3, is connected to the junction of R42 and R43 and the circuit composed of QS, Cl9, and R4 1. This circuit receives KHz. phase modulated test data from the Decoder Logic Panel and converts it to a -28 DBM test signal. This signal then passes through the receiver and carrier detect channels where it is demodulated and fed back to the decoder as a test input. When Sl is in the "normal" position: 1. LED 1 is dark. 2. Pin 8 is at the O volt (ground) reference. 3. Received data enters the normal signal processing channels. 6042, p. 3-11

51 m 0 N... "O. w,... N 9 l 2 N Test NPUT p Signal BUFFER... u... T,, Modulated SELECTOR N Data AND p MATCHNG... u T.. T CLOCK OUTPUT 0 OSCLLATOR BUFFER u 13 Clock rjj1"" p KHz. u T 76.8 KHz. 2 STAGE 3 POLE... AMPLFER... FLTER... SENSTVTY ADJUST... TEST MODES g 15 T 7 p 8 u T.,,,,..,... PHASE DETECTOR... OUTPUT WNDOW BUFFER Data u... T 14 DETECTOR... p u T Q -.. FREQUENCY DOUBLER PHASE LOCKED LOOP - _.:_ 2... LEVEL DE?ECTOR AND.. DELAY... AMPLFER RECTFER Figure 3-3. Receiver Block Diagram OUTPUT BUFFER 0 Carrier: U Detect T 15 p u T

52 3.5.2 Decoder Logic Panel N l Description The Decoder Logic Panel is constructed from CMOS integrated circuits on a 60 position wire wrap socket assembly and is housed as part of the decoder logic drawer. This unit accepts phase shift keyed data from the Receiver PCB N , decodes and checks the data, and oupus the valid data word whenever input data is no longer received. The track circuit associated with the Wayside Coil is also monitored to detect occupancy. Data is tput:!:_in wq_;9_rmslparallel and serial. Tp.e parallel outputs provide a logic level output (logic "0" = O volts, logic "!"= +12 volts de) for use in the Route or ASC nterface Panels (N or 0204). The serial output is buffered by optica.l isolators on the Power Distribution and nterface Board N to provide compatibility with standard EA RS232-C data interfaces. This serial message output from the Decoder Logic Panel is 48 bits; 8 zeroes followed by a 4 bit sync code(alternate 1 and zero bits), 28 bits of data, a single fixed logic 1 bit, and a 7 bit BCH Check Code The Decoder Logic Panel also incorporates a test pattern generator and 6 LED indicators to display internal operating status. These LED' s are:. 1. Good Message 2. Error Message 3. Track {occupied} 4. Key-on 5. Carrier Detect 6. Cab Signal The Good Mssage LED indicates that the last message received and outputted by the decoder was a valid or good message. The - Error Hessage LED indicates that the last message was received in error. The Track LED indicates that the track circuit which the decoder unit is monitoring, is occupied. The Key-on LED indicates that a data set enable {or Key-on) output is activated and supplied to external data carrier equipment. This occurs whenever the track circuit is occupied, provided the test pattern mode is not activated. The Carrier Detect LED indicates the presence of a carrier output from the receiver, detecting the presence of a ransponder Coil over the Wayside Coil. The Cab Signal LED indicates that the cab signal bit {Data bit 26) is present (logic 1) in the message received from the lead car (first message received after occupancy). The test pattern generator circulates a test message through the logic unit for self check of the logic. This generator is 6042, p. 3-13

53 controlled by a three position rotary switch located on the receiver printed circuit board. The three switch positions are: 1. T-DCOD (test decoder) 2. NORM (normal) 3. T-RCVR (test receiver) With this switch in the test decoder position, an alternating valid and then invalid phase shift encoded message is connected to the decoder logic input. f the decoder is operating properly, the Good and Error.Message LED's will be alternately lit. The test mode simulates a track occupancy, causing the Track LED to light and disables the Key-on and cab signal logic. When the switch is placed in the test receiver mode, the test phase shift encoded message is modulated by a 76;8 KHz. signal and. fed into the receiver card. The output of the receiver is fed, as normally, into the logic panel. Good and Error Message LEDs will light alternately and both the Track circuit and Carrier Detect LED's will be lit. The Key-on and Cab Signal LED's are disabled. The valid or good test pattern message is also outputted from the test generator whenever the Error Message is lit in normal operation. This special message is interpreted by other receiving equipment to indicate data received in error. n the normal position- -the test generator is disconnected from the inputs to the decoder or receiver and data inputs are provide from the Receiver PCB Basic Theory of Operation The basic functions of the Decoder Logic Panel are shown in the block diagram Figure 3-4. The operation of this unit is essentially controlled by the track circuit and carrier detect signals. The Decoder Logic Panel is enabled when the track circuit is occupied, at which time, reset signals are removed from the good and error message flip-flops and the output timing logic, and a Key-on signal is generated. The input timing logic remains disabled until a carrier detect input is received, while the output logic is not enabled until after a message has been received. When the track circuit and carrier detect inputs are both present, the input timing logic is enabled and the phase shift key to binary decoder begins decoding the data input into binary. nitially the decoded data is a string of 8 logic zeroes in the first portion of the start or sync code. When the first logic 1 bit is received, after these 8 zeroes, the sync detection logic is enabled and the input data is examined for a 4 bit string of alternate ones and zeroes, the 1010 sync 6042, p. 3-14

54 pattern. f the sync pattern is received correctly, the timing logic generates shift pulses to store the remaining data bits in a 36 stage shift register. As the serial data is received, decoded and stored in the shift register, a bit counter is enabled and updated to record the number of data bits received. After twenty-nine data bits have been received, a BCH check circuit is enabled to check the next seven data bits received against a seven bit check word internally generated in the decoder logic. f the seven BCH data bits are received and compared correctly, the input timing logic is halted after the last data bit has been received. The shift pulses are inhibited and the shift register contains 36 valid data bits. The bit counter is disabled at the beginning of the 36th bit count. No further input data is accepted and the logic remains in this halted state until the carrier detect input is removed and the data is outputted. At that time, the absence of carrier and the decoded count 36 from the bit counter set the good message flip-flop. The valid data is nqw available for output from the shift register However, if the message does not begin with the proper sync pattern format, or a string of more than eight logic zero bits appears in the data, or the BCH data bits do not compare with the calculated BCH check word, an error exists in the incoming data. Whenever a sync error, zero string error, or BCH error occurs, the timing logic and phase shift decoder are disabled and the bit counter and shift register are reset. The logic is again enabled when the next logic 1 bit is received and decoded. f sufficient errors occur so that a valid message can never be decoded by the logic from the incoming data, an error message flip-flop is set when the carrier detect input is removed, and a special format error message from the test message register is made available for output. When the carrier input is removed and the good message flip-flop is set, a good message strobe pulse is generated, to indicate that valid data is available from the parallel outputs of the shift register. The data bits representing the route and car number are outputted as 6 parallel complement binary coded decimal digits. The four status indications bits are outputted in true binary format. The cab signal flip-flop is set at this time only if the cab signal indication (data bit 26) is set and the valid data is from the first message received since track occupancy. 6042, p. 3-15

55 At the end of the strobe pulse, the transmit flip-flop is set and the output timing logic is enabled. The timing logic loads a sync code into the output data register and generates a shift pulse to output the data. Valid data is serially shifted out through the data output register after.the sync code. A counter, updated by the output shift pulse, keeps track of the number of bits outputted. After the 48th and last bit is outputted, an end transmission signal is generated by this counter. This "end X" pulse resets the transmit flip-flop and generates a reset to the input timing logic, enabling the input logic to accept another message when it occurs. The output data bit rate is jumper selectable from 150 to 2400 bits per second, dependent upon system application. The rate is selected to insure that the message is outputted before the next carborne transponder signal is inputted. f an error message occurs, and the error flip-flop is set rather than the good message flip-flop, an error message strobe is generated to indicate an invalid message was received. A special error message consisting of non BCD characters (1101) as the 6 digits and 4 zeroes for the status bits is transmitted along with the correct BCH check code for that message. Receiving equipment must decode this message as an error indication. Output timing is otherwise the same as for a valid good message. After the special error message is outputted, the transmit flip-flop and input timing logic are reset and the decoder is again enabled to accept another input message. The decoder incorporates a "power on" detection circuit to reset the decoder when power is first applied. Test Mode - Decoder f the test mode is activated from the test switch on the receiver printed circu.it board, the test message is circulated through the logic to check operation. There are two modes: test decoder and test receiver. n the test decoder mode, the serial data output from the test and output registers is phase shift encoded and fed into the data input of the phase shift to binary logic. The normal data input from the receiver board is disabled at this time. The test logic generates a test track occupancy signal to enable the logic unit, and a simulated carrier detect input is produced to activate the input timing logic, while test data is being recirculated from the test circuit through the logic. The decoder input and output logic function normally. However, the key-on output is disabled to prevent data transmission of test data out of the logic unit to external terminal devices. The good and error message detection circuitry is checked by changing the 21st data bit in the test message from 1 to O every other messase. This causea a BCH error every-other message generating the error condition. The LED indicators on the decoder panel will show the track circuit LED lit and the good and error messages alternately flashing on and off. 6042;,p

56 28 BT PARALLEL DATA..,. PSK DATA... r PSK TO BNARY 36 BT DATA r DECODER SHFT --., REGSTER... FRST MESSAGE LOGC BT CAB... SGNAL CAB.. r 26 F/F 0:, H - CRCUT,, RESET.,j'"...! SYNC!-<: SERAL DATA DETECT ZERO STRNG DETECT 1,3 :i- 'r DATA OUTPUT REGSTER SERAL... r DATA OUTPUT BCH. CHECK i, GOOD.-?-mSSAGE F/F 0\ 0.i:,. V... RESET CARRER DETECT TP.ACK CRCUT... r! NPUT SHFT PULSE BT! TUNG l1essage COUNTER "' LOGC... TRAK TRACK KEY ERROR F/F J: OUTPUT CRCUT L-4 TMNG NTERFACE OU LOGC r--, 8... H TEST & ERROR 1-J 11ESSAGE TEST REGSTER DATA... ' J,.,. TRAUS- TEST. MT TEST r LOGC,... F/F NPUT "O w J Figure 3-4 Decoder Logic Panel Block Diagram

57 The test receiver mode operates in a similiar fashion, with the exception that the phase encoded test data modulates a 76.8 KHz squarewave that is fed into the input of the receiver. The receiver outputs feed the decoder logic as in the normal operating mode. The simulated track occupancy is still maintained. The simulated carrier detect signal is not required,as the receiver outputs are used. The Key-on output is again disabled to prevent transmission of the test data. The LED indicators on the decoder panel will indicate track occupancy. The Good and Error message LED's will alternately flash on then off,.with the Carrier Detect LED lighting when the Good and Error Message LED's are both off Detailed Theory of Operation The AV Decoder Logic Panel N receives control signals and data from the AV Receiver PCB N and the Power Distribution and nterface PCB N Phase shift keyed data (RCV data) and other control signals from the receiver enters the Decoder Logic Panel through a dual in-line connector at location Bl. n addition to data, the basic control signals received by the Decoder Logic Panel are: TR,CXRDET, NORM, TEST DEC, TEST REC and KHz. clock. TR is the TRACK signal from the Power Distribution and nterface PCB. t is a logic O level whenever the track circuit activating the AV decoder is occupied. CXR DET is a logic 1 signal generated by the receiver whenever the carrier signal from a Transponder Coil is present from a Wayside Coil and nterrogator. NORM is a logic O signal generated by the receiver, indicating that the Test Switch Sl on the receiver is set in the normal (NORM) operating position. TEST DEC is a logic O signal generated by the receiver whenever receiver PCB Test Switch Sl on the Receiver PCB is placed in position 1 (Test Decoder position). n this mode the RCV DATA and CXR DET signal inputs from the receiver are inhibited and a test message is circulated through the decoder panel to check its circuitry. TEST REC is a logic O signal generated by the receiver whenever receiver PCB Test Switch Sl is placed in position 3 (Test Receiver position}. n this mode, a modulated phase shift encoded test message, generated by the decoder, is fed to the input of the receiver PCB to check its operation. The CXR DET and RCV DATA signals from the receiver remain active to the decoder 6042, p. 3-18

58 The KHz. clock is generated by the receiver PCB and used by the decoder to develop timing pulses to control data flow. The decoder panel generates three clock signals from the KHz. clock to control its input timing logic. They are: Q6-CL, BCl, and Delay Clock (B24 pin 9). The 2.4 KHz Q6-CL signal is free running and directly controls the delay clock which is a logic O pulse with each positive transition occurring approximately 2µs after the positive transition of the Q6-CL signal. The timing of Q6-CL (and delay clock pulse) is controlled such that the positive edge of Q6-CL occurs in the middle of each data bit, assuring that the data is stable when clocked, thus preventing problems due to transitions and propagation. BC! is a clock produced by the bit counter Al8 only after the incoming message data has been correctly checked for the proper sync word. ts function is to load data into the main data register of the decoder. BCl is the inverse of Q6-CL when generated. When DC power is first applied to the Decoder Logic Panel, a master reset signal (MSTR) is momentarily applied to registers in the logic to establish initial conditions, preventing false operation. An RC timing circuit (4.7 µfd capacitor and 22K resistor bypassed by a diode) located on component mount Al3, begins to charge when power is applied, producing a logic 1 MSTR at A12 pin 12 and a logic O MSTR at Al2 pin 15 until the capacitor is charged. Operation of the decoder logic is enabled only when the track circuit associated with the AV unit is enabled. A logic O TR signal (BJl-9) from the track circuit interface on the Power Supply and Distribution PCB is fed through an inverter to the Track Flip-Flop B9, generating a logic 1 TRAK signal when the clock input (4.8 KHz.) to that flip-flop goes positive. The TRAK signal removes the reset from the Good Message and Error Message FF's (B6 pin 4 and 12) through NANO gate Bl3 pin 4. The TRACK LED is lit through inverter BS pin 2. The logic O level TRAK signal at B9 pin 14 also removes the reset from the Cab Signal FF (B9 pin 4) and the 1st Message FF (B7 pin 4). f the receiver Test Switch Sl is in the Normal position, a logic O NORM signal at BlS pin 9 is inverted and along with the TRAK signal generates a logic Oat A30 pin 13. This signal is inverted to produce a logic 1 KEY signal at BJl-11 to activate an optional external data set and also to light a KEY ON indication LED via Al2 pin , p. 3-19

59 NPUT LOGC AND SYNC DETECTON OPERATON (See Timing Chart Figur With the track circuit previously occupied, the-- decoder's input timing logic is enabled with presence of a logic 1 CXR DET signal from the receiver PCB (Bl pin 6) whenever a carborne transponder is over the Wayside Coil. The output of inverter A20 pin 2 goes low, which lights the CXR DET LED. The CXR DET and TRAK signals drive NANO gate output A25 pin 13 high, which removes the reset from single shots Al4 pin 3 and pin 13. This signal is also inverted at A20 pin 6, generating a logic O CD TRAK SMCO signal which removes the reset from 7 stage binary counter A21 pin 2 and re-establishes the reset to the Good and Error Message FF's B6. Single shots Al4 begin to "look" for any change in data in the ROD signal (data from the receiver) fed through bilateral switch A23 pin 11. When a change in data occurs (transition from a logic 1 to a O or vice versa) one of the single shots of C A14 will fire, generating a 2µs logic one pulse at NANO gate B20 pin 4. This START pulse."is inverted at NAND gate B20 pin 3 to momentarily reset the counter Al9 at pin 2 and the DELAY CLOCK at B24 pin 13 to sync the decoder clocks with incoming data, so that clock transitions occur in the middle of each bit. The negative edge of this 2µs pulse at B20 pin 4 now sets the ON FF Bl8 pin 15 which removes the reset from the Phase FF at AlO pin 12. On the next low to high transition of the DELAY CLOCK at B24 pin 9, the Enable Data FF at Bl8 pin 1 is set. With the Enable Data FF set, the set on the Data FF (AlO pin 7) is removed and resets are removed from the sync detection logic C's A7 and A8. The phase flip-flop is reset and the data flip-flop is set when the first data transition occurs. f this first transition is from a logic O level to a positive level, the following sequence of events occur: (refe to timing chart Figure 6-21). The logic 1 ROD signal is "exclusive ored" with the logic O phase FF signal to produce a logic 1 Data input (Al0-6) to the data FF. When the first Q6-CL and delay clocks occur a half bit time later, the logic 1 ROD signal causes the phase FF to set, and the enable data flip-flop is also set. Since the phase FF and ROD are both positive, the exclusive ored data input signal goes to a logic O, but only after the delay clock occurred, so the data flip-flop does not change state. On the next delay clock, the data flip-flop is reset, but phase and ROD remain positive. Note in phase encoded format the presence of a logic 1 bit is indicatd by a change in phase or level from a O volt to positive or from a positive to zero level. No change for more than 1 bit time indicates the following bits are logic O. Since ROD was positive for 2 cycles of the delay clock, this will be interpreted as a logic 1 followed by a logic Oat the output of the data flip-flop. 6042, p. 3-20

60 The ROD signal must change phase before the third delay clock is produced if the correct sync word is present in the incoming phase encoded data signal. When ROD goes to OV, the exclusive ored ROD signal and positive phase FF output will again produce a logic 1 data input of AlO pin 6. On the third delay clock, the data flip-flop will be set since data input AlO pin 6 is a logic 1, and the phase FF.will be reset since ROD is O volts. The third data bit is a logic 1. mmediately after the third delay clock occurs, the data input signal (AlO pin 6} goes to a logic O since both ROD and phase are at O volt. f ROD stays at zero volts until the 4th delay clock, the data input will remain a logic zero, causing the data flip-flop to reset to a logic zero, when the 4th delay clock pulse occurs. The fourth data bit is a logic O. This process is continued for the remaining data in the message until all data bits are decoded. The ROD input may be of any phase initially without affecting operation, with the exception of the first transition and bit time. f the first transition of ROD is from a positive voltage to O volts, the data input signal AlO pin 6 is a logic O since the phase flip-flop is initially reset. This would cause the data flip-flop to be reset to a logic zero, from its present condition, on the first clock after the transition of ROD. However, the preset input to the data FF is not removed until after the enabled data FF Bl8 pin 1 is set on the positive trailing edge of the first delay clock, prevening the clock input to the data FF from clocking the flip-flop at that instant. So the data flip-flop remains set for the first bit. Note that this preset signal from the enable data flip-flop has no effect on the data flip-flop for the opposite initial phase change in ROD. When ROD goes from a O volt to positive voltage initially, the data input signal at AlO pin 6 is a logic 1 before the first delay clock pulse would occur. When the enable data flip-flop is set on the first delay clock pulse after the initial received data transition, the sync check logic is enabled by removing the reset to flip-flops A7 and A8. The sync logic looks for the 1010 sync code during the first four bit times of the message. Sync is checked by comparing the,_ output of the data flip-flop AlO pin 1 with the complement output of the sync counter FF A7 pin 2. This comparison is done in exclusive or gate A9 pin 4 and fed to the sync error flip-flop A8. Since both the sync error flip-flop A8 and the sync counter A7 are held reset and the data flip-flop is held preset until after the first delay clock pulse occurs, no sync errors can occur on the first data bit. The sync counter is clocked by the positive transition of Q6-CL. So on the second positive 6042, p. 3-21

61 transition of Q6-CL, the sync check signal (A7 pin 2) goes to a logic O. f the input data contains the correct sync bits, the data flip-flop will be reset on the positive edge of the delay clock immediately after the second positive transition of Q6-CL. The exclusive or of Data and Sync check causes the sync error input A9 pin 4 to go to a logic O. Since the sync error flip-flop AS is clocked by the inverse of Q6-CL, the error is not checked for another bit time. Since the input is a logic 0, the sync error flip-flop cannot set when clocked, so it remains reset. The Data FF will be reset on the next delay clock during the DATA signal. On the next (third) positive edge of the Q6-CL, the 1st stage Sync Check FF is reset, which sets the 2nd stage FF (A7 pin 15). The Sync ERROR NPUT is driven high, but if the correct sync word is present within the message, the Data FF will be set on the next positive edge of the DELAY CLOCK 2 µslater. The SYNC ERROR NPUT will go low before the Sync Error FF is clocked. This process continues during the next Q6-CL cycle. The Sync Error FF must remain reset during the complete sync word. Setting of the flip-flop will result in a sync error and a complete reset of the decoder's input timing logic. For no sync errors to occur, the binary sync word at the Data FF must consist of a 4 bit binary string of alterate logic l's and O's {1010). f the correct sync word has been received, the 4th Q6-CL pulse since the Enable Data FF was set will reset the 1st and 2nd stage SYNC CHECK FF's and set the 3rd stage, driving the RESET signal from A8 pin 14 low. RESET low disables the 1st stage Sync Check FF at A7 pins 5 and 6 from counting further, and holds the Sync Error FF reset through NAND gate B20 pin 15. Sync error check is now completed correctly and DATA is ready to be shifted into the decoder shift register. Data nput {Refer to Timing Chart Figure 6-22). When the Reset signal goes to a logic 0, terminating the sync check, Bit counter Al8 is enabled to cqunt the data bits and produce a BCl clock signal (2.4 KHz. squarewave) (A18 pin 14) at the middle of each Bit time to shift data into the shift registers BS, Al, A2 and of B22. Resets are also removed from these data shift registers and the BCH check flip-flop A6. Data is fed from the Data flip-flop AlO pin 1 to the shift register input BS pin 7, and clocked into the shift register on the positive edge of the clock signal at Gate Bl3 pin 12, which is the inverse of clock BCl. Since BCl is 180b out of phase with Q6-CL, the inverse of BCl is in phase with Q6-CL. The Data flip-flop is clocked by the clock produced by Q6-CL to insure that data is moved from the 6042, p. 3-22

62 data flip-flop to the data shift register before new data is loaded into the data flip-flop. While data is being inputted to the data register, binary counter Al7, through NANO gate A4 pin 13, checks for excess zeros in the message. The Zero Test Counter Al7 is reset with every change in ROD data by one of the Al4 single shots through NANO gate B20 pin 4, inverter A24 pin 12 and NANO gate All pin 11. f no change in data occurs for nine Q6-CL pulses, indicating 9 zero bits of information, the Zero Test Counter decoded nine output {A4 pin 13) goes low, generating a Zero Test Error to reset the input timing logic of the decoder panel. f no zero test errors are generated, data continues to be shifted into the data shift registers with each trailing edge of the BCl clock. At the 28th bit count, a decoded count 28 signal at NANO gate Al6 output pin 1 goes low. This signal is inverted at Al2 pin 4 and fed into the set input of the BCH Check FF {A6 pin 6). BCl count 28 also resets the Zero Test Counter via NANO gate All pin 2. The next BCl clock pulse {29th) sets the BCH Check FF, driving the BCH CHECK signal to a logic O and enabling the BCH Error FF {B7 pin 12). The decoder now checks the next seven incoming data bits for a BCH error as they are shifted into the data register. When a logic 1 {Parity) signal is present at the BCH Error FF set input {B7_E,!,n 10) from the output of parity generator (B4 pin 9) during a BCl clock pulse, the BCH Error FF is set, generating a BCH error resetting the input logic to the decoder. Parity generators B4 and B9 are cascaded to perform a BCH check on the incoming data bit and the data present in the decoder's data storage registers. The parity generators are wired to the data registers in correspondence to the quotient obtained from the division of two polynomials utilizing only the 36 most significant digits. The dividend has the form of x35, and the divisor is x7 + x6 + x f the-7 BCH check bits in the received message (DATA signal) are correct, the output-at B4 pin 9 will remain low so that the BCH error FF will not be set. This allows the 7 BCH data bits to be shifted uninterrupted into the decoder's data register by the BCl clock. f no errors were generated up to and including the 36th BCl clock pulse, the decoders data register contains a valid message. on the next positive level of BCl, at the middle of the 36 bit count, a Logic O level DATA GOOD signal is generated at NAND gate Al6 pin 15. DATA GOOD inhibits the bit counter (Al8} from further operation through NAND gate A25 pin 3. When A25 pin 3 goes high, the counter stops,holding BCl at a Logic 1 keeping DATA GOOD a Logic o. 6042, p. 3-23

63 No further data is entered into the data register. NAND Gate B20 pin 10 is disabled which prevents the decoder from being reset when the CXR DET signal goes away. DATA GOOD low is also inverted at BS pin 12 and applies a Logic 1 signal to the set input of the Good Message FF (B6 pin 10) to prepare it to be set when the reset signal (caused by Carrier Detect) at B6 pin 12 is removed. The input timing logic of the decoder is now halted, restricting any further data input. The decoder will remain in this halted state until the CXR DET signal is removed (goes to a Logic 0), indicating that a Transponder Coil is no longer directly over a Wayside Coil. On the next cycle of the clock signal, the Good Message flip-flop will be set. DECODER LOGC OUTPUT TMNG FOR A GOOD MESSAGE (See timing chart Figure 6-23). mmediately after the carrier detect (CXR DET) signal at A25 pin 5 goes low, the decoder's output logic is enabled. ThP CD TRAK SM CD signal goes high via NAND gates A25 output pin 4 and 13 and inverter A20 pin 6. The Good Message FF (B6) is enabled and on the next positive edge of the Clock signal at Al9 pin 5, the Good Message FF is set, lighting the Good Message LED. The GOOD MSG signal generates a high GM+ EM signal which places a Logic 1 on the set input (Pin 6) of the First Messge flip-flop (B7). On the next positive transition of the CLOCK signal, the 1st Message FF is set. The 1st Message FF clocks the Cab Signal FF at B9 pin 3 and if the lead car and cab signal bits (Data Bits 25 and 26) are logic l's in the message stored in the data register, the cab signal FF sets. The cab signal LED, via inverter BS pin 6, will light. A Cab signal indication is brought off the decoder at BJl pin 8 to drive the cab signal relay on the Power Distribution and nterface PCB. The Logic 1 GM+ EM signal at B23 pin 3 triggers a 10 millisecond XFER single shot (B28) through NAND gates B23 pin 4 and A27 pin 13. This transfer pulse is applied to NAND gate A4 along with the Good Message signal to generate a Logic O good message strobe GMST for 10 milliseconds at A4 pin 3. This strobe indicates that valid data is available on the 28 data lines from the data shift register. The fixed bit and 7 BCH data check bits are not available on the parallel outputs. The transfer pulse also loads a start code into shift register Bl7 thru the parallel control input Bl7 pin 9. This start code is outputted as a prefix to the serial data when the serial data output is enabled. 6042, p. 3-24

64 The trailing edge of the 10 millisecond transfer pulse fires a 2 microsecond SET XMT single shot (B28). The SET XMT signal (B28 pin 9) sets the transmit flip-flop,driving the Xmit signal at A30 pin 3 to a logic 1. This flip-flop is a simple latch constructed from NANO gates A30 and A28. The Logic 1 XMT signal enables the Data output signal at Bl4 pin 12. The Logic O XMT signal (A28 pin 6) enables the Bit Rate Counter A22 and Bit Counter B25. The proper clock rate is gated thru bilateral switch A23 pin 3 by the high TES'f signal at A23 pin 10, allowing Bit Counter B25 to count the number of data bits outputted. After 4 counts, the CT4 flip-flop A29 is set when B25 pin 4 goes to a Logic 1. The CT4 signal at A29 pin 1 enables the transmit clock (Xmit CL and Xmit CL) through A30 pin 4. Since the transmit clock only begins to occur after four bit times, and the data out was enabled at Bit Count Oby Xmit, the initial output state of shift register Bl7 is gated out for five clock periods, adding 4 additional logic zeroes to the beginning of the output start code. The XMT CL signal begins clocking the start code and data serially through output shift register Bl7 via NANO gate Bl3 pin 12 and bilateral switch Bl2 pin 11. Data from the storage registers is also shifted to the DATA OUT line (Bl4 pin 12) via bilateral switch Bl2 pin 2, shift register Bl7 pin 3, and inverter BS pin 6 by XMT CL. The complete message (start code, data, BCH check bits) leave the decoder from the DATA OUT line via NANO gate A30 pin 12 which is enabled by a logic 1 TEST signal. The DATA and DATA signal outputs (BJl pin 13, and BJl pin 12) are buffered by inverters A24 pin 10, A9 pin 12 and A20 pin 15 to drive optical isolators on the Power Distribution and nterface PCB. The serial data output is selectable at rates of 150 to 2400 bits per second using a jumper in Location AlS. Twelve stage binary counter A22 divides the KHz. clock from the receiver and a jumper in slot AlS selects the appropriate transmission rate as follows: Location AlS - OutEut Freguencx 1 to Bits/Sec. 2 to Bits/Sec. 3 to Bits/Sec. 4 to Bits/Sec. 5 to Bits/Sec. 6042, p. 3-25

65 On the 4Sth output clock pulse (Count 52), the complete good message has been outputted serially from the decoder including a start code and 7 BCH check bits. On the negative edge of Count 52 of the output CLOCK (A23 pin 3) a CT52 Logic O spike is generated at A2S pin 12. CT52 fires the Reset XMT single shot B30 pin 6, generating a 10 MS logic 1 pulse. The negative going RESET XMT pulse at B30 pin 7 resets the XMT latch at A2S pin 4. A2S pin 6 goes high, resetting output clock Cs A22 and B25. The XMT signal goes low which drives the DATA OUT signal (Bl4 pin 12) high. At the end of the RESET XMT pulse, a 10 MS ENDX Pulse is generated from single shot B30 pin 10. The ENDX pulse resets the Enable Data and on FF' s Tia All pin 12. The Enable Data FF resets the input timing logic by resetting the sync detection C's AS and A7 and setting the Data FF Alo.. The RESET signal line goes high which resets the Bit Counter (AlS), BCH FF (AG) and the data storage =egisters (BS, Al, A2, A3 and of B22). At the completion of the 10 MS ENDX pulse, the decoder input logic has been enabled and is ready to accept another data input message. DECODER LOGC ERROR DETECTON TMNG (See Timing Chart Figure 6-26) Sync Error Before data is shifted into the decoder, the correct sync word must be present at the beginning of the message. When a message is received by the decoder, the decoder's input timing logic is enabled by the first received data transition. As with the correct sync word, a 2 µs start pulse is generated to sync the timing clocks to the received message. The ON and Enable Data FF's are set, enabling the sync error detection C's (A7 and AS) and the Data and Phase FF's. The sync error is detected only when the binary data from the Data FF (AlO pin 1) is not the same logic level as the SYNC CHECK signal (A7 pin 2) when the Sync Error FF (AS pin 3) is clocked. Should these signals not correspond, the SYNC ERROR NPUT signal at A9 pin 4 will be a Logic 1 when the Sync Error FF receives a clock pulse from the inverted Q6-CL signal. The sync Error FF will set which drives NANO gate output All pin 6 high, enabling the Reset FF (A6) to set on the next KHz. clock pulse. When the Reset FF sets, A6 pin 14 goes low and resets the Enable and on FF's (BlS) via NANO gates Bl3 pin 3, B20 pin 12 and All pin 12. These flip-flops disable the decoder's input timing logic by disabling the Data and Phase FF's and the sync.error detection C's A7 and AS. The error signal is removed and the Reset FF A6 pin 14 is reset on the next KHz. clock pulse. mmediately after the Reset FF is reset, the decoder input logic will again be enabled whenever the next change in data occurs. 6042, p. 3-26

66 Excess Zero Error The decoder also scans the message for excess zero errors. The Zero Test Counter's (A17) operation is designed so that the counter is reset with every change in data detected by single shots Al4 via NANO gate B20 pin 4 and inverter A24 pin 12. An excess zero error is generated whenever received data (RDD) does not change phase for 9 consecutive Q6-CL pulses, indicating more than eight Logic O data bits in the message. When an excess zero error is generated, NANO gate A4 pin 13 goes low and enables the Reset FF (A6 pin 10) to set by driving NANO gate All output pin 6 high. When the Reset FF sets, the decoder's input logic is disabled the same manner as if a sync error wee generated. BCH Error The decoder performs a BCH error check on the lat 7 data bits of the received message after Bit Count 29. f any of the BCH check bits differ from the BCH check word calculated from the 29 previous data bits, the output of parity generator B4 pin 9 will go hig, enabling the BCH Error FF {B7 pin 13) to set on the next BC clock pulse. Setting of the BCH Error FF, drives B7 pin 14 low and causes NANO gate All output pin 6 to go high. This again enables the Reset FF (A6 pin 10) to be set on the next KHz. clock pulse. The Reset FF also disables the input logic as for sync or zero test errors. The BCH error FF (B7 pin 12) and the BCH Check FF (A6-2) are reset via the reset and enable data signals. nput logic is again enabled with the next change in data after the Reset FF has been reset. Decoder Output Timing For An Error Message As soon as the CXR DET and TRAK signals of the decoder panel are a logic 1 {i.e., when the track circuit is occupied and a car-carried Transponder Coil is present over a Wayside Coil), a seven stage binary counter A21 begins counting Q6-CL pulses. At the 44th count of the counter, which can occur while a message is being decoded, the message received (MSG REC) FF A26 pin 1 is set via NANO gate A28 pin 11 and inverter A24 pin 2. A signal from this FF and a high DATA GOOD signal {sinc.e the message is still being decoded) drives the DG MSG REC signal high at inverter A24 pin 4. The DG MSG REC signal tries to set the Error Message FF {B6 pin 6) but the flip-flop is held reset by a low CD TRAK SMCO signal caused by the presence of a logic 1 CXR DET signal. f no valid (good) messages are received by the decoder by the time the CXR DET signal goes low, the DATA GOOD signal at Al6 pin 15 will remain high, keeping the DG MSG REC signal high. The Error Message FF will then be set on the first positive clock pulse from C Al9 pin 5 after the carrier detect signal is removed, lighting the Error Message LED. A logic O ERROR signal will enable bilateral 6042, p. 3-27

67 switches Bl2 at pins 5 and 14 via NANO gate Bl3 pin 13 which enables a valid test data message, stored in Registers Bll, 16, 21, 22 and B26, to be shifted through shift register B17 to the DATA OUT line by the XMT clock. Data from the decoder's data storage registers cannot be shifted from the decoder since bilateral switches Bl2 at pins 15 and 6 are not enabled and the data shift register does not contain a complete valid message. The ERROR signal holds the Data Load FF set (B27 pin 7), causing the test generator to output a valid test message. As for a good message, the GM+ EM signal at NANO gate B23 _pin 3 goes high which fires the XFER single shot (B28 pin 6) via NANO gate B23 pin 4 and A27 pin 13 which loads the test message to be outputted into the test messag register. A 10 MS error message str.obe (EMST) is generated and outputted at AJ2 pin 8 from NANO gate A4 pin 4 which signifies to external equipment that an error message has been received be decoder. The SET XMT, XMT, CLOCK, CT4, XMT CL, CT52, RESET XMT and ENDX signals occur the same as for a good message output. (See Figure 6-23 and Decoder Logic Output Timing/Good Message description.) The ENABLE DATA signal will be a logic O and the RESET signal will be a logic 1 when an error message is outputted. The DATA OUT signal for an error message will have the form: ' Word ;,... Error Message Data "',/' Fixed Bit BCH Check Word This format is a series of 0010 words (4 Bits each) which are equivalent to the character= (equal sign) in ASC code. This error message indication has a valid format (no sync BCH or zero er.rors) and it is available on the DATA and DATA lines (BJl pins 13 and 12) for transmission to external equipment through the optical isolators on the Power Supply Distribution and nterface PCB. The External equipment must be designed to recognize the 0010 signal (= sign) as an error character. Decoder Test Good and Error Message Timing (See Timing Charts Figure 6-24 and 6-25) ntroduction When the decoder logic unit is placed in the TEST DEC mode, a logic O TEST DECODER signal is fed to the decoder through location Bl pin 9. This signal enables a phase encoded test message, generated within the decoder test message generator, to circulate through the decoder panel to check circuit operation. Proper operation causes the Track LED to 6042, p. 3-28

68 light the Good and Error Message LEDs to alternately flash. NORM, TEST DEC and the KHz clock are the only external signals necessary for the decoder to begin operation in the test decoder mode. n the test decoder mode, the NORM signal at location Bl pin 10 is a logic 1. This NORM signal is also called the TEST signal at the decoder. A logic 1 TEST signal will manually set the Track Occupied FF through B9 pin 9 causing a simulated logic 1 TRAK signal to appear at B9 pin 15. As in normal operation, the set Track Occupied FF will light the Track LED and enable the transmit latch (XMT) to be set. A TEST signal at inverter Bl5 pin 10 is used to disable NANO gates A30 pin 14 and A30 pin 10 which inhibits a logic 1 KEY signal and indication and inhibits test data from exiting the decoder on the DATA lines. Two bilateral switches Bl2 pin 5 and 14 are enabled for transmitting TEST DATA to the DATA OUT signal line. Description of Operation The TEST DEC signal from the receiver at Bl pin 9 is a logic O. This signal removes the reset from the simulated carrier detect (SMCO) FF at A29 pin 12 and also fires a 2 µs single shot at B24 by driving the output of NANO gate B23 pin 13 high. The 2 µs pulse at B24 pin 6 _sets the Cycle Test FF A26, driving the output at A26 pin 14 low. The CYCLE TEST signal clocks and resets the Data Load FF at B27 if it is not already reset. When the Data Load FF is reset, the DATA LOAD signal at B27 pin 2 is a logic 1. This signal is fed into the decoder's test message generator at B21 pin 4 (i.e., the 21st data bit of the test message). The 21st data bit high will generate a BCH error when this message is circulated through the decoder. Therefore the first test message is always an error message. The CYCLE TEST signal also fires the.xfer single shot through B28 pin 4 which dumps parallel data into the test pattern generator C's B26, B22, B21, Bl6 and Bll and also the sync word into the output shift register Bl7 at pin 9. At the completion of the XFER pulse, the SET XMT single shot B28 pin 10 fires, generating a 2 microsecond set Xmit pulse. This pulse, as in normal operation, resets the CT4 FF (A29 pin 4) and sets the XMT latch at A30. A logic 1 XMT signal at A30 pin 3 enables the output clock A22, and binary counter B25. The set Xmit pulse also sets the SMCO FF through A29 pin 9, to simulate a received carrier detect signal. SMCO low drives the CD TRAK SMCO signal low via NANO gate A25 pin 13 and inverter A20 pin 6 and resets the Good and Error Message FF's B6. The DATA OUT signal is driven low by the XMT signal. A 2.4 KHz. output clock signal A22 pin 2 feeds through a bilateral switch A23 pin 2 which is enabled by the TEST signal at A23 pin 15. The data output rate is fixed at 2400 Hz., compatible withlnput data rate requirements. 6042, p. 3-29

69 As with normal operation, the CT4 FF sets on the fourth output CLOCK pulse, enabling the XMT CL signal at A24 pin 6. n the test mode, the XMT CL signal at Bl4 pin 13 is held disabled by a logic O TEST signal at Bl4 pin 14. This prevents the XMT CL from shifting data out of the data storage register to external output terminals but allows the BCl clock to shift data in. The TEST DATA is now shifted through the output register Bl7 to the DATA OUT line by the XMT CL at 2400 Hz. rate. The test message is phase encoded and fed back into the decoder's input timing logic. DATA OUT is a shifted through flip-flop B27 pin 15 which phase encodes the test data (i.e., every time a logic 1 is shifted in, the flip-flop changes state). The phase encoded data at B27 pin 15 is fed through a bilateral switch A23 which has been enabled by the TEST DEC signal at pin 14 to the ROD line and into the decoder's input timing logic. The test message is decoded and checked for sync, zero and BCH errors the same as a normal message. A BCH Error will be generated on bit count 30 since the BCH code is intentionally incorrect for the 29 message data bits, because Bit 21 incorrect. After the input logic becomes reset, it will enable itself and sync errors will be generated as.the decoder looks for a start code in the remainder of the test message. At bit count 52 of the output CLOCK {A23 pin 2), the Reset XMT single shot B30 pin 6 fires. RESET XMT resets the SMCO FF at A29 pin 13 driving the_ _signal to a logic 1. The SMCO signal causes the CD TRAK SMCD signal to go high which enables the Error Message FF B6. Since DATA GOOD is still high because an error message was received, and the Message Received FF (A26 pin 1) was set on the 44th Q6-CL pulse, the DG MSG REC signal at inverter A24 pin 4 will be high. The DG MSG REC signal at B6 pin 6 enables the Error Message FF (B6 pin 1) to set on the next clock pulse, lighting the Error Message LED. The logic O ERROR signal causes the GM+ EM signal at NANO gate B23 pin 3 to go high which resets the MSG REC FF at A26 pin 4. The ERROR signal sets the Data Load FF through B27 pin 7. This flip-flop will be held normally set by the ERROR signal till the SMCO FF A29 pin 14 sets again. Since the Data Load FF is set, a logic O signal is inserted into the 21st data bit of the test message which enables the test generator to circulate a GOOD message through the decoder on the next cycle. The RESET XMT signal single shot also resets the CYCLE TEST FF A26 pin 12 via NANO gate A27 pin 4. After the RESET XMT pulse, single shot B30 pin 10 fires, generating an ENDX pulse. The ENDX pulse resets the decoder input timing logic and sets the CYCLE TEST FF via NANO gate B23 pin , p. 3-30

70 The cycle is repeated with the XFER and Set XMT single shot firing, driving the SMCO signal low and resetting the Good and Error Message FF's and loading another test message. Only this time a good test message is circulated through the decoder. No errors will be generated with this message and the DATA GOOD signal will go low. When the SMCO signal goes high this time, the Good Message FF will set and the Good Message LED will light. When the CYCLE TEST FF A26 pin 14 is set again by the ENDX pulse, the Data Load FF will reset because it is not being held set by the Error Message FF. The decoder will continue to circulate good and error test messages through its circuitry as long as it remains in the test mode. Decoder Test Message Timing {Test Receiver Mode) When the Test switch on the Receiver PCB is placed in the Test Receiver mode, a logic zero TEST REC signal at AJl pin 8 causes the decoder to circulate the test message through the Receiver PCB to check its circuitry before it enters the decoder's input timing logic. Test data enters.the receiver from exclusive or gate A9 pin 13 which modulates the phase encoded test data with a 76.8 KHz. squarewave. The receiver demodulates the data and generates a logic 1 CXR DET signal. The carrier detect and test data signals from the receiver enter the decoder as in normal operation through the RCV DATA (Bl pin 5) and CXR DET {Bl pin 6) lines. Since a carrier detect signal is generated by the receiver, a simulated carrier dete ct (SMCO) signal is not needed, so the SMCO flip-flop A29 pin 12 is held reset by a logic 1 TEST DEC signal. Decoder timing.in the Test Receiver mode is similar to that of the Test Decoder mode, except the SMCO signal is a constant logic 1. The CXR DET LED will flash on and off in this mode. The carrier detect LED is on when the Good and Error Message LEDs are off (reset by the incoming carrier detect signal). When the carrier detect goes away, either the good or error message will light, depending on whether a good or error test message was received Route Buffer Panel (Option #1) For the description and theory of operation of the Route Buffer Panel, see Service Manual 6042A ASC nterface Panel (Option #2) For the description and theory of operation of the ASC nterface Panel, see Service Manual 6042B. 6042, p. 3-31

71 3.5.5 Power Distribution and nterface PCB N Description This Power Distribution and nterface PCB provides surge protection for the signal input and AC input to the Decoder Logic Unit. Connectors J6 and J7 provide input/output access to the signals of the decoder drawer. A regulator circuit creates the regulated voltage for powering the PCB's contained in the Decoder Logic Unit. Also included on this PCB is optical isolation and level translation of signals for the data carrier equipment interfaces used with the serial output of the Decoder Logic Panel, and relay interfaces for the track circuit input and cab signal output circuits Theory of Operation Figure 6-28 is a circuit diagram of the Power Distribution and nterface PCB. The metal oxide varistor (MOV) between faston terminals BXl and CXl provides surge protection for the AC input to the Decoder Logic Unit. The signal input to the Decoder Logic Unit is on pins 1, 3, and 5 of connector J7 of the Power Distribution and nterface PCB. Surge suppressors SPl, SP2, and SP3 provide lineto-line and line-to-ground transient protection for the input signal at a 90 volt level. Transistor Ql, diodes 02 and 03, resistors R2 and R3 and capacitors Cl and C2, comprise a 12 volt DC shunt regulator circuit. Unregulated DC (approximately 14V to 16 VDC) enter.s the regulator circuit at faston terminals Bl and Nl from a packaged power supply. Resistors Rl and LED Dl provide visual indication of the applied unregulated DC. Both unregulated and regulated voltage is available at pins 4 (unregulated +V) and pins 5, 6 and 7 (regulated +V) of connector J3, respect! vely. The "Key" signal from the Decoder Logic Panel enters pin 11 of connector J3 and is optically coupled and level shifted to EA voltage levels by optical col.l.pler Cl. The "Key-On" signal is available on pin 19 of connector J7. (An EA -v Key-On signal is off; EA -+v: Key:-On sigl'l:al is on.) The Data and Data signals from the Decoder Logic Panel enter pins 12 and 13 of connector J3, respectively. Optical couplers C2 and C5 provide isolation and level shifting to EA voltage levels to the transmit data output, pin 18 of connector J7. (EA -v = Mark; EA +V = Space.) Note the power for the EA interfaces (Data and Key-On) is obtained externally from the EA voltage of the optional data carrier equipment. (EA + volts, pin 15 of connector J7, EA - volts pin 17 of connector J7). 6042, p. 3-32

72 Optical isolator C3 provides an isolated track circuit input at pins 11 and 13 of connector J7. nput requirements are 12 to 20 volt DC. Resistors RS and R9, diode D4 and capacitor C3 form a delay circuit for the track output to the Decoder Logic Panel at pin 9 of connector J3. Cab signal relay, C4, is controlled by the cab input from the Decoder Logic Panel at pin 8 of connector J3. he normally open contact of C4 is provided with protection by Rll and C4. The cab signal relay output is on pins 9 and 7 of connector J7. The.relay contact is capable of handling amp. max. at 50 VDC max. or 10 watts max. (resistive load). The Power Distribution and nterface PCB also provides interconnection between connector JG and connectors J4 and JS. These connectors are used for input and output connections. on Decoder Logic Units provided with Route Buffer Panels (N ) and ASC nterface Panel (N ). 6042, p. 3-33

73 3.5.6 Decoder Wire Wrap Panel Connections Jl-1 J2-2 Jl-3 Bl (1) RCV Data (1) DB26 (1) Sig A (1) Sig A (2) (2) DB25 (2) Sig GND (2) Data (To RCV) (3) (3) TR (3) O Volts (3) +V (UNREG) (4) (4) CXR DET (4) +V (UNREG) (4) KHZ (5) (5) (5) +V (REG) (5) RCV DATA (6) (6) +V (REG) (6) +V (REG) (6) CXR DET (7) {7) O Volts (7) +v (REG) (7) +V (REG) (8) (8) (8) CAB (8) TEST REC (9) DB9 (9) (9) TR (9) TEST DEC (10) DBlO (10) TEST (10) TR GND (10) NORM (11) DBll (11) GM+ EM (11) KEY (11) O Volts (12} DB12 (12) TRAK (12) DATA (12) 0 Volts (13) DB13 (13) MSTR (13) DATA (13) O Volts (14) DB14 (14) DB27 (14) SB B (14) O Volts (15) DB15 (15) DB28 (15) 0 Volts (15) O Volts (16) DB16 (16) KHz (16) 0 Volts (16) SG B (17) DB17 (17) (17) 0 Volts (18) DB18 (18) (18) 0 Volts (19) DB19 (19) DBS (19) O Volts (20) DB20 (20) DB7 (20) O Volts (21) DB21 (21) DB6 (21} O Volts (22) DB22 (22) DBS (22) O Volts (23) DB23 (23) DB4 (23) O Volts (TR GND) (24) DB24 (24) DB3 (24) O Volts (25) (25) DB2 (25) O Volts (26) (26} (MSB) DBl (26) O Volts Connector J2-4 is not used. 6042, p. 3-34

74 3.5.7 AV Decoder Wiring *Cab Signal and Route Output Relays Contact Rating.5 amp Max; 50 VDC Max 10 watts {Maximum) J7-ALL J J JS-ALL PN SGNAL PN SGNAL PN SGNAL PN SGNAL NO. NAME NO. NAME NO. NAME NO. NAME 1 Signal A nput 1 From nterrogator 1 EA-V nput A BXl B en 3 Signal B nput 3 3 EA DATA c GROUND From nterrogator ASC OUTPUT EA KEY-ON OUTPUT 5 Signal Ground 5 5 From nterrogator EA +V nput 7 Cab Signal* 7 Route l* 7 Relay Output / w 9 Cab Signal Relay Common \ 0 Route J 9 10 \ 10 Route \ Track ndication 11 Route VDC) Route Track ndication 13 Route 7 13 Common (OV) Route EA +Volts nput 15 Route Route EA -Volts nput 17 Route Transmit Data 18 Route BCH Output 19 Key-On output 19 Route ASC Current Loop Common ASC Current Loop nput ASC 20 MA. Current Loop nput (510 ohm resistor) Route Route Route Route Route Route Route 20* Jl JS JS JS Route Common Route Common , p. 3-35/36"

75

76 SECTON V NSTALLATON 4.1 CAR-CARRED EQUPMENT Required Equipment 1. Transponder Coil N Progranuner N Cable Assembly N Transponder Coil (N ) The AV Transponder Coil assembly is provided with a mounting frame for mounting the coil to a customer supplied frame under the car body. t is recommended that the coil be mounted near the center of the car, along the centerline of the vehicle, to provide for bi-directional running of the vehicle. The coil must not be placed closer than 12" from any metallic object, except the coil mounting frame. The Transponder Coil should not be placed closer than 4 ft. from any truck wheel, that is 4 ft. from the centerline of the last wheel in a truck. AV coils cannot be mounted closer than 40 ft. from each other. When mounting the coils, the gap in the mounting frame must not be shunted by any metallic object, as this will result in a shorted turn, effectively shielding the coil Programmer (N ) The Programmer box is manufactured for mounting in the motorman's cab of the vehicle. The front panel provides a flat surface for rear mounting to a panel. Four 10x32 threaded mounting holes are provided for mounting Cable Assembly (N ) The Programmer and Transponder Coils are interconnected via a 40 ft. cable (2 twisted pair with shield). One end of'this cable is supplied with a waterproof AN/MS connector attached and another connector is supplied for attachment on the opposite end after the cable has been mounted. t is recommended that the cable be run through conduit to protect it from physical abuse and environmental damage. Note: the 40 ft. cable must not be shortened or lengthened without consulting WABCO. This cable is part of a tuned circuit and changes in length will affect coil tuning, degrading car-carried equipment operation. 6042, p. 4-1

77 4.1.5 nterface Wiring (Programmer) The rear of the Programmer contains two (2) panel mounted AN/MS connectors for input/output connections. The smaller of the connectors provides connections to the Transponder cable. The mating cable plug is wired to the 40 ft. cable as follows: J4 Pin A B c D Wire Color Red Black White Shield Drain Wire E Green The mating female cable connector is J (MS3106E-16S-lS) The second connector provides an input to the four status indication bits when required. Each of the four status inputs is an individual 2 wire circuit, plus and minus, that will operate from a nominal 36 volt DC input (24 to 40 volts DC). Each input draws approximately 5 ma. at 36 VDC. Wiring and pin numbers are as follows: JS Pin A Lead car indication input, positive (+) B Lead car indication return, negative (-) c Cab signal indication input, positive (+) D Cab signal indication return, negative (-) E 1st spare indication input, positive (+) F 1st spare indication return, negative (-) G 2nd spare indication input, positive (+) H 2nd spare indication return, negative (-) The mating female cable connector is J (AN3106A-20-7S). Cable clamp, J (AN ). Boot, J (AN ). " Car Number nsertion The car number is inserted and programmed in the AV Programmer via four 10 position rotary switches, accessible from the side of the P.rogrammer through holes in the case, when the cover is removed. A small screwdriver can be used to rotate the switch dials to the appropriate digit value. 6042, p. 4-2

78 The number and switch relationship is as follows: Switch SWl Switch SW2 Switch SW3 Switch SW4 {leftmost) = units (2nd from left) = tens (3rd from left) = hundreds (rightmost) = thousands Refer to the label inside of the lid for switch locations: When replacing the lid, the large side must cover switch access holes WAYSDE EQUPMENT Required Equipment Qty. Description Piece Number nterrogator Panel nterrogator Case Junction Box Coil Cable T.W.C. Wayside N T.w.c. Wayside N T.w.c. Wayside N T.w.c. Wayside J ft. _±6 inches, A #8 AWG, 2 conductor, twisted, shielded, direct burial. shielded 1 Cable Power cordage, 3 conductor #14-16 AWG Customer Supplied 1 Cable Signal, 135 ohm, Customer Supplied twisted pair, shielded maximum length approximately 5,000 ft. 1 Equipment Rack ncluding Decoder Logic Unit Depends Upon Application 6042, p. 4-3

79 4.2.2 Wayside Procedure 1. Establish the location of the Wayside Coil and junction box between the rails. 2. Establish the location of the AV nterrogator Unit. - Note: Cable A from the junction box has a fixed length of 30 ft. The signal cable from the nterrogator to the Decoder Logic Unit has a maximum length of 5000 ft. 3. Determine the location and dig trenches for all cables, including the AC power and signal cables (if underground installation is desired) between the equipment rooms and/or cases. 4. Lay all cables in the trenches and determine their correct lengths. 5. Build the foundation for the nterrogator Unit. 6. nstall the junction box for the Wayside Coil between the rails. 7. Fasten the Wayside Coil to the ties between the rails in such a way as to allow for some motion of ties, due to changes in environment, with a minimum amount of stress on the Wayside Coil. Note: Use no metallic framework. 8. Connect coil and cable A to the wayside junction box. Note: The cable shield is not terminated at the Wayside Coil, only in the nterrogator. 9. Mount the nterrogator case on the nterrogatqr foundation Wire the power, coil and signal cables to the AAR terminals in the nterrogator case. Note: The coil cable shield S terminated at the nterrogator end. 11. Mount nterrogator subplate assembly N into the nterrogator case N and attach MS connectors. Note: Before installation, check nterrogator power connection options for either 110 or 220 VAC operation. NOTE For 220 VA9'.-operation, a jumper connects between terminals 2 and 3 on TB-A of the nterroi.;rator Unit (See.Figure 5-12). For 110 VAC operation, jumpers connect between terminals 2 and 4 and between terminals 1 and 3 on TB-A of the nterrogator Unit (See Figure 5-12). 6042, p. 4-4

80 WAYSDE NSTALLTON COMPLETE Equipment Room Procedure 1. Locate the AV equipment rack containing a Decoder Logic Unit in the Equipment Room. NOTE: Should decoder logic drawer come unmounted, consult WABCO-Union Switch & Signal Division for assembly instructions. 2. Connect AC power (115 or 220 VAC, check power options) to the nterrogator power cable. Note: nterrogator unit should be turned off before applying AC power. 3. nstall 115 VAC power to AV equipment rack. -4. Feed cable for return signal from the nterrogator to the Equipment Room and connect to the AV rack. Note: Ground the shield of return signal cable at this end only. 5. Wire the track indication input to the AV rack. 6. Wire outputs as required or used from AV rack to external equipment for route selection, cab signal, data set, local displays, etc. 7. Perform tuning adjustments, as per paragraph 4.3, at the wayside and the Equipment Room. END OF NSTALLATON 4.3 SYSTEM ADJUSTMENTS AND TUNNG The following adjustments and tuning procedures are necessary after the complete installation of all AV equipment. t will also be necessary to repeat these procedures in the event of the replaement of the nterrogator, coils, or cable assemblies because of critical component parameters nterrogator Adjustments Power Output and Tuning.Adjustments This procedure is used to tune the AV and adjust the power level of the KHz. amplifier in the nterrogator. 1. Connect a VOM (set to the 50 volt b.c. scale) to the meter terminals on the nterrogator (Control PCB N ) 6042, p. 4-5

81 2. Make sure that the nterrogator power switch is in the "ON" position. 3. Adjust potentiometer RS (upper right side of amplifier PCB) until the meter reads 10 volts (indicating 100 volts RMS output). 4. Loosen lock nut on the variable tuning capacitor located below the meter terminals, and adjust the capacitor for a peak reading on the meter. Retighten the lock nut. Note: f no peak is noted, remove jumper from 1 and 2 on PCB N and connect between 2 and 3 and then repeat procedure. 5. Adjust potentiometer RS for a 20 volt reading on the meter, (200 VAC output). 6. Remove the meter connections Received Signal Level Adjustments This procedure is used to set the gain of the amplifier that drives the line carrying the received signal between the nterrogator and the TWC Decoder Logic Unit. This procedure requires two persons and communication between the relay room (decoder drawer) and the wayside nterrogator. Necessary equipment includest 1. An AV car-carried transponder system. 2. Hewlett Packard Model 403A - transistorized AC voltmeter or equivalent db meter. Test Procedures 1. Place the power switch on the TWC Decoder Logic Unit in the "OFF" position. 2. Connect the AC voltmeter between test point 3 and test point 5 (TP3 is common) on the Receiver PCB located in the Decoder Logic Unit. 3. Set the voltmeter to the O db scale. Energize the meter and TWC Decoder Logic Unit. One person must remain at the relay room to record the meter readings and carrier detector indication. 6042, p '

82 4. Perform the Power Output and Tuning Adjustment procedure on the nterrogator under test (See Sec ). 5. Place a known good AV car-carried Transponder Coil {connected to the car-carried Programmer) approximately 12 to 14" above the Wayside Coil. 6. Adjus.t potentiometer Rl8 in the nterrogator on the upper left side of the PCB for a reading of -5 to -15 db on the AC voltmeter at the relay room. {Verify the reading through voice communication to the relay room.) (Verify that the Carrier Detect LED in the decoder is lit.) The recommended setting is -10 db. However, on extremely short lines, this level may overdrive the line and a readjustment to no less than -15 db may be necessary Verify that the Carrier Detect LED, in the decoder drawer,' extinguishes when the Transponder Coil is removed from the field of the Wayside Coil. Also verify that the db meter reads less than -SO db. a. f the Carrier Detect LED in the decoder drawer does not extinguish when the transponder is removed, lower the gain adjustment by turning potentiometer Rl8 in the nterrogator until the Carrier Detect LED just extinguishes. (Note the Transponder Coil should NOT be over the Wayside Coil.) Replace the Transponder Coil over the Wayside Coil at a 12 to 14" height. Verify that the Carrier Detect LED lights in the decoder drawer, and that the received signal level is between -5 db and -15 db. f the signal level is less than -15.db {e.g., -20 db, etc.), the signal line between the interrogator and decoder is faulty and should be examined for proper connections and a single one-point ground on the shield, and checked for induced noise. END OF ADJUSTMENTS AND TUNNG 6042, p. 4-7/8

83

84 SECTON V MANTENANCE - TROUBLESHOOTNG 5.1 NTRODUCTON This section is provided to aid maintenance personnel in the testing and/or repair of suspect defective AV equipment. The information provided and procedures detailed herein are based upon the availability of a known complete working AV system to maintenance personnel. The troubleshooting procedures are based on the concept of replacing faulty equipment sub-assemblies (printed circuit boards, power supplies, etc.) in the field locations with operable spares and returning faulty equipment to shop service for repair. A majority of the problems associated with the AV equipment will be repairable by these procedures Maintainer Capabilities Maintenance personnel involved with performing the troubleshooting operations outlined herein should have a basic understanding of electronics but do not necessarily need to comprehend the complete operational cocepts of the AV system. However, it must be recognized that the problem solving techniques presented here may not solve all system problems. Problems of this nature must be referred to personnel having an understanding of the operational features of the AV equipment; Section and of this manual. Personnel required to gain the understanding should have a knowledge of digital equipment and integrated circuit hardware operational concepts, especially Complementary Metal Oxide Semiconductor (CMOS) devices. 5.2 GENERAL ALGNMENT f in the course of maintenance/troubleshooting it becomes necessary to replace the nterrogator or its sub-assemblies, the coils or the Cable Assembly, it will be required to perform the System Adjustments and Tuning procedures (Refer to Section 4.3). This is due to the critical cable length, electrical parameters and tolerances of the aforementioned assemblies. 6042, p. 5-1

85 5.3 BASC SYSTEM FELD TROUBLESHOOTNG The purpose of this guide is to aid field service personnel in locating and replacing defective AV components at field wayside locations and carborne installations. Defective assemblies should be forwarded to shop service facilities for repair Recommended Equipment 1. Simpson 260 VOM {or equivalent). 2. Complete spare AV equipment set, including: A. Wayside (1) Wayside Coil J (2) TWC nterrogator Unit N (3) TWC Logic/Decoder Unit N as applicable B. Car-Carried (1) Programmer (2) Transponder Coil (3) Cable N N N General This proce.dure gives. a list of symptoms and a sequential checking guide which isolates failures to the various components of the AV system. The first problem encountered is to determine whether fault is located on car-carried or wayside equipment. t is unlikely that all wayside or all car-carried equipment will fail at any one time. As a further aid to field service personnel in isolating system component failures, a Troubleshooting Guide is presented in flow chart form in Figures 5-1 through , p. ;..; Basis System Failures There are three basic failures: 1. Problem A - All Transponders fail at a given wayside. Solution: Problem is in wayside equipment - perform wayside tests, Section

86 2. Problem B - Some transponders fail at all wayside locations. Solution: Replace suspect car-carried equipment. 3. Problem C - Some Transponders fail only at certain waysides. Solutions: (1) Check for proper mounting of the car-carried Transponder Coils. NOTE Before removing car-carried equipment, check for opens or shorts in cable assembly N and proper inputs from the vehicle via connector JS. Also check for proper mounting of the Transponder Coil N l under the vehicle; verifying that the gap in the coil mounting frame is not closed by any metallic path or substance. (2) Perform the Power Output Tuning and Received Signal Level adjust procedures. (Sec. 4.3). (3) Replace suspected car-carried equipment. t is recommended that no troubleshooting other than mechanical inspection be done on carborne units while mounted on the vehicle, except when a wayside installation is conveniently located nearby in an area that does not conflict with revenue service, and only as a last resort. Return suspect carborne equipment to repair facilities Wayside Malfunction Symptoms Fault isolation of the system begins by identifying the symptom of the system failure mode. Listed below are the three major symptoms of a wayside equipment failure. 1. No Response At All. (Section ) 2. ncorrect Response-Errors. (Section } 3. Missing nformation - Cab Signaling, Routing, etc. (Section } 6042 t P, 5-3

87 Refer below for troubleshooting guide for the above three wayside malfunction symptoms No Response At All - check the following items in order presented: A. Relay Room - TWC Decoder Logic Unit (1) Are all connectors on rear of the TWC decoder/logic drawers properly inserted? (2) s the front panel power switch in the "ON" position? (3) s the front panel fuse o.k. ( amp slo-blow)? Assure A.C. input to decoder logic drawer is present. (4) Release slide lock, pullout drawer, and remove cover by unfastening the two turn fasteners. Refer to tag on inside cover for location of LED's and switches. (5) s the Power On light emitting diode, (Dl), on the Power Distribution and nterface PCB lit? f not, replace drawer (power supply failure). (6) s the rotary switch on the Receiver PCB in the "NORMAL" (center-12 position)? f not, place in "NORMAL" position and check if system is operational. (7) Place rotary switch in position 1 (test decodercounter-clockwise). This tests the Decoder Logic Panel. LED 1 on the receiver should light. On the decoder panel, the Track LED should light, and the Good and Error Message LED's should alternately-flash. Replace drawer if any indication is not observed. (8) Place the rotary swjtch in _position 3 (test _ receiver-clockwise). This tests the Decoder and the Receiver printed circuit boards. All indications, as in Step 7, should occur. The Carrier Detector LED should also be lit. Replace drawer if any indication is not-observed. (9)" Return the rotary switch to the "NORMAL" (center) position (2). With no vehicle in the track circuit, all LED ' s on the Receiver and Decoder boards should be out. f either the Track or Key-On LED's are on when the 6042, p. 5-4

88 track is unoccupied, check the external track relay logic and connections into the AV decoder drawer through connector J7. Check that the Carrier Detect LED lights when a Transponder Coil is placed over the Wayside Coil (at approximately 12-14" height) and goes off when the coil is removed. f the carrier detect fails to light up, no signal is being received from the nterrogator- go to nterrogator Check Section l(B). f the Carrier Detect LED is on constantly without a transponder present, refer to the nterrogator Received Signal Level Adjustment procedures. (Section 4.3) f the LED's are lit as in Steps 7, 8, and 9, but the Good Message LED does not light when the track circuit is occupied and a transponder is passed over the Wayside Coil, the problem is most likely in the tuning of the nterrogator filter circuit. Replace the nterrogator, as the filter adjustment is a bench adjustment and should not be done in the field. Refer to Section 5.7 for nterrogator bench troubleshooting. Before proceeding to the.nterrogator for further check, generate a false track occupancy by jumpering the contacts on the AV track repeater relay. Verify that the Track Occupy and Key-On LED's are lit. Check for a missing or_blown fuse in the relay room power lines that provide AC to the nterrogator. B. nterrogator Check (1) Check that the 2 MS style connectors in the nterrogator box are firmly in place. (2) Check that the power switch is in the "ON" position and LD2 is lit. f not, check the fuse and power connections on A:AR terminal strip for power input signal. Check for a missing or blown fuse in the relay room rack, which provides AC to the nterrogator. WARNNG: The nterrogator may be powered with 220 volts A.C., 60 Hz. The output is 200 to 300 volts AC. at KHz. Care should be taken when working with this unit. 6042, p. 5-5

89 (3) Check the power output of the nterrogator by connecting a VOM (set to 50 voe scale) to the two meter terminals. The reading should be 20 volts (NOTE: The meter reading on the 50 yoc scale should be multiplied by ten to indicate the actual RMS AC output voltage). f necessary, adjust potentiometer RS (located on the upper right side of the nterrogator PCB near the large filter capacitor) for a 20 volt DC reading (200 volts RMS output). f the power output cannot be adjusted to meet the specified output, perform the amplifier tuning procedure (Section 4.3) before replacing the nterrogator Panel. (4) f the output of the new nterrogator cannot be adjusted properly, check for a broken wire (or shorted_ wj;e) _t_the Wayside Coil. Temporarily connect a khown good Wayside Coil in place of the suspect coil to verify Wayside Coil failure. (Use 30 ft. cable A ) (5). f the pciwer.._ciutput is within spec place a - working Transponder over the Wayside Coil. Check for proper operation of the AV. Perform the nterrogator Received Signal Level Adjustment procedure (Section ). f the system is still not operational, replace the nterrogtor. (6) Check all inter-unit wiring for shorts or opens between relay room, interrogator and Wayside Coil ncorrect Response-Errors 6042, p. 5-6 f messages are being received at the AV Decoder Logic Unit, but only in error, check the following in the order presented: A. Relay Room - TWC Decoder Logic Unit (1) Release decoder drawer slide lock, pullout drawer, and remove cover by unfastening t,h,e two turn fasteners. Refer to tag on inside cover for location of LED's and switches. (2) Place the rotary switch on the receiver in position 1 (test decoder-counter-clockwise). This tests the Decoder Logic Panel. LED 1

90 on the Receiver should light. On the Decoder Panel, the Track LED should light and the Good and Error Message LED's should alternately flash. Replace drawer if any indication is not observed. (3) Place the rota switch in position 3 (test receiver-clockwise}. This tests the Decoder and the Receiver printed circuit boards. All indications, as in Step 2, should occur. The Carrier Detector LED should also be lit. Replace drawer if any indication is not observed. B. nterrogator (1) Perform the Power output Amplifier Tuning Procedure and Received Signal Level Adjustment Procedure (Section 4.3) on the nterrogator Unit under test. (2) f the system is not operational, replace the nterrogator and retune as per Section 4.3. (3) Check the signal line between the nterrogator and Decoder Logic Unit for intermittent connections, proper grounding of all shields, and possible induced noise. (4) f the signal line is o.k, replace the decoder drawer Missing nformation - Cab Signaling, Routing, Etc. A. f the AV is receiving valid messages at the decoder drawer, but the cab signal indication is not functioning in the external equipment: (1) Check to see if the Cab Signal LED in the decoder drawer lights when a Good AV message is received. See "NOTE" below. (2) f the Cab Signal LED lights, check the cab signal output external equipment and wiring. Remove connector J7 from the rear of the decoder drawer and jumper pins 7 and 9 together on the cable plug (connector 7). This simulates the cab signal relay contact. 6042, p. 5-7

91 f the simulated contact closure operates the extrnal equipment, replace the decoder drawer. f the external equipment fails to operate, the problem is in the external wiring. (3) f the Cab Signal LED fails to light, replace the decoder drawer. (4) Check the car-carried equipment for correct operation of the cab signal and lead car (auxiliary bits 1 and 2) inputs. Replace the suspect car-carried Programmer Units. NOTE: To properly receive the cab signal indications, the cab signal and lead car information must be sent in the first good message after the track circuit is occupied. A Transponder Coil connected to a Programmer with lead car and cab signal status bits activated, must be passed over the Wayside Coil at a 12 to 14" height. The track circuit relay connected to the AV decoder drawer under test, must be cycled to occupy and unoccupy after every message. B. f the AV is receiving valid good messages at the decoder drawer but the route information is incorrect, perform the following checks: (1) Make sure that the AV decoder drawer is type N with the Route Buffer option. (2) Check that connector J6 is firmly connected at the rear of the decoder drawer. (3) Check that the First Message, Good Message and Correct Route LEDs are lit when the first good AV message is received after the track circuit has been occupied. (4) f the First Message and Correct Route LEDs are lit, check all external wiring tq the route relay outputs on connector J6. Remove plug connector to J6 and jumper across appropriate pins on the cable plug to simulate route relay contact closures. 6042, p. 5-8

92 f the wiring is correct, replace the decoder drawer with another type. (5) f the First Message or Correct Route LEDs do not light, verify that the route selector switches on the car-carried Programmers are set to the correct route number between 1 and 20 and the lead car status input (auxiliary bit 1) is activated. Verify that lead car indication is sent on the first good message received after the track circuit has been occupied. Replace the decoder drawer with another type. 6042, p. 5-9

93 AV/TWC SYSTEM START YES PROBLEM S N WAYSDE EQUP. PERFORM WAYSDE TESTS FG. 5-2 DO SOME TRANSPONDERS FAL AT ALL WAYSDE LOCATONS 7 YES REPLACE SUSPECTED CAR CARRED EQUPMENT. NO NO YES 1. REPLACE SUSPECTED CAR CARRED EQUPMENT. 2. PERFORM NTERROGATOR DJUSTMENTS {Sec. 4.3) 3. CHECK MOUNTNG OF SUSPECTED CAR CARRED EQUPMENT. SYSTEM S OPERATNG OK. Figure 5-1. AV/TWC System, Test and Troubleshooting Guide 6042, p. 5-10

94 WAYSDE LOCATON START NO CHECK EQUP. N RE.AV AM. PER FG. 5-3 ANDNTERR. PER FG. 5-4 YES CHECKTWC DECOOER/LOGC UNT AND NTERROGATOR PER, FG. 5-5 NO YES CHECK TWC DECODER/LOGC UNT CAB SGNAL. CRCUTS PER FG, 5-6 YES CHECK TWC DECODER/LOGC UNT ROUTE BUFFER CRCUTS PER FG,5-7 AV/TWC WAYSDE LOCATON S OPERATNG PROPERLY, Fi_r.e 5-2 AV/TWC Wayside System, Testing and Troubleshooting Guide 6042 p 5-11

95 RELAY ROOM START MAKE SURE CONNECTORS > ARE PROPERLY AND SECURELY NSERTED. PLACE SWTCH NON POSTON. REPLACE FUSE laslo BLO. PROBLEM SNAC POWER DSTRBUTON TO DRAWER. RELEASE SLDE LOCK, PULLOUT DRAWER, AND REMOVE COVER. REFER TO LABEL ON NSDE COVER FOR LOCATON OF LED'S AND SWTCHES. NO THERE SA POWER SUPPLY FALURE. REPLACE DRAWER. CONTNUED ONSHEET2 Figure 5-3A Relay Room, AV/TWC Testing and Troubleshooting Guide {Sheet 1 of 4) '6042, p. 5-12

96 FROM SHEET t NO PLACE SWTCH N NORMAL POSTON AND RECHECK EQUPMENT, STARTNG WTH SHEET 1. PLACE ROTARY SWTCH N POSTON 1 (TEST DECODER (CCW. (THS TESTS THE DECODER LOGC PCB. NO REPLACE DRAWER FANY NDCATON SNOT OBSERVED. PLACE ROTARY SWTCH N POSTON 3 (TEST RECEVERJ (CW. (THS TESTS THE DECODER AND RECEVER PCB'S. NO REPLACE DRAWER. RETURN ROTARY SWTCH TO NORMAL POSTON AND MAKE CERTAN THAT TRAN S NOT N TRACK CRCUT. CONTNUED ON SHEET 3 Figure 5-3B Relay Room, AV/TWC Testing and Troubleshooting Guide (Sheet 2 of 4) 6042, p. 5-13

97 FROMSHEET2 YES PROBLEM SN EXTERNAL TRACK RELAY LOGC OR CONNECTONS TO J7. PLACE TRANSPONDER COL ABOUT NCHES ABOVE WAYSDE COL. S CARRER DETECT LED LT 1 NO NO SGNAL BENG RECEVED FROM NTERR OGATOR. CHECK NTERROGATOR PER FG. 5-4 REMOVE TRANSPONDER COL FROM ABOVE WAYSDE COL, YES ADJUST NTERROGATOR SGNAL GAN Sec ENSURE TRACK CRCUT S OCCUPED AND TRANSPONDER COL S PLACED OVER WAYSDE COL.!NOTE 21 CONTNUED ON SHEET4 Figure 5-3C Relay Room, AV/TWC Testing and Troubleshooting Guide (Sheet 3 of 6042, p. 5-14

98 FROM SHEET3 NO PROBLEM S MOST LKELY MPROPERLY TUNED NTERROGATOR FLTER. REPLACE NTESROGATOR (NOTE 11. YES RELAY ROOM AV/TWC EQUPMENT OPERATNG OK. CONTNUE AV/TWC SYSTEM TEST PER FG, NOTE: 1. FLTER ADJUSTMENT CANNOT BE DONE N FELD, 2, F NECESSARY, GENERATE A FALSE OCCUPANCY CONDTON BY JUMPERNG THE CONTACTS ON THE AV TRACK REPEATER RELAY. Figure 5-3D Relay Room, AV/TWC Testing and Troubleshooting Guide (Sheet 4 of 4) 6042, p. 5-15

99 NTERROGATOR START YES REPLACE OR NSTALL FUSE. REPEAT SYSTEM TEST PER FG.5-2 NO NO PROPERLY NSTALL THEM. REPEAT SVSTEMTEST PER FG YES CHECK FUSE AND POWER N.;.;O CONNECTONS ON AAR STRP 'FOR POWER NPUT. YES WARNNG EXERCSE EXTREME CAUTON WHEN MEASURNG POWER NPUT TO NTERROGATOR. PROBLEM SN NO AC DSTRBUTON ;.;: TO NTERROGATOR FROM RELAY ROOM. LED LD2 CRCUT S DEFECTVE. CONTNUED ONSHEET2 Figure 5-4A nterrogator, Testing and Troubleshooting Guide (Sheet 1 of 3) 6042, p. 5-16

100 FROM SHEET 1 WTH VOM SET TO 50 voe RANGE, CHECK NTERROGATOR OUTPUT BY CONNECTNG VOM TO THE TWO METER TERMNALS. WARNNG EXERCSE EXTREME CAUTON WHEN MEASURNG OUTPUT WHCH S BETWEEN 200 TO 300 VOL TS AC AT 153.&KHZ. NOTE: YES NO ADJUST POTENTOMETER RS (RGHT SDE OF NTERROGATOR PCB NEAR LARGE FLTER CAPACTOR) FOR 20 voe READNG. 1. METER READNG ON 50VOC RANGE, WHEN MUL TPLEO BY 10 YELDS THE RMS AC OUTPUT. 2. TEMPORARLY CONNECT KNOWN GOOD WAYSDE COL TO NTERROGATOR TO VEAi FY WAYSDE COi L FALURE. F POWER OUTPUT CANNOT BE ADJUSTED FOR 20VDC READNG, PERFORM PROCEDURE N SEC NO REPLACE NTERROGATOR. ADJUST NEW NTERROGATOR (Sec. 4.3)" YES YES NO PROBLEM S WAYSDE COL OR BROKEN OR SHORTED WRE TO WAYSDE COL. (NOTE 21 PERFORM THE NTERROGATOR RECEVED SGNAL ADJUSTMENT PROCEDURE (Sec ) REPEAT SYSTEM TEST PER FG. 5-2 CONTNUED ONSHEET3 Figure 5-4B nterrogator, Testing and Troubleshooting Guide (Sheet 2 of 3) 6042, p. 5-17

101 FROM SHEET2 NO REPLACE NTERROGATOR YES NO CHECK ALL NTER UNT WRNG FOR SHORTS OR OPENS. YES WAYSDE LOCATON SOK. Figure 5-4C nterrogator, Testing and Troubleshooting Guide (Sheet 3 of 3) 6042, p. 5-18

102 NCORRECT RESPONSE START RELEASE SLDE LOCK, PULLOUT DRAWER, AND REMOVE COVER. (REFER TO LABEL ON NSDE OF COVER FOR LOCATON OF LED'S AND SWTCHES.) PLACE ROTARY SWTCH N POSTON l (TEST DECODER) NO REPLACE DRAWER PLACE ROTARY SWTCH N POSTON 3 (TEST' RECEVER), (THS TESTS THE DECODER AND RECEVER PCB'S, ARE ALL NDCATONS FROM PREVOUS STEP PRESENT PLUS CARRER DETECTOR LED LT? NO REPLACE DRAWER PERFORM NTERROGATOR POWER OUTPUT AND TUNNG PROCEDURE PER. (Sec. 4.3) CHECK SYSTEM BY PERFORMNG PROCEDURES N FG CONTNUED ONSHEET2 Figure 5-SA ncorrect Response, Testinq and Troubleshooting Guide (Sheet 1 of 2) 6042, p. 5-19

103 FROM SHEET 1 NO REPLACE NTERROGATOR CHECK THE SGNAL LNE BETWEEN NTERROGATOR AND DECODER LOGC UNT FOR NTERMTTENT CONNECTONS, PROPER GROUNDNG OF ALL SHELDS AND POSSBLE NDUCED NOSE. NO REPAR AS NECESSARY. YES REPLACE DECODER DRAWER. Figure 5-SB ncorrect Response, Testing and Troubleshooting Guide (Sheet 2 of 6042, p. 5-20

104 CAB SGNAL EXTERNAL NDCATON MSSNG YES REMOVE CONNECTOR J7 FROM REAR OF DECODER DRAWER AND JUMPER PNS 7 AND 9 TOGETHER ON THE CABLE PLUG, THS SMULATES CAB SGNAL RELAY CONTACT CLOSURE. NO REPLACE DECODER DRAWER NO PROBLEM SN EXTERNAL EQUPMENT YES REPLACE DECODER DRAWER NOTE: 1. TO PROPERLY RECEVE CAB SGNAL NDCATONS, CAB SGNAL AND LEAD CAR NFORMATON MUST BE SENT N THE FRST GOOD MESSAGE AFTER THE TRACK CRCUT S OCCUPED. Figure 5-6 Cab Signal Missing External ndication, Test and Troubleshooting Guide 6042, p. 5-21

105 ROUTE NFORMATON NCORRECT ENSURE THAT DECODER DRAWER S TYPE UN WTH ROUTE BUFFER PCB. NO PROPERLY CONNECT CONNECTOR NO SET SWTCHES. TO CORRECT NUMBER NO REPLACE DRAWER WTH ANOTHER 0301 TYPE PROBLEM S N EXTERNAL EQUPMENT. CHECK WRNG TO ROUTE RELAYS. Figure 5-7 Route nformation ncorrect, Test and Troubleshooting Guide 6042, p. 5-22

106 5.4 SHOP MANTENANCE The procedures outlined in the following sections are presented as a guide to maintenance and repair personnel to assist in the troubleshooting and repair of defective AV equipment at maintenance and repair facilities Required AV Equipment The procedures described herein are based upon the availability of a complete AV system consisting of: A. Wayside nterrogator Case Wayside Coil Cable - 30 ft. Decoder and ASC terminal or Decoder N N J A special, direct burial (fixed length) N KSR33 teletype or compatible Cathode Ray Terminal N with Route Buffer nterconnecting cables, see Figures 5-12, 5-13, and Test Cable - nterrogator to Decoder Logic Unit Belden #8737, 22 AWG, twisted pair, shielded, (length as required). Cable Connectors - for J6 and J7 from Decoder, 37 way. AMP-connector # (J070945) -housing # (J709542) -mounting hdw. # (J507357) -contact, female # (J709544) or Cinch -connector #DC-375 -housing #DC mounting hdw. #D Mating Connector-for J8 from Decoder (AC nput) 3 Pin connector #AN3106A-14S-7S (J ) Clamp #AN (J700875) Boot #AN (J070322) 6042, p. 5-23

107 B. Carborne Programmer Transponder Coil Cable Assembly Cable, Test N N N ll01 (fixed length 40 ft.) Refer to Figure 5-9 This system equipment should be maintained in working order at depot maintenance facilities for troubleshooting and repairing subsystem components when required Suggested Test Equipment tem 1 ea. Frequency Counter Minimum Specifications Freq. Range: 1 Hz. to 50 MHz. Accuracy: ±0.001% Sensitivity: 100 MV RMS Readout Digits: 7 Digits Suggested Model 1. HP 5245L Frequency Counter 2. HP 5223L Frequency Counter 1 ea. Oscilloscope with compatible 10:1 probes (2 required) Freq. Range: DC to 30 MHz. Time Base: 0.2 µs/dv to los/dv. with delay and mixed sweep. Time Base Accuracy: 1% Dual Channel, Operation. AC or DC Coupling External Sweep Mode Voltage Accuracy: ±3% Sensitivity: 0.05 V/DV. to SOV/DV. 1. Tektronix Tektronix , p. 5-24

108 5.4.2 Continued tem 1 ea. V.O.M. Minimum Specifications Voltmeter Voltage Range: OV to SOOOV Accuracy: ±3% nput Resistance: 20K ohm/vdc SK ohm/vac Ammeter: Current Range SOµA to loa Accuracy: ±2% Ohmmeter: Resistance Range: 0 to 20 Megohm Accuracy: ±5% Reading at Center Scale Suggested Model 1. Simpson ea. AC V.T.V.M. or (T.V.M.) 1 ea. Signal Generator (Sinewave) 2 ea. 1 ea. Band Width: 1 Megahertz Frequency Range: lhz-lmhz Sensitivity: 1 MV nput mpedance> 2 Megohm Shunted by 60 pf Frequency Range: 10 Hz KHz Output Amplitude: 20V rms Frequency Accuracy: 2% Output mpedance: 600 ohms Power Supply - 12 volts ±.5 volt DC@ 1 ampere Power Supply - 36 volts ±2 volts DC@ 1/2 ampere 1. HP 403A 2. HP 400LR 3. HP Wavetek Model Wavetek Model , p. 5-25

109 5.4.3 Optional Test Equipment (Coil Testing) Quantity tem 1 ea. mpedance Bridge Minimum Specifications nductance Range: 0.5 microhenries to Suggested Model General Radio Type 1608-A 1100 henries. Capacitance Range: 0.05 pf.to 1100 mfd. Resistance Range: 0.05 ohms to 1.1 M ohms Accuracy: At 1 KC± 0.1% ±0.005% of full scale. Lowest Rand L ranges: ±0.2% ±0.005% of full scale Accessory Test Components Quantity tem Required Features Suggested Model 1 ea. Resistor 1 ea. Capacitor 1 ea. Resistor "R4" (Optional for Transmitter Test) 1 ea. Resistor "RS" (Optional for Transmitter Test) 1 ea. Switch lok ohm, W, carbon composition, 5% Polystyrene, mfd. ±10 pf, 100 voe 130 ohms, w Carbon Composition 5% 2000 ohms, 50 watt Toggle, SPOT J Series&. Parallel network of 9 polystyrene and silver mica capacitor: J Dale NH-SO J , p. 5-26

110 ea. Resistor 620 ohms, \W, 5%, J Carbon 1 ea. Resistor 130 ohms, w, 5%, J Carbon 1 ea. Resistor 1.3K ohm, \W, 5%' J Carbon Miscellaneous Accessories Suggested Quantity tem Required Features Model 20 ea. Nut AAR M ea. Nut AAR M ea. nsulated Nut AAR Ml ea. Bag Nuts & Washer AAR N ea. Terminal Strip AAR 2-way N ea. Tuning Tool nsulated JFD Type 5284 or Cambi on Type ea. Table Wooden, Approx. 4' High, Surface Area 3' x6' 1 ea. Yardstick 6042, p. 5-27

111 5.5 PERODC MANTENANCE A regular scheduled program for maintenance and inspection is recommended for the AV System that will not conflict with revenue service. As part of these regular procedures, the AV assemblies should be checked in the following manner. 1. Ensure that power is removed from the assembly to be inspected, and then remove the cover. 2. Make a thorough visual inspection of all wiring and cables. Check for frayed, loose or burned wires. 3. Check the physical integrity of all components. Look for burned or cracked components, loose solder connections, leakage of insulation compounds, and general physical damage. When a printed circuit board contains integrated circuit packages, ensure that all packages are firmly mounted. 4. f the internal panel surfaces and components have an excessive amount of dust deposited on them, use a soft brush and/or low pressure stream of air to remove the foreign material. CAUTON Do not clean PC boards or small internal components with a stiff brush or solvents, because damage to the circuits may result. A high-powered vacuum cleaner should NOT be used on small internal components. 5. Wipe the external surfaces of the assemblies with a soft damp cloth to remove dust, dirt or other foreign materials. 6. Reinstall any cover/s that were removed and restore power. 7. t is recommended that the system adjustment and timing be checked semi-annually, and if necessary, the procedures outlined in Section 4.3 be performed , p. 5-28

112 5.6 CAR-CARRED EQUPMENT TROUBLESHOOTNG (With Flow Charts) General The following procedure is a guide to bench test carborne AV equipment that.was determined to be faulty by direct substitution. The problems with the AV Car-Carried equipment can be divided into the following classifications: 1. No messages transmitted by a given car-carried unit as indicated by no messages received by the wayside: 2 Consistent error messages transmitted by a given carcarried unit, and received as error messages by the wayside. 3. Good messages transmitted by a given car-carried unit; however data is incorrect as follows: A. Car number incorrect B. Route number incorrect c. No routes decoded D. Cab signal indication defective E. Spare bit indications defective Suspect and/or defective car-carried equipment should be removed from the vehicle and replaced with known good equipment. The defective equipment should be returned to depot maintenance for repair. Before removing equipment, check for opens or shorts in cable assembly N and proper inputs from the vehicle to the prog?;"ammer via connector JS. Al'so check for proper mounting of the Transponder Coil N under the vehicle; verifying that the gap in the coil mounting frame is not closed by any metallic path or substance Required AV Equipment The procedures described herein are based upon the availability of a complete AV wayside as listed in Section 5.4.l(A) Wayside Equipment Preliminary Set-Up Verify that the required wayside equipment is properly connected and operational. Perform the Power Output and Tuning 6042 l? 5-29.

113 Adjustment Procedure and Received Signal Level Adjustments on the nterrogator, using a known good car set. Adjust the outpu for a 200 volt RMS level. Refer to Sections 4.3, 5.7 and Figure 513. Check system operation with a known good set of carborne equipment before proceeding Car-Carried Equipment Basic Set-Up Connect the Transponder Coil, Programmer, and nterconnecting cable o_f the car equipment, which is under test, together in its normal configuration. Place the Transponder Coil, over the Wayside Coil at 12-14" height, using a non-metallic spacer. WARNNG: Always make connections between coil and programmer with the coil away from the field of the Wayside Coil. Shock hazard from high voltage in unloaded tuned circuits of the Transponder Coil exists otherwise Basic Test and Programmer Troubleshooting With the car-carried equipment connected and the Transponder Coil in place at a 12-14" height over the Wayside Coil, check whether the Carrier Detect LED is lit in the decoder drawer of the wayside test set-up. l. Carrier Detect LED off-(dark). Problem - no signal received from Programmer; refer Section and the Flow Chart, Figure Carrier Detect LED on (lit). Remove Transponder Coil from over the Wayside Coil. The Carrier Detect LED in the decoder should go off (dark), and either the Good or Error LED should light. 2A. Error Message LED in decoder on (lit). Problem - incorrect message from the Programmer. Refer to the logic troubleshooting guide Section and Flow Chart, Figure 5-8, for troubleshooting information. 2B. Good Message LED in decoder on (lit). 6042, p This indicates that the basic timing electronics in the Programmer and the Transponder Coil are functioning properly. Possible problem - Data received and transmitted is possibly incorrect due to malfunction in switches or external status inputs. Refer to Section and Flow Chart, Figure 5-8, for troubleshooting details, as required.

114 ...,.. WABCO CAR CARRED EQUPMENT TROUBLESHOOTNG GUDE ' CONNECT ALL SWTCHES ANO CABLES TO DSASSEMBLED PRO GRAMMER. TRANSPONDER COL '>\.,z...,..,,...,.. 101,:i,11,. ' MEASURE DC VOLTAGE ACROSS ZENER OOOE JJ4 ANO 033 N 1ROGRAMMEA 1SOCVOLTS AT ZENER DODE OJ.4 APPROXMATELY 12TO 15VOC OR GREATER NO CHECK AC NPUT VOLT AGE AT CONNECTOR J4 PNA&PNB WTHACTVMOR OSCLLOSCOPE AC NPUT VOLTAGE 11 VOLT AC 153.&KHZ MNMUM NO CHECK FOR SHOATS N NPUT CABLE. SOCKET OR PCS i "' REPLACE TRANSPONDER COL ANO CABLE ASSEMBLY WJTH KNOWN GOOOUNTS ves ve,. l NO CHECK FOR SHORT ACROSS ZENER 033 "NO CAPACTOR Cl ANO CHECK FOR OPEN RESSTOR R3 t F SHORT STLL PRESENT CHECK FOR COPPER SHORTS OR DEFECTVE,cs l NO RESPONSE RECEVED AT WAYSDE CONNECT CAR CARRED EQUJPMENTSET PLACE TRANSPONDER COJL OVER 4i\Y"1iiDE <;Oil AT A 12-!l" <.te15ht f S CARRER DETECT teo N DECODER DRAWER OF TEST SETUP lllvmnated, ves!soc VOLTAGE ATOOOE 033 APPROXMATELY 9-12VOC CHECK FOR OPENS N CABLE ' AND OPENED OR SHORTED DODES 037THRUD40 * CHECK FOR SHORTED ZENER 034. SHORTED CAPACTOR C2 COH. OR CABLE DEFECTVE REPlACE AND CONTNUE TEST ves..... YE.... t CHECK FOR AN AC OUTPUT VOLT AGE ACROSS TVM """',s OUTPUT VOLT AGE ATJ4 CTOE 16 VOL TS AC RMS YNMUM L CHECK FOR SHORTS OR OPENS N CABLNG OPEN RESSTOR R 10 t CHECK FOR SHORTS OR OPE.NS N TRANSSTOR Q 1 & 02 DODES 035 & 038 ANO RESSTORS t CHECK FOR PROPER BASE DRJVE TO 01 & KHZ SQUARE WAVES 9-12 VOLT AMPLTUDE. AT C12 PNS 10& 11 NO YE_! REMOVE TRANSPONDER con. FROM OVER THE WAYSDE COL., CARRER DETECT LED N DECODER ORAR EXTNGUtShES.j isthe GOOD \4ESSAGE LED N THE OECOOER DRAWER OF THE TEST SET UP LLUMNATED NO STHE ERROR \.1ESSAGE LEO N THE DECODER DRAWER OF THE TEST SET UP _LLUMNATED_ YES ' Y_ AEPLACE THE TRANSPONDER C01LOVER THE WAYSDE.OL AT 1:.. fa."... t!jght t l CHECK FOR A KHZ PULSE TRAN AT C7 PN 10 ANO C2PN 10 S i: FG. 6-Z S 153.6KHZ SGNAL PRESENT AT 1C7PN to AND C2 PN 10 NO CHECK C7 CHECK RESSTOR Rl ANO CRCUT WRNG FOR SHORTS. OPENS r GOOD MESSAGES RECEVED AT WAYSDE CAR OR ROUTE NUMBERS R;ECEVEO NCORRECTLY PROGRAMMER LOGC S FUNCTONAL CHECK OAfA NPUTS t CHECK EACH CAR NO. SWTCH ANO ROUTE SWTCH FOR PROPER OPERATON CHECK DODES FOR OPENS ANO SHORTS YES.. - CH,:: ;;"'E TO SWTCHES PER FG. S-2 NOTE WELL WHEN CHECKNG OATASWTCHESANO STATUS NPUTS. PASS TRANSPONDER COLOVERWAYSOECOL TO RECORD DATA. THE TRACK CRCUT MVST BE CLEARED ANO REACTVATEO TO DECODE LEAD CAR & CAB SGNAL NDCATONS AT T,..E TEST DECODER. t CHECK FOR A 78.8 KHZ SQUARE WAVE AT C1 PN9AND Cl2PNS4.6,9. O. 11, 12, 15 THE 76.8KHZ SGNAL PRESENT NO CHECK THE RESET SGNAL AT C2 PN 11 ANO C8 PN 10 PER TMNG DAGRAM F'lG. 6 CHECK C8. A2 ANO C1 1F RESET PULSE Y_ GOOD MESSAGES RECEVED AT WAYSDE ROUTES NOT OECOOEO PROPERLY. CA8 SlGNAL OR OTHER STATUS BTS NOT RECEVED i PROGRAMMER LOGC S FUNCTONAL CHECK.STATUS NPUTS ' CHECK STATUS NPUTS USNG TEST NPUT CRCUT ANO EXTERNAl 30V DC POWER \J?P.Y SEE ;:'1$UA.E 6-3, CHECK WRNG TO JS FOR OPEfrtSOR SHORTS SHORTED OR OPEN DODES O,t1-41, 28-31, DEFECTVE OPTCAL SOLA TORS tc15 - tb ANOC14 - S NOT PRESENT + PROGRAMMER OK, REASSEMBLE ANO RETEST ALL NPUTS f DSASSEMBLED ' CHECK LOGC SGNALS PF.A T.UrMl CHART FtCUU! 6-4. AT C1, C2. C3, C7. C8, JC9 THESE SGNAtS ARE NOEPENOENTOF DATA FROM SWTCH 1NPUTS t SET ROUTE NUMBER TO 19 CAR NUMBER TO CONNECT STATUS NPUT TEST CRCUT TO CONNECTOR JS ENERGZE THE LEAD CAA STATUS BT f CHECK DATA DEPENDENT LOGC SGNALS AT C4. 5, , 14 PER TMNp CHART /F14URE 6 4. FPROBlEMS STLL EXST CHECK NSTALLATON ON CAR NCLUDNG WRNG NTERFACE REPLACE DEFECTVE COMPONENTS AS REQURED CHECK FOR SHOATS OR OPENS N PC BOARO OPPER REPLACE OEFi;CTVE COMPONENTS AS REQURED. CHECK DODES CHECK COPPER FOR OPENS OR SHORTS.. -::,..--:::-_: -...: -... _. Figure 5-8. Car-Carried Equipment Troubleshooting Flow Chart 6042, p. 5-31/32

115 NOTE WELL: The printed circuit board N used in the Programmer has been conformal coated with a clear insulating material to protect against dirt and moisture. t is necessary to pierce this material with pin tip probes or scrape the material off of connections to troubleshoot components. Also it is suggested that boards be resprayed with clear plastic spray, clear kyrlon or equivalent if components are replaced. Be extremely through in removing solder flux residue before recoating the board. Mask off switches and DP connectors to prevent spray from contaminating contacts Car-Carried Equipment Failure--No Signal Received From Car-Carried Equipment 1. Replace the Transponder Coil and cable with a known good coil, repeat basic tests in Section Refer to Sections and for Transponder Cable and Coil tests. 2. f symptoms still persist, examine the Programmer for loose cables or wiring connection. 3. Disassemble the Programmer, removing the printed circuit board, thumbwheel switch and connector cable assemblies. 4. With the Programmer disassembled, reconnect the thumbwheel switch cable assembly and output connector cable assembly to the Programmer, and replace Transponder Coil 12-14" over Wayside Coil. Refer to schematic, Figures 6-2 and Measure the voltage across zener diode 034. t should be between 12 and 15 volts DC. 6. f voltage is low or absent, check input voltage across connector J4-Pins A, B.using an AC TVM or scope. NOTE: Frequency is KHz. The voltage shouid be - at least 11 volts RMS. f voltage is present at J4-A, B, check for open cable connections from J4, A and B, open and/or shorted diodes 037 thru 040, shorted Zener 034 or capacitor C2. f no voltage is present, check for short in cable or C socket connections. 7. f voltage is present and correct across 034, check for approximately 9-12 volts DC across zener diode 033. f no voltage is present, check 033 or capacitor Cl for shorts and resistor R3 for open. 6042, p. 5-33

116 f a short exists with D33, Cl and R3 removed, check for a solder bridge in the VDD supply line to the Cs and defective Cs. Shorted Cs will be warm to the touch. 8. When DC voltage is correct across 034 and D33, check for an AC voltage across connector J4-C and E using the TVM. Minimum reading 16 VAC RMS; frequency 78.6 KHz. f voltage is correct, the Carrier Detect LED must be lit in the test decoder drawer. 9. f low or no AC voltage is present at J4-C, E, check transistors Ql and Q2, diodes DJS and 036 and cabling. Check for DC voltage across RlO and J4-D to common. 10. Check for r6.8 KHz squarewaes.rem C 12 pi 10 and 11 to the bases of Ql and Q2. f these signals are present and output levels are correct, Carrier Detect LED in decoder mus.t be lit. f the 76.8 KHz squarewaves are not present at C 12 pins 10 and 11, refer to the programmer logic troubleshooting guide in Section and follow the Flow Chart, Figure 5-8. NOTE that the squarewaves at C12 pins 10 and pin 11 must be 1800 out of phase Logic Troubleshooting Guide (Programmer) 1. Before attempting the steps in this procedure, perform all of the steps in Section l after disassembling the Programmer. 2. Set the route thumbwheel switch to 19 and the car number to Refer to the label inside of the top cover of the Programmer for.switch positions. Switch SW4 controls.the most significant digit (0) Switch SWl controls the least significant digit (3). 3. Connect the auxiliary input test circuit cable assembly, Figure 5-9, to connector JS. Place the polarity switch in the plus (+) position and energize the lead car indication using the first switch. 4. Refer to the detailed operation of the Programmer in Section of this manual for circuit operation. 5. Place the Transponder Coil, connected to the Programmer under test, over the Wayside Coil at 12-14" height. 6. Check the DC voltage at Zener 033 ; at least 9. volts DC must be present. A Logic 1 must be within 0.1 volts of this level. A Logic O is defined as O volts within 0.1 volt. 6042, p. 5-34

117 PS LE.AD C.AR. <A.SW'Z. DC POWER. NPUT. +36V Polarity SPAs:a.e l /E SW4 '-.,.,_- S.P.a.e 2. <G sws ov + B OP DT' C:.liM"ER OFC: \N D F Figure 5-9 Status nput Test Cable Assembly.. PS-AN3106A-20-7S J H 6042, p. 5-35

118 7. Check for a KHz pulse train at pin 10 of C7 and C2. f the output is not available, check C7 and resistor Rl. 8. Check for a 76.8 KHz squarewave at pin 9 of C2. f the signal is not present, check the logic level at C2 pin 11 and C8 pin The reset pulse at C8 pin 10 should be positive going pulse for cycle of the KHz clock. This reset pulse should occur every 20 milliseconds. Refer to Timing Chart, Figure Refer to Timing Chart, Figure 6-4, and check all the following signals per the timing chart. Signal Reset 2.4 KHz clock Bit counter stage 1 Bit counter stage 2 Bit counter stage 3 Frame O Frame 1 Frame 2 Frame 3 Frame 4 Frame 5 Frame 6 (pulse) Dump pulse Output shift pulse BCH reset BCH output enable Location C8 pin 10 C2 pin 2 C2 pin 4 C2 pin 13 C2 pin 12 Cl pin 2 Cl pin 1 Cl pin 3 Cl pin 7 Cl pin 11 Cl pin 4 Cl pin 5 C7 pin 4 C9 pin 10 C3 pin 14 C3 pin 1 These signals are the basic timing signals in the programmer logic and they must be present for proper operation. 6042, p. 5-36

119 11. f the timing signals are correct, check for the proper occurrence of the data related signals. NOTE: Sh Register Q8 CS pin 3 Data out C4 pin 11 PSK Data C13 pin 1 BCH circulate C4 pin 10 Parity C13 pin 13 These signals are dependent upon the data being.transmitted. The Timing Chart, Figure 6-4, defines the data related signals for the following data word lead car bit. {Route 19 car #0123). The printed circuit has been conformal coated to protect against dirt and moisture t is necessary to pierce this insulation layer with pin tip probes to read the signals. NOTE: When checking.the data output signals, it is advisable to trigger the scope externally on the appropriate frame signal during which questionable data is being outputted, and use.1 channel of a dual channel oscilloscope to display either the 2.4 KHz clock, the output shift clock or dump pulse as a reference to the various bit positions. The desired signal to be examined is displayed on.the second input channel of the oscilloscope. 12. f the logic and timing signals are occurring correctly, the programmer logic unit is functional. Remove the Transponder Coil from over the Wayside Coil, the Good Message LED in the test decoder must light Good Message - ncorrect Data. 1. Check each position of each route and car number switch to determine if the switches, cabling and diode array Dl-D31 are functioning correctly. 2. Connect the test cable assembly, Figure 5-9, to connector JS on Programmer. Energize each of the status inputs from switches on the test cable connected to connector JS. Place the polarity switch on the test assembly in the negative position to check the reverse bias protection diodes D41 thru 044, then place the polarity switch, on the status input test assembly, back into the positive position and recheck the status inputs. 6042, p. 5-37

120 NOTE WELL: When checking variable data from the route and car number switches and status inputs, it is necessary to place and then remove the Transponder Coil over the Wayside Coil to receive and decode data in the test wayside decoder. Also routing information in the decoder with Route Buffer and the cab signal status is decoded only from the first message received. The track circuit input (occupancy indication) to test decoder must be cycled off and on again, to guarantee that the next message received will be the first message in the simulated train. Also lead car, and/or cab signal status inputs must be activated via the status input test cable to connector Js on the Programmer. The status inputs can be checked on a terminal device connected to decoder drawer N equipped with an ASC interface Transponder Cable Assembly Test (N ll01) f the Transponder Cable Assembly is suspected of being defective, it can be checked, using an ohmmeter, for continuity and/or shorts. With an ohmmeter (Simpson 260 VOM or equivalent), measure continuity between pins on both ends of the cable. Measure Continuity Between: MS Connector Wire Between To Pin Color Ends of Wire Remaining Wires A Red 0 ±.25 ohms nfinity B Black 0 ±.25 ohms nfinity c White 0 ±.25 ohms nfinity D Shield 0 ±.25 ohms nfinity E Green 0 ±.25 ohms nfinity Also inspect the cable for mechanical integrity: 1. Cable must be free of nicks, cracks or burns. 2. MS connector hardware must be secure. 3. Strain relief boot must be installed properly. 4. Cable length must be 40 feet± 0.5 ft. 6042, p. 5-38

121 Transponder Coil Test (N ) The Transponder Coil assembly is molded in a sealed fiberglass unit to withstand under car environment, making repairs difficult. The coil can most easily be checked by substitution of a known good unit. NOTE: When examining the under car mounting, check that the gap in the coil frame is not closed by any metallic portion of the mounting assembly. Closing the gap will result in a shorted turn around the coil, effectively removing any magnetic signal coupling to and from the unit. f substitution is not possible, measure the coil windings resistance and inductance to verify wiring opens or short circuits. The circuit of the coil assembly is shown in Figur 5-10 below. COLS PCB CONNECTOR (Sl) 1 r ,6 (l PN E 16T 16T 12T Cl uf (S2/Fl) 2 1 Y. (F2) 3 a w. (@ (@ 4 9 Bk. C2 015µ f R (TAG) D c B- Figure , p. 5-39

122 Coil Characteristics Winding nductance DC Resistance Sl-Fl 104 µh at 76.8 KHz 2.8 ohms S2-F2 104 µh at 76.8 KHz 2.8 ohms Sl-F2 414 µh at 76.8 KHz 5.6 ohms A - B 69 µh at KHz 2.4 ohms A tolerance of ± 5% is allowable in all readings. The capacitors are mounted on a printed circuit board enclosed in the aluminum box on top of the coil assembly Resonant Frequency Tests The resonant frequency of each coil in the assembly can be determined using the test circuit of Figure NOTE: The coil assembly must be on a non-metallic surface. Also the forty-foot cable, N , should be used to make connections to the coil. The receive coil at pins A and B must resonate at KHz ±5.5 KHz. Resonance is indicated by a minimum reading (null) on the ab meter. After- determining resi"onant frequency, adjust the output level from the sinewave generator.to -10 db. Change the frequency above and below resonance until the meter reads -7 db. The frequency must be within 2 KHz of the resonant frequency. The transmit coil, connected to pins C and E, must resonate at 80.8 KHz± 3 KHz (unloaded) and the 3 db points must be within 1 KHz of resonance. 5.7 NTERROGATOR TROUBLESHOOTNG The following procedure is used to bench test the AV nterrogator Unit N , 0202, should it be determined to be faulty by direct substitution. As a further aid in troubleshooting the nterrogator, a Troubleshooting Guide is presented in Flow Chart form in Figure Physical nspection.. Before connecting the faulty nterrogator to the test circuit, a physi_cal inspection of the nte:rragator Unit must be made. 6042, p. 5-40

123 osc. SNE OUT COM FREQUENCY COUNTER. COM N COM TVM (db) N lk. A v"' TRAN SPONDER N CABLE. 40 FT. -_.._... N r---'..j...-- NON-METALLC WORK-TABLE TB - Ji:, KJ / y TB WRNG E -. Gre en D - Shield C - White B - Black A - Red 1, x Figure P s-41

124 Check for foreign material, blown fuse, broken, shorted or nicked wires, and for physically damaged components on the nterrogator Unit. nspect to insure that all interconnections between PCB's are properly inserted and that all connections are fastened securely, making good electrical connection. Replace all damaged components Required AV Equipment Refer to Section for necessary standard AV equipment Suggested Test Equipment Refer to Section for suggested test equipment Suggested Test Accessories Refer to Sections and for suggested test accessories Notes/Cautions/Warnings 1. WARNNG: USE EXTREME CAUTON WHLE OPERATNG APPARTUS AND ELECTRONC TEST EQUPMENT N THE PRESENCE OF THE AC NPUT SOURCE. 2. NOTE: t is recommended that in a noi sy electrical environment, the nterrogator rest in its metal case (N ) with the lid removed when testing. This partially eliminates stray capacitance, hc c effect the esured waveforms on some unit. 3. WARNNG: Should it be required for the nterrogator Unit to be grounded, all electrical test equipment (frequency counter, oscilloscope, etc.) used to test the nterrogator should be isolated from ground to prevent possible damage to the nterrogator unit. USE EXTREME CAUTON WHEN OPERATNG SOLATED TEST EQUPMENT: THE CASE MAY BE "HOT"! 4. s. NOTE: NOTE: The AC power from switch Sl on the Control PCB N connects between terminals 1 and 4 on terminal board A (see Figure 5-12). For 220 VAC operation, a jumper connects between terminals 2 and 3 on TB-A of the nterrogator Unit (see Figure 5-12). 6042, p. 5-42

125 6. NOTE: For 110 VAC operation, jumpers connect between terminals 2 and 4 and between terminals 1 and 3 on TB-A of the nterrogator Unit (See Figure 5-12). 7. NOTE: Only connections to Pins 1 and 3 on connector J7 of the Decoder Logic Unit are necessary for nterrogator Troubleshooting. (See Figure 5-14) nterrogator Transmitter Test NOTE: The nterrogator Transmitter operation can be tested two ways. One method is to connect up a complete AV instal_lation using a known good Wayside Coil, Transponder Coil, Programmer, Decoder drawer, and cables. The AV Transmitter circuitry can also be tested by substituting resistors R4 and RS for all the above equipment used for a complete installation (see Figure 5-12). Should resistors be used, the four Faston connections to capacitors Cl and C2 on the underside of the Control PCB N must be disconnected and insulated before assemblying test circuit. Failure to do so can result in extensive damage to the nterrogator Unit Output Check (See Figure 6-11) 1. Before assemblying test circuits, isolate the output tuning circuit of the nterrogator from the output transformer by disconnecting the two Faston connections to the tuning capacitors, Cl and C2, from the "Power Connector", pins B and E, on the underside of Control PCB N Make an ohnuneter check across one of the tuning capacitors Cl or C2 to assure that the output tuning circuit is not shorted. Measured resistance should be approximately 200K ohms. Should a large difference in resistance be measured, check that the correct Fastons have been removed, and for shorted tuning capacitors or defective voltage divider network on the Control PCB N With an RCL bridge, measure the capacitance of the output tuning circuit of the nterrogator. Make the bridge connections across one of the tuning capacitors Cl or C2 on the Control PCB. A. With a jumper between the terminals marked 1 and 2 on the Control PCB, the capacitance should be variable from approximately.0348 µf to.0361 µf by adjusting the Variable Tuning Capacitor. B. With a jumper between the terminals marked 2 and 3 on the Control PCB, the capacitance should be variable from approximately.0355 µf to.0368 µf by adjusting the Variable Tuning Capacitor. 6042, p. 5-43

126 .,_. ;., f the measured capacitance value is incorrect or not variable, a problem may exist with one of the output tuning capacitors on the Control PCB. NOTE: f the control PCB is still suspected of being defective or if any troubleshooting was performed on the PCB; then the AV nterrogator must be tested using a complete AV installation to fully check the operation of the voltage divider network nitial Procedure 1. Arrange a test set-up as per Figure Connect for either 110 VAC or 220 VAC operation. Use either resistors R4 and RS or a complete AV installation. 2. For test set-up using J Wayside Coil (see Figures 5-13 and 5-14): A. Use wooden table to support coil. B. When spacing Transponder Coil (N ) 12-14" above Wayside Coil, use a non-metallic spacer such as cardboard, wood, etc. 3. Before applying AC power, insure that: A. Switch Sl is turned off. B. nterrogator is wired correctly for either 110 VAC or 220 VAC operation. c. AC terminals on bridge rectifier are connected to terminals 1 and 2 on TB-B (near filter capacitor). D. Resistor "RS" or cable A and coil J ,. connected across terminals marked E and Fin Figure s-12. E. Resistor "R4", or Decoder Logic Unit, connected between terminals marked c and Din Figure F. f using resistors R4 and RS, the four Faston connections to capacitors Cl and C2 on the underside of Control PCB N must be disconnected. G. f using Wayside Coil J , the four Faston connections to tuning capacitors Cl and C2 on the underside of Control PCB N must be connected. H. RS and Rl8 on Amplifier PCB N are turned fully counter-clockwise at least five (5) turns. 6042,. p. 5-44

127 Transmitter Check (Refer to Figure 6-9) NOTE: The Transmitter circuitry is not operating properly if any of the following measurements do not meet the specifications: 1. Apply correct AC power, either 110 VAC or 220 VAC, depending upon how the nterrogator Unit is wired across points marked A ad B, as shown in Figure Connect VTVM across points marked E and Fin Figure With unit turned on, and by rotating RB clockwise, the output should be adjustable to over 200 VAC RMS. f the Wayside Coil is being used in place of resistor "RS", using a VOM set to the SOV scale measure the DC voltage across the meter terminals marked (+) and (-) on the Control PCB N The measured voltage should be 20V ±1 VDC with a 200 VRMS output to the coil. 3. Using a frequency counter, measure the frequency of the signal at test point 3 (TP3) on the Amplifier PCB N The frequency displayed on the counter must be the same frequency as stamped on crystal CRl, which. should be KHz ±15 Hz. 4. Look at the signal between TPlO and TP8 on the Amplifier PCB N with an oscilloscope. The displayed signal should be a KHz sinewave. WARNNG: HGH VOLTAGE 200 VAC RMS at KHz. 5. f all the preceding checks prove positive, the nterrogator Transmitter circuitry is operational and Section on Transmitter Troubleshooting can be skipped nterrogator Transmitter Troubleshooting f the Transmitter portion of the nterrogator is determined to be faulty, the following troubleshooting technique is recommended. (Refer to Figures 6-9, 6-11 and 6-13 for complete nterrogator wiring.) NOTE: All succeeding components and measurements in this section refer to the Amplifier PCB N unless otherwise noted (see Figure 6-9). 1. Using the test circuit of Section (see Figures 5-12, 5-13 and 5-14), measure the voltage between TP20 and TP19 (connnon). With power switch on, LED (LD2) should be lit and 36 VDC ±2 VDC should be present. Possible problem areas; check for a blown fuse on Control PCB N , improper or loose connections between PCB's and power supply, 6042, p. 5-45

128 m 0,&:> t-..>... 'O U1 m TB-B TB-A NOTE: oo ) CABLE N4514S l VARABLE TUNNG CAPACTOR CABLE JUMPER SHOWN N N4Sl VAC NPUT CONFGURATON.. CABLE TAG NUMBER NOTE l & 2 CASE N4Sll ;30 cable A Figure AAR TERMNAL STRP»- Fl Fl»,7".. RETURN SGNAL TO DECODER J78002, t OR J NOTE 3 Wayside Test nterconnections "RS". +i 'L., OR._J NOTE 3 & 4 NOTES: l)ac Power from switch Sl PCB N4510S5-69XX connects between terminals 1 and 4. 2)For 110 VAC operation connect jumpers between terminals 2 and 4 and between terminals 1 and 3. 3) Resistor "R4" and "RS" optional for nterrogator transmitter check. 4)Resistor R4 optional for nterrogator transmitter tuning procedure.

129 (length as CABLE desired) TWSTED PAR N45l SUB-PLATE ASSEMBLY DECODER LOGC UNT PROGRAMMER N CABLE N YARD STCK COL J l CAR CARRED. TRANSPONDER COL...7" N " CASE CABLE TAG NUMBERS CABLE A FEET WOOD TABLE *Connectors J6 and J8 on the Decoder Logic Unit need not be connected for nterrogator troubleshooting. Figure , p. 5-47

130 ' 0.&::. \).. 'O lj1.&::. co RETURN SGNAL FROM. NTERROGATOR SGNAL B SGNAL A 12VDC ±.25VDC t-3 f+ POWER SUPPLY SWl H u z t-3 ti H e H 0 z ti H H e fa H 0 z " \) +! a CAB SGNAL RELAYCOMMQN... CAB SGNAL RELAY OUTPUT... ( co, ) n l t\j t! H H H H H H z z z z z z w... U --' W --'... \D...i } 117 VAC-60 Hz TO EXTERNAL EQUPMENT.AS REQURED & JG J7 JS DECODER LOGC UNT NOTE: Only connections to pins l,and 3 on connector J7 are necessary for nterrogator troubleshooting. Figure 5-14

131 bad LED, open resistor R31, and a defective power supply. (Transformer, capacitor and rectifier are mounted on chassis). NOTE: f fuse is blown, check for the possibility of a short in the AC line or DC power circuit. 2. Measure the DC voltage between TPl and TP19. There should be 20 voe ±2 voe present. Maximum voltage is obtained with the position of RS fully counter-clockwise. f measured value differs, check zener diode Dl, resistor Rl for open, and capacitor Cl for a short. 3. Measure the frequency at TP2. The measured frequency should read KHz ±15 Hz. Also check the signal at TP2 with an oscilloscope. The displayed waveform should be a clipped signal which resembles a squarewave (see Figure 5-15). The voltage should read. 11.0V p-p ±2 V p-p on scope. f the measured frequency is off by a small amount, it may be corrected by adjusting capacitor C3 on the Amplifier PCB. Otherwise, look 'for possible opens and shorts within the oscillator and filter circuitry sections on the Amplifier PCB N Measure the frequency at TP3. The frequency should remain at KHz ±15 Hz. Observe the signal at TP3 with an oscilloscope. The displayed waveform should be a sinewave with a voltage of 11 V p-p ±2 V p-p (see Figure 5-16). The maximum voltage at TP3 should be when RS is positioned five turns counterclockwise. f no signal is present or if waveform remains distorted, check the filter components and potentiometer RS on the Amplifier PCB. 5. Observe the sianal at TP5 with an oscilloscope. By adjusting RS, the signal at TP5 should be variable from OV to approximately 65 V p-p maximum, with some clipping of the signal. The maximum signal amplitude for a sinewave without clipping should be approximately 55 V p-p. With RS five turns counterclockwise, the DC voltage at TP5 measued with a VOM should read 38 voe ±2 voe. n case of no signal, distortion, or little or no amplification at TP5,.check the transmitter cascaded Class A amplifier stage, transistors Q9 and Q4 and connecting components for possible faults. To continue testing, or if amplifier stage is operational, temporarily set the amplitude of the AC waveform at TP5 to maximum amplitude without clipping, as observed on the oscilloscope by adjusting RS. 6. Connect one channel, of a dual channel oscilloscope, between Fastons marked Al and Gl (common) on the Amplifier PCB, and the other channel to Faston marked A2. By adjusting RS, two sinewaves 1800 out of phase with each other should be displayed on the oscilloscope (see Figure 5-17). 6042, p. 5-49

132 For normal operation, with the output voltage across resistor RS or the coil set to 200 VRMS ±10 v RMS, the signals at Al and A2 should be approximately 5.5 v p-p sinewaves. When using resistor loads {R4 and RS), the voltage should be approximately 4.5 V p-p. f little or no signal is measured, problem areas might be an open primary or shorted secondary of transformer Tl, and/or shorted bias resistors R27 and R Measure the output voltage of power transistors between TP7 and TP6 with a VTVM. Output voltage should read approximately 35 V RMS ±5 VRMS for normal operation with 200 V RMS ±10 V RMS output to either the coil or resistive load {RS). The signal should still be a sinewave. Possible problem areas, check output power transistors and emitter resistors on nterrogator Chassis {see Figure 6-13), and primary of transformer T2 on the Amplifier PCB. 8. Measure voltage between TPlO and TP8 on the Amplifier PCB with VTVM. Voltage should be adjustable to over 200 V RMS for either coil or resistive loads by adjusting RB. The signal, when observed with an oscilloscope (CAUTON: HGH VOLTAGE), should be a sinewave. f measured values disagree, check transformer T2 for shorts on the Amplifier PCB. 9. f a Wayside Coil and cable are being used in place of res±stor RS, use a VOM set to the 50V scale to measure the DC voltage across the meter terminals marked (+) and (-) on the Control PCB N The measured voltage should be 20V ±1 VDC with a 200 V RMS output to the coil. ncorrect readings indicate a defective voltage divider network on the Control PCB Power Output and Tuning Adjustments The following procedure is used to tune a working nterrogator Transmitter output and adjust its output level. This procedure must be performed with the Wayside Coil J and 30 ft. cable A connected across points marked E and Fin Figure 5-12 and with.all Fastons connected on the underside of the Control PCB N Resistor R.4 may be used in place of the Decoder Logic Unit, also the Transponder, Programmer and connectig cable are not needed nitial Procedure 1. nsure that all Faston to capacitors Cl and C2 on.the underside of Control PCB N are connected. 6042, p. 5-50

133 2. Before applying AC power, insue that resistor RS is not connected with coil. 3. f unable to tune nterrogator as per next section, repeat nterrogator troubleshooting procedure, Section 5.7, using the Wayside Coil Tuning Procedure (See Figure 6-11 and Figure 6-12) Refer to Section nterrogator Return Signal Test Notes 1. n order to test the receive portion of the AV nterrogator, the Transmitter portion of the nterrogator must be operating properly. f not sure of the unit's operation, refer to Sections and on nterrogator Transmitter testing and tuning. 2. The receive circuitry of an nterrogator Unit must be tested using a complete AV unit. This includes a known good Transponder Coil, Programmer, Wayside Coil, Decoder Logic Unit and cables. Resistors R4 and RS cannot be used for this procedure and all Fastons on the underside of the Control PCB N , if disconnected for a revious test, must be reconnected to their initial positions nitial Procedure 1. Place the Transponder Coil N (connected to a Programmer} 12-14" above Wayside Coil, using a non-metallic spacer such as cardboard, wood, etc. 2. Before applying AC power, insure that: A. Coil and cable A is connected across terminals marked "coil" in Figure B. Cable to Decoder Logic Unit is connected between terminals marked C and Din Figure nterrogator Return Signal Testing (Refer to Figure 6-9.) NOTE: Should any of the following test results be incorrect, the receive circuitry of the nterrogator is faulty. See Section for troubleshooting procedure. 6042, p. 5-51

134 1. Check connections on TB-A (near transformer) for either 110 or 200 volt operation and apply correct AC power across points marked A and Bas shown in Figure Connect VTVM across points marked E and Fin Figure Switch unit on and rotate RB on Amplifier PCB N clockwise until 200 V RMS ±lov RMS is indicated on VTVM across coil. 3. Connect signal probe of an oscilloscope to TPS on the Receiver PCB N of the Decoder Logic Unit and connect common to TP3. The waveform displayed on the oscilloscope, by adjusting Rl8 in the nterrogator should resemble the picture in Figure 5-18 and The zero crossings of the waveform should be distinct and well defined, or inductor L2 on the nterrogator Amplifier PCB N may be out of tune. See troubleshooting procedure, Section Remove oscilloscope and connect VTVM (0 db scale) to test points TP5 and TP3 on Receiver card in the Decoder Logic Unit. With Transponder Coil 12-14" over Wayside Coil and by adjusting potentiometer Rl8, the output on VTVM should be adjustable between -5 and -15 db. 5. f no problems were encountered in Steps 1-4, then the return signal portion of the nterrogator Unit should be in proper working order and ready for adjustment (see Section 5.7.9) nterrogator Return Signal Troubleshooting f the return signal portion of the nterrogator is determined to be faulty, the following troubleshooting technique is recommended (refer to Figures 6-9 and 6-11). 1. Connect VTVM across points marked E and Fin Figure Switch unit on and adjust RB on Amplifier PCB N until 200 V RMS ±10 V RMS is indicated on VTVM across the Wayside Coil (points E and Fin Figure 5-12). 2. Connect signal probe of an oscilloscope to TPll on the Amplifier PCB N and connect common to TP8. With a Transponder Coil (connected.to a Programmer) placed 12-14" over the Wayside Coil, a 76.8 KHz signal, mixed with a KHz signal, should be displayed on the oscilloscope (see Figure 5-20). The measured voltage on the oscilloscope should be approximately 4 volts p-p. When the Transponder Coil is removed from over the Wayside Coil, a KHz sinewave of approximately 1 volt p-p should appear on the oscilloscope. Should the observed signal be considerably differ_ent from that of Figure 5-20, check the KHz parallel resonant trap (Ll, C27 and Cl7) on Amplifier PCB 6042, p. 5-52

135 N nductor Ll of the parallel tuned circuit should be set so that a null (minimum signal) is obtained at TPll with the Transponder Coil removed. Also, check the parallel tuned circuit (C18 and L2) on the Amplifier PCB N nductor L2 and capacitor Cl8 should resonate at approximately 76.8 KHz. nductor L2 is tuned for best zero crossing per Step Measure the signal at TP12 (TP19 is ground) on Amplifier PCB N with an oscilloscope. With the output to the Wayside Coil adjusted to 200 V RMS ±10 v RMS, the amplitude of the signal should be approximately 2 volts p-p on a properly adjusted unit. f little or not output appears at TP12, check components and connections between the secondary of L2, resistor R29, and potentiometer Rl8 on Amplifier PCB N Measure the DC voltage at TP14 on Amplifier PCB N with a VOM. Voltage indicated on VOM should be 35 VDC ±2 VDC. Check bias component of.receiver class A amplifier line driver stage (transistors Q7 and Q8) if a different value is measured. 5. Observe the signal at TP15 on Amplifier PCB N with an oscilloscope, the displayed waveform should resemble Figure For operation with R8 adjusted for 200 V RMS across the Wayside Coil, and Rl8 adjusted for a -10 db signal at TPS and TP3 on the Receiver PCB N of the Decoder Logic Unit, a voltage of approximately 12 volts p-p should appear at TP15. n case of distortion, little or no amplification at TPlS, check components and connections in the receiver cascaded Class A line driver stage (transistors Q7 and Q8 and connecting components). 6. Connect one channel of a dual channel oscilloscope between TP18 and TP17 (common) on the Amplifier PCB N and the other channel to TP16. By displaying in the alternate mode, two signals 180 degrees out of phase with each other should be displayed on the oscilloscope (see Figure 5-22). When the nterrogator is operating with 200 volts across the Wayside Coil and a -10 db signal at TPS and TP3 of the Receiver PCB as in the previous step, then the voltage for each waveform on the scope should read approximately 1.5 volts p-p. For possible problem areas, check the secondary of transformer T3, LED (LDl) and resistor R32 on the Amplifier PCB N Connect the oscilloscope to TPS and TP3 (TP3 is common) on the Receiver Board N of the Decoder Logic Unit. f no problems were encountered in Steps 1-6, then by adjusting Rl8, the displayed waveform should resemble Figures 5-18 and f the zero crossings are not distinct and well defined, try adjusting inductor L2 on 6042, p. 5-53

136 the Amplifier PCB N otherwise check the tuned circuit consisting of inductor L2 and capacitor Cl8. With VTVM connected in place of the oscilloscope and by adjusting Rl8, the output on the Receiver should be adjustable between -5 and -15 db Received Signal and Level Adjustment Notes 1. The following procedure is to be performed on a verified working nterrogator. f unsure of operation, perform nterrogator Transmitter Test (refer to Section 5.7.6; Parts through inclusive) and Return Signal Test (refer to Section 5.7.8, Parts through inclusive) before continuing Adjustment Procedure Refer to Section , p. 5-54

137 Figure 5-15 nterrogator (Transmitter) TP2 Figure 5-16 nterrogator (Transmitter} TP3 Figure 5-17 nterrogator (Transmitter) Al/Gl (Top) A2/Gl (Bottom) 6042, p. 5-55

138 Figure 5-18 Receiver TP5/TP3 Typical Message Form.at Figure 5-19 Receiver TP5/TP3. (Expanded) Zero Crossing 6042, p. 5-56

139 Figure 5-20 nterrogator (Return Signal) nterrogator TP11/TP8 Figure 5-21 nterrogator (Return Signal) nterrogator TP15 Figure 5-22 nterrogator (Return Signal) TP18/TP17 (Top) TP16/TP17 (Bottom) 6042, p. 5-57/5

140

141 WABCC "-t' NTERROGATOR PROBLEM CHECK NPUT ANO OUTPUT CABLE TERMNALS;ALSO CHECK FOR SHORTS AND OPENS N COL ANO CABLE CHECK TRANSMTTER AANSMTiCR )P!':!A';"fCHAL TUrtN S GAt. i:hec!c US!G :o,-,ur! AY ltst't'. :ti.ac! -\ <MOWN ;QOQ UAH:SMMDU MT l:z T'Q f.'" JVE:l :lit, ND :=Jut tt ic.::p! ACROU ;,, \110 :CmfOJf, :N 1!Cl: YU v-_s ves REPtACe FUSE ADJUST RB S020VOC on 'METEQ.. NTERROGATOR OPERATONAL OiECKCABLE TO DECODER.. CHECK POWER ANO CABlE FROM RACK ROOM: REPAR CONNECT VOM TO TESTPONTS ffl.190n AMPLFER BOARO -:H!CK '3.s <Hz AHO :-a.a -<Hi:!UHl 0 CRCUTS 1 GOTO DECODER DEFECTVE UD 2 ORA31 ON AMPLFER BOARD; REPAR CONNECT VOM TO TESTPOHTS ONAMP1.FER BOARD NO CONNECT KNOWN GOOD con. ANOCABU CONNECT SCOPE TO TESTPONTS Q.BON AMPLFER BOARD CHECK U. =129 ANO,Ut CONNECT sec..! 'l"q T"l9 oln UPL1'1tR.ica. ':'Pl% ANO' DEFECTVE CONNECTtONS TO AMPUFER BOARO;REPAR DEFECTVE CONTROL BOARD OR CONNECTONS: REPAR CHECKT20N AMPLFER BOARD OR OUTPUT TRANSSTORS; REPAR CONNECT score TO TF.STPONTS 8-7 ON AMPtlFER SOARD vu CONNECT 5COP! TO ip,.19.no YON 'to TPf ht' OH A.MPlr,1u1 PCS. CHECK Tl ON AMPLFER BOARD OR OUTPUT TRANSSTORS: REPAR CHECK!AS ilp!rat10h =o rc:==: l!ri;. SECTON,. 7.s.,. HPS & ANO,. Y!S DEFECTVE BRDGE. FLTER CAPACTOR. OR CONNECTONS: REPAR CHECK ANO SUPPORT CRCUTRY ON AMPUFER BOARD ANO REPAR NO :CNN[C'f SCOPE TO TP 6-l 7 ANO TSS l 71 ON o\mf'll "ER 111:9., DEFECTVE FllTER: REPAR CONNECT COUNTER ANO SCOPE TO TESTPONTS 2-Ut ON AMPLFER BOARD CHECK T'J. LEO (LO J ANO. 11)2. DEFECTVE TRANSFORMER: REPAR DEFECTVE OSCLLATOR CRCUT; FRST CHECK CR t. 01. ANOQ20N J\MPUFER BOARO: REPAR CONNECT VOM TO TESTPONTS 1-19 ONAMPUflER BOARD DEFECTVE CONNECTONS TO AAA TERMNALS: Al.SO CHECK CONTROl 80AAD ANO SWTCH; REPAR DEFECTVE ZENER 01, RESSTOR Rt. OR CAPACTOR Cl: REPAR Figure nterrogato Troubleshooting Flow Chart 6042, p. 5-59/60

142 5.8 WAYSDE COL The following procedure is used to determine if the AV Wayside Coil, J , is operating properly Physical nspection (Refer to Figure 6-31) Any Wayside Coil (J ) suspected to be faulty should undergo a physical inspection before testing its operation. nsure that the fiberglass mold of the Wayside Coil is not broken and that it. is free from cracks. There should be no wires visible through the fiberglass mold other than the connecting cable. The.connecting cable should have a fiberglass seal around it, and it should be free from breaks, shorts and nicks. All defective units should be replaced Suggested Test Equipment Refer to Section Test Accessories Refer to Section Test Procedure NOTE: f any of the values obtained in the succeeding measurements are considerably different than the given approximate values, then the coil unit is defective and should be replaced. 1. Measure the DC resistance of the Wayside Coil, J with an impedance bridge. The measured resistance should be approximately 100 milliohms ±20%. 2. Measure the series inductance of the Wayside Coil with an impedance bridge. The measured inductance should be approximately 26.0 micro-henries ±10%. 3. Arrange physical test set-up as per Figure Arrange an Electronic Test Set-Up as shown in Figure P 5-61

143 NOTE: The Mfd ±10 pf capacitor can be made up using a series and parallel capacitor network of polystyrene and silver mica capacitors. 5. Adjust oscillator amplitude to 20V ± 1 V p-p sinewave at the output terminals. 6. Vary the frequency of the oscillator between 50 KHz and 200 KHz. A peak on the oscilloscope should appear at 165,000 Hz ±4000 Hz. f a different value is measured, recheck the circuit of Figure -25 and the value of the Mfd. capacitor with an impedance bridge. Should no problems be found within the test circuit, then the coil is defective and should be replaced. 6042, p. 5-62

144 FBERGLASS MOLD UNNG CAPACTOR WOOD TABLE..._ Figure 5-24 FREQUENCY COUNTER Output OSCLLATOR. Common lok W MFD. osclloscope Common WAYSDE COL Figure , p. 5-63'

145 5.9 DECODER LOGC UNT TROUBLESHOOTNG General The following procedure is presented as a guide to bench troubleshooting Decoder Logic Units that are determined to be faulty by direct substitution Malfunction Symptoms Decoder Logic Unit failures can be divided into the following classifications: 1. No messages received or decoded. 2. Consistent errors in every message. 3. Good messages received, however, data is incorrect as follows. A Car or route numbers decoded incorrectly. B. Cab signal indication and relay inoperative. 4. Optional interface failures--refer to interface troubleshooting guides in supplementary manuals Fault solation This section is presented as an aid in isolating a fault to a particular subassembly of the Decoder Logic Unit, i.e., Power Supply, Power Distribution and nterface PCB, Receiver PCB, Decoder Logic Panel and connecting cables. As a further aid, a troubleshooting guide, in Flow Chart form, (Figure 5-36) is also presented. Detailed troubleshooting instructions are included for each subassembly in following sections of this manual. 1. Remove the cover from the defective Decoder Logic Unit by unfastening the two turn fasteners. 2. Remove any and all interconnecting cables between the Decoder Logic Panel and optional interface panels if so equipped (from connectors Jl-1 and J2-2 on Decoder Logic Panel). Refer to the tag inside of top cover for connections (see Figure 5-26). 6042, p. 5-64

146 < J6 J6 "" JS..,. POWER DST. & NTERFACE UN J7 Jl '""' U\ l J4 -- r u1rnllll POWER SUPPLY UJ AC AC - + ' 0.s:,. N... "CJ ] J- n-2 J2-4 r:::j... i i LJ BG Lio ERROR / GOOD MESSAGE MESSAGE CARRER DETECTOR O O TRACK CAB O O KEY ON SGNAL 863 DECODER UN UN TEST DECODR 2 NORMAL < 3 TEST RECEVER TWSTED PAR P' RECEVER UN Ul ' U1 Figure Decoder Logic Unit Major Component Location

147 3. Connect 117 volts, 50/60 hertz across pins A and B of connector JS on rear of decoder drawer. Energize the AC and turn on the power switch located on the Decoder Logic Unit. Refer to Section for mating plug part numbers. 4. The light emitting diode Dl on the Power Distribution and nterface PCB should be lit. f so, go to Step 5. f not, check: A. Front panel fuse and switch. B. AC input to power supply at power supply; replace defective wiring or shorted varistor on Power Distribution and nterface PCB. C. Remove connections Bl and Nl from Power Distribution and nterface PCB. Check for volts DC unregulated output of power supply. NOTE, some decoder drawer power supplies have a one (1) amp. fuse inside unit. Check this if DC is not present and then troubleshoot the power supply. D. Reconnect the positive output of the power supply to faston Bl and the common to faston Nl. f the LED on the Power Distribution and interface board does not light, remove Connector J3 from Power Supply distribution and nterface PCB and check input and output voltages on the regulator per Figure The regulated output should be 12 to 15 volts, unloaded. f impropr voltages are present,check regulator per Section E. f the LED comes on and voltage output is within specifications, replace jumper cables to Decoder Logic and Receiver PCB. f the LED goes out again, look for a short in Decoder Logic Panel or Receiver PCB power wiring. 5. Verify that 12 volts DC is applied to the Decoder Logic Panel and Receiver PCB, per Figures 6-16, 6-18, 6-19 and Check that the Test Switch, on the Receiver PCB, is in position 2 (Normal). All LEDs on the Decoder Logic Panel and Receiver PCB should be off. f not, refer to Receiver PCB troubleshooting Section to check the switch and LED on the Receiver PCB and, to Decoder Logic Panel troubleshooting Section to check improper LED operation. 7. Place the Test Switch on the Receiver PCB to position 1. (test decoder). This tests the Decoder Logic Panel. 6042, p. 5-66

148 A. LED 1 on the Reeiver PCB should light. f not, go to Receiver PCB troubleshooting Section to check the-switch and LED 1. B. On the Decoder Logic Panel, the Track LED should be on and the Good and Error Message LEDs should alternately flash on and off. The Cab Signal, Key-On and Carrier Detector LEDs should be off. f not, replace the cable between receiver and decoder, then go to Decoder Logic Panel troubleshooting, Section Place the Test Switch on the Receiver PCB to Position 3 (test receiver). This tests the Receiver PCB in conjunction with the Decoder Logic Panel. A. On the Receiver PCB, LED 1 should be lit. B. On the Decoder Logic Panel, the Track LED should be lit, the Carrier Detector LED should be blinking on and off rapidly, and the Good and Error Message LEDs should be alternately flashing on and off. Key-On and Cab Signal LEDs should be off. f not, replace the cable between the Decoder Logic Panel and Receiver PCB, troubleshoot the Receiver PCB Section 5.9.6, then troubleshoot the Decoder Logic Panel Section Verify that the required AV! equipment is properly connected and operational. Perform the power output and tuning adjustment procedures on the nterrogator using a known good car set and decoder drawer, see Section Connect the Decoder Logic Unit, under test, to the known working nterrogator per Figures 5-12 and Connect a 12 volt DC power supply to the track circuit input as shown on Figure Place the test switch on the Receiver PCB in the Normal position 2 (center position). 11. Energize the decoder and track circuit input power supply. The Track and Key-On LEDs should both light. All other LEDs on.the decoder should be off. f not, check the.decoder Logic Panel Section and the Power Distribution and nterface PCB Section , p. 5-67

149 12. Connect the Transponder Coil Programmer and interconnecting cable of the carborne equipment together in its normal configuration as per Figure Place the Transponder Col over the test Wayside Coil at a 12" to 14" height, using a non-metallic spacer. WARNNG: Always make connections between Transponder Coil and Programmer away from the field of the Wayside Coil. Shock hazard from induced high voltages in unloaded tuned circuits of the Transponder Coil exist otherwise. 13. With the Transponder Coil over the Wayside Coil, the Carrier Detector LED in the decoder should be on. f not, check the wiring from connector J7 through the Power Distribution and nterface PCB to the Receiver PCB. See Section Remove the Transponder Coil from over the Wayside Coil, the Carrier Detector LED should turn off and the Good Message LED should light. This indicates a working decoder. Go to Step 15. f the Error Message LED lights, or neither the Good or Error Message lights, trace the signal input from the input Connect9r J7 through the Power Distribution and nterface PCB to the Receiver PCB and Decoder Logic Panel. 15. Turn off the power supply to the track circuit input. The Good Message, Track and Key-On LEDs should go off. f not, check the Decoder Logic Panel Section and Power Distribution and nterface PCB Section Connect the status input test cable assembly, Figure 5-9, to the Programmer and energize Lead Car and Cab Signal switches. 17. Connect an ohmmeter across the cab signal relay contacts, Connector J7, Pins 7 and 9. The meter should indicate an open circuit. 18. Energize the track circuit input and pass the Transponder Coil over the Wayside Coil and then remove the Transponder Coil. The Cab Signal LED should be on, along with the Track, Key-On and Good Message LEDs. f not, check the Decoder Logic Panel Section The cab signal relay contacts should be closed. f not, check the cab signal relay on the Power Distribution and nterface PCB Section and interconnecting cables. 19. Deenergize the track circuit input power supply. All LEDs on the decoder should go off _and the cab signal relay contacts should be open. 6042, p. 5-68

150 20. Repeat Steps 15 through 18 with the cab signal status input to the transponder off, then again with the lead car input to the transponder off. n neither case should the Cab Signal LED or relay be activated. Otherwise check the Decoder Logic Panel. 21. f all of the LEDs on the Decoder Logic Panel and Receiver PCB indicate correct operation in all modes, but the Data outputs are incorrect, check the Power Distribution and nterface PCB, Decoder Logic Panel outputs and interconnecting cables. 22. f all tests are passed correctly, the basic Decoder Logic Unit is functioning correctly. Refer to option checking procedures to check the optional interface panels as required Power Supply Troubleshooting All Decoder Logic Units contain a 12 volt unregulated DC power supply (Standard Power Supply Model #15CB12). Should this power supply be determined to be defective, either the internal wiring and components (transformer, diodes, fuse and filter capacitor) may be checked, or the power supply may be replaced. New power supplies may be purchased from any Standard Power ncorporated distributor or from the Union Switch & Signal Division of WABCO. Our part number.is J Power Distribution and nterface PCB Test General The following procedure is intended as a guide for testing the operation of the Power Distribution and nterface PCB, N (See Figure 6-28). As a further aid in troubleshooting the Power Distribution and nterface PCB, a Troubleshooting Guide is presented in flow chart form in Figures 5-27, 5-28 and nitial Procedure 1. The Power Distribution and nterface PCB to be tested should be installed in the Decoder Logic Unit of a working AV! System at the maintenance facilities. 2. Disconnect connectors J3, J4 and JS from the Power Distribution and nterface PCB. 3. Remove all connections to connectors J6, J7 and JS from the back of the Decoder Logic Unit. 6042, p. 5-69

151 Power Supply Test 1. Remove the AC power input Fastens from the Power Distributio and nterface PCB; measure the resistance between Fastens CXl and BX! on the PCB using a VOM. f a short should exist, check the Metal Oxide Varistor {MOV) across CXl and BXl. 2. Connect 117 volts AC 50/60 hertz across pins A and B of connector JS on the rear of the Decoder Logic Unit. Turn on the power switch on the Decoder. LED Dl should light and the unloaded DC voltage between (+V) and {GND) on connector J3 should be approximately 13 ± 0.5 voe. f problems exist, check the components and connections of the voltage regulator portion of this PCB. Check Zener diode 02 {13V), Dl, Ql, Cl and C2 for shorts and resistors Rl, R2, R3 and LED Dl for opens EA Data Channel Test 1. Preliminary Connect two 12 voe power supplies to the Power Distribution and nterface PCB as follows: A. +12 voe to connector J7 pin 15 (EA + Volts) B. -12 voe to connector J7 pin 17 (EA - Volts) c. Ground to Fasten Nl (GND) 2. Key-On Optical solator Test A. Turn on the Decoder Logic Unit and external power supplies. B. Using a VOM measure the voltage at connector J7, pin 19 {Key-On output signal) with respect to ground. The voltage should be approximately +12 voe. c. Ground pin 11 of connector J3 {Key input signal), the _voltage should be approximately -11 voe. ncorrect readings indicate a possible problem with the Key-On optical isolator Cl, its connections or resistors R4 and RS. 3. Transmit Data Optical solators A. Turn on the Decoder Logic Unit and external power supplies. B. With power applied as in 1 (above), use a VOM to measure the voltage of the Transmit Data signal at pin 18 of 6042, p. 5-70

152 connector J7 with respect to ground. indicate a voltage from Oto ±.5 voe. The VOM should c. Ground the Data signal at pin 12 of connector J3. The measured voltage should be approximately +11 voe. Problems indicate optical isolator C2, its connections, or related components may be defective. D. Remove the ground from the Data signal at pin 12 and ground the DATA signal at pin 13 of connector J3. The Transmit Data signal voltage should be -11 voe indicated - on the VOM. Problems indicate optical isolator C5, its connections, or related components may be defective Track Signal Test A. Apply +12 voe to the Track ndication signal at pin 11 of connector J7, and common to the Track ndication Common signal at pin 13 of connector J7. B. Ground pin 10 of connector J3 (Track GND signal) to the Decoder Logic power supply common. Measure the Track output signal voltage at pin 9 of connector J3 with respect to common. The measured voltage should range from o to +.5 voe. c. Switch off the external 12 V supply to connector J7. The voltage at the Track output should rise to approximately 11 VDC; also, monitor a time delay (0.1 second) before this voltage rises to its final value. ncorrect readings indicate that optical isolator C3, its connections and/or its related circuitry may be defective Cab Signal Test A. Turn on the Decoder Logic Unit and ground the Cab input at pin 8 of connector J3. B. Using a VOM,measure the resistance of the cab signal relay contacts, between pins 9 and 7 of connector J7. The measured value should range from Oto.4 ohms. c. Disconnect the ground from the Cab signal. The resistance indicated on the VOM should approach infinity. Problems indicate either a defective relay (C4), power connections, and/or related components. 6042, p. 5-71

153 POWER SUPPLY CHECK CAB SGNAL CHECK START START REMOVE CONNECTONS TO CONNECTORS J3,J4,J5,J6,& J7 REMOVE CONNECTONS TO CONNECTORS J3,J4,J5,J6,& J7 MEASURE RESSTANCE BETWEEN FASTONS CX AND BX SWTCH ON POWER TO THE DECODER LOGC UNT YES CHECK FOR SHORTED COPPER OR DEFECTVE MOV BETWEEN FAS TONS SEE POWER SUPPLY FLOW CHART SWTCH ON POWER TO THE DECODER LOGC UNT GR0UMD CAB SGNAL NPUT CHECK CONNECTONS, RELAY C4, AND R,C4 CHECK VOLTAGE REGULATOR. CRCUT REPLACE LEO REMOVE GROUND FROM CAB SGNAL NPUT NO POWER SUPPLY OUTPUT S OPERATONAL CAB SGNAL NDCATON OPERATONAL 6042, p Figure 5-27

154 START REMOVE CONNECTONS TO CONNECT0RS J3 J4,J5,J6, & J7 EA DATA CHANNEL APPLY: +SVOC TO EA>V -15VOC TO EA-V GROUND TO GNO CHECK C':NEC1' CNS C2.C5.tNO PELATEO CtAP':tiE tts SEE POWER SUPPLY FLOW CHART GROUND DATA NPUT SGNAL CHECK CONNECTONS C2 ANO RELATED COMPONENTS 'l: '<10'/E OATA S :;:-,,1 l jaoi..:no, :';'3:J'j\j!-;!) l'tr'l'?' 'i:gn.:.l GROUND KEY NPUT SGNAL CHECK ON NE CT ONS C S AND RELATED COMPONENTS NO EA DATA CHANNEL S OPERA TONAL KEY ON SGNAL OK Figure , p. 5-73

155 TRACK SGNAL CHECK START REMOVE CONNECTONS TO CONNECT ORS J 3, J4J5J6,&J7 SWTCH ON POWER TO THE DECODER LOGC UNT NO SEE POWER SUPPLY FLOW CHART APPLY 12 voe ACROSS TRACK SGNAL NDCA TON NPUTS GROUND THE TRACK GND SGNAL CHECK CONECTONS, i., OPTCAL SOLATOR C3, AND RELATED CRCUTRY REMOVE 12VDC FROM TRACK SGNAL NDCA- TON NPUT NO TRACK NDCATOR OPERATONAL 6042, p Figure 5-29

156 Continuity Tests A. Check the continuity between connectors J7 and J3 as follows:. J7 J3 pin #1 < > 1 3 <-----+) 14 5 ( ) 2 Verify correct continuity between these pins and that no shorts exist to any other pins on connectors J7 and J3. Problems indicate either shorted voltage suppressors SPl, SP2 and SP3, or broken or shorted copper on the Power Distribution and nterface PCB. B. Check the continuity between connector J6 with connectors J4 and JS as per schematic (Figure 6-28). Verify that no other continuity exists other than indicated on the schematic. Problems indicate shorted or broken copper on the PCB, or defective connectors Receiver PCB Troubleshooting General.. The following procedure is a guide to bench testing of suspect Receiver PCB N A. Preliminary Setup 1. Refer to the circuit operation of the Receiver in Section 3.5.l of the manual before performing this procedure. (See Figures 6-16 and 6-17 for parts layout and schematic.) 2. nstall the suspect Receiver PCB securely into a known working Decoder Logic Unit drawer, leaving out all connections from the Decoder Logic Panel to any optional interfaces. (See the cover of the Decoder Logic Unit for connections.) 3. Place the.test Switch Sl on the Receiver PCB to position 2 {Normal). 6042, p. 5-75

157 NOTES: (1) All pin numbers listed in the procedure refer to the card edge connections on the Receiver PCB unless otherwise noted. (2) All measured signals on the Receiver PCB are referenced to common at test point 19 or pin 18 unless otherwise noted Suggested Test Equipment 1. VOM Simpson 260 or equivalent. 2. Frequency Counter 3. Oscilloscope 4. AC Voltmeter See Section for equipment specifications Power Supply Test 6042, p Switch on the AC input to the Decoder Logic Unit. 2. Measure the unregulated DC voltage at pin 16 on the Receiver PCB. The DC voltage should be approximately 14 volts DC, with less than 1.0 V ripple. 3. Measure the regulated DC voltage at pin 17 on the Receiver PCB. The DC voltage should be 13.0 V ±0.5 voe. f the regulated and the unregulated voltage readings of Steps 2 and 3 are low, remove the dual in-line connector (PL!) form the socket on the Receiver and measure the voltages on the exposed pins of the dip socket connector as follows: a) Voltage between pin 3 and common (pins 11-15) should be approximately 14 VDC with less than 1.0 volt ripple. b) Voltage between pin 7 and common (pins 11-15) should be 13.0 v ± 0.5 voe. f both voltages are correct,there is a problem associated with the Receiver power supply input. Also, if the unregulated voltage is low, check for shorts in the regulator circuit consisting of capacitors Cl6, Cl7, Cl8 Zener diode D9 and associated components.

158 4. Measure the regulated voltage drop across Zener diode 09. t should be lov ±0.5 VDC. An incorrect reading with a correct unregulated voltage indicates a problem with the 10 volt regulator circuit Clock Test 1. Check the Clock Out signal at pin 13 on the Receiver with an oscilloscope. The clock should be a squarewave approximately 12 volts minimum, with respect to common. f incorrect, check the signal at inverter C6 pin 12. The signal should be a rounded squarewave of approximately 10 volts peak with respect to common. A correct signal at the inverter indicates that transistor Q6 or the sped up circuit composed of R47 and C23 may be defective, otherwise, check C6, crystal and assocated components. 2.:. Measure the frequency of the clock at pin 13. The frequency should be KHz ±100 Hz. f the frequency is out of tolerance, adjust C20. f unable to adjust to within tolerance, replace crystal and/or capacitors C21, C Test Mode Test 1. Place the Test Switch Sl on the Receiver PCB to position l (Test Decoder). LED 1 on the Receiver should be lit and pin 5 should be at ground potential. f incorrect, check rotary switch Sl, LED 1 and resistors R46, R Place the Test Switch Sl on the Receiver PCB to position 3 (Test Receiver). LED 1 on the Receiver should be lit and pin 7 should be at ground potential. Check that a 12 volt digital test signal is inputted from the decoder via pin 9 to the base of Q5. This test signal should also appear at test point 1 with an amplitude of approximately 350 mv. peak-to-peak. f incorrect, check rotary switch Sl, transistor Q5 and associated components. 3. Place the Test Switch Sl on the Receiver PCB to position 2 {Normal). 6042, p. 5-77

159 LED 1 on the Receiver should be dark and pin 8 should be at ground potential. f incorrect, check rotary switch Sl, LED land resistors R46, R Demodulator and Carrier Detect Tests A. Required Set.up A complete operating AV System as in Figure 5-13 should be used to perform the Demodulator and Carrier Detect tests on the AV Receiver PCB with the Transponder Coil in position over the Wayside Coil. This is to assure that a constant return signal is being fed from the Transponder Coil via the nterrogator to the Receiver PCB. A continuous message is necessary to properly check the operation of the phase locked loop circuit and to trigger the oscilloscope to observe in detail the demodulated message waveforms on the Receiver PCB. The following criteria should be used to perform these tests: NOTE: 1. Test Switch Sl on the Receiver PCB set to position 2 (Normal). 2. All pictured waveforms on the Receiver were taken with the oscilloscope externally triggered from the Frame O (FRO) signal from the Programmer. 3. All readings are taken with the nterrogator properly tuned and set up to produce a -10 db level at test point 5 on the Receiver PCB. 4. Transponder Coil should be set in position 12" to 14" above Wayside Coil (use non-metallic spacer). 5. All pictured waveforms were taken with the message from the programmer set at There is a possibility of variations from the described signal levels or waveforms pictured if a different message is entered into the Programmer... f a complete system is not available, a quick check of the Receiver CB's filter and amplifier stages, and demodulator circuits can be made with the Decoder Logic Unit in the test receiver mode. For this test, all measurements must be taken with an oscilloscope externally triggered by the XMT signal (A30 pin 3) from the Decoder Logic Panel. Peak-to-peak voltage readings taken in the test receiver mode will be less than those taken with a complete system since the signal input is smaller (approximately 350 mv peak-to peak) at TPl. t is also recommended when observing the demodulated waveforms at TP8 and TP9 that the oscilloscope be triggered in the single sweep mode to eliminate problems due to the changing phase of the complete test messages. 6042, p. 5-78

160 NOTE: ncorrect readings will result from the use of any averaging instruments such as frequency counters and VTVM's in the test receiver mode, since a continuous message input is not present from the decoder. B. Demodulator Test With the Receiver PCB to be tested installed into the Decoder Logic Unit of a complete operating AV System, perform the following: 1. Using a VTVM, check the signal at TP5 on the Receiver. By adjusting Rl8 on the nterrogator, the signal at TP5 should be adjustable to -10 db. f not, using an oscilloscope, observe the signal between input pins 1 and 2 on the Receiver. The waveform should resemble Figure 5-30, although the amplitude may be different depending upon the position of the Transponder Coil over the Wayside Coil and the return signal strength from the nterrogator. f -10 db is obtained at TP5, the input signal should be about 2 V p-p minimum. f the waveform is incorrect, remove the dip socket connector (PLl) from the Receiver and recheck the input signal at connector J7 pins 1 and 3. f the waveform is now correct, check for a shorted primary of transformer Tl on the Receiver PCB. 2. Observe the signal at TP2 on the Receiver PCB. The signal should be identical to the waveform at pins 1 and 2 except about 10% lower in voltage. An incorrect signal signifies a possible problem with test switch 51, isolation transformer Tl, resistor network Rl, R2 and R3, or the bandpass filter input. (nsure that the test switch 51 is in the normal position:.) 3. Observe the.signal at TP5 on the Receiver PCB. The waveform should resemble Figures 5-18 and Figure 5-18 shows a complete message and Figure 5-19 shows the details of one zero crossing. This signal at -10 db shall be approximately 0.84 V p-p. f incorrect and the nterrogator is properly tuned, the problem is in the bandpass filter circuit. The filter is precision tuned at the factory, and it is recommended that field tuning be ayoided. However Section " on tuning describes the procedure, if necessary. 4. Check the amplifier stages by observing the signal at TP7. The signal output of the 2nd amplifier stage should be approximately 9V p-p (see Figure 5-31). f incorrect, determine if the 1st amplifier stage is defective by observing the signal at TP-6. t 6042, p

161 should be identical to the signal at TP5, except approximately 3.5 V p-p. An incorrect signal indicates a problem with the first stage of Cl. Check the setting of R4 (see tuning procedure Section ) and troubleshoot 1st amplifier stage. f the signal at TP6 is correct, there is a problem with the 2nd stage of Cl or associated components. 5. Verify the correct operation of the phase locked loop circuit as follows: Measure the frequency at TPlO. t should be a KHz ±100 Hz sinewave with a maximum amplitude of approximately 15 V p-p. An incorrect signal indieates a malfunction in the frequency multiplier circuit Q4, Ll and Cl. Check the signal at TP12. A lov squarewave with a frequency of KHz ±200 Hz should be present. An incorrect signal indicates a faulty phase locked loop, C4. Check the frequency at TP13. t should be one-half the frequency of TP12, KHz ±100 Hz. Check the signal at TP14. A 76.8 KHz ±50 Hz squarewave should be present. ncorrect signals indicate a defective C5. NOTE: The following frequencies are given only as an intermediate check with no input from the nterrogator: TPlO, no signal; TP12, KH.z; TP13, KHz; TP14, KHz. 6. Check the phase detector by observing the signal at TP8. The waveforms. should resemble Figures 5-32 and Figure 5-32 shows one complete message and Figure 5-33 shows details of a phase change in the message. A faulty signal indicates &ither a problem with the third stage of Cl or with analog switch C3. 7. Check the window detector C2 by observing the signal at TP9 (see Figures 5-32 and 5-33). An incorrect signal indicates a problem with C2 and/or associated components. 8. Check the signal at pin 14 on the Receiver PCB. t should be identical to the one at TP9 except 1800 out of phase and an amplitude of 14 V p-p. f there is a problem at pin 14, check Ql and associated components. 6042, p. 5-80

162 C. Carrier Detect Test 1. Observe the signal at TP7 as described in the Demodulator Test part B step 4. f incorrect, perform the entire Demodulator Test procedure to locate the problem before continuing. 2. Observe the signal at TP15. t should be identical to the signal at TP7 except 1800 out of phase. An incorrect signal indicates a problem with C6 and/or associated components. 3. Check the output of C7 at TP18. when there is data being received and 14 VDC with no signal after a 0.5 milliseconds. t should be 2 VDC from the nterregator delay of approximately f incorrect, check for a problem with C7 and the turn off delay c ircuit consisting of Q3, R35, ClS, DS and associated components. (See tuning procedure Section for Carrier Detect Delay Adjustment if required. ) The DC voltage at TP17 controls the delay at TP18 by varying the input threshold voltage to comparator C7. This voltage is dependent on the setting of variable resistor R35 (see Section ). With the delay set for 1 millisecond the voltage at TP17 should be approximately 5.8 volts with data input and 6.2 volts with no signal. The voltage at TP16 is clamped by diode DS to no more than 0.7 volts DC above TP17. Typical voltages for TP16 are 6.3 volts DC when data is received and 4.9 volts DC with no signal input. 4. Measure the carrier detect output at pin 15 on the Receiver PCB. t should be approximately 14 VDC when data is being received and zero volts with no signal. ncorrect values indicate a problem with Q2, DS and/or associated components Receiver PCB Tuning Adjustments The AV Receiver PCB N used in the Decoder Logic Unit comes pre-adjusted from the factory. The following procedures should be performed. on a suspected faulty Receiver PCB only if required after the completion of the Receiver troubleshooting procedure :.. 8, KHz:. bandpass filter adjustment. 2. Receiver sensitivity and phase locked loop frequency adjustments. 3. Carrier Detect delay adjustment. 4. Clock frequency adjustment.

163 ) Figure 5-30 _ Receiver PCB Pin 1-2 w... ::""'. :'.. -4 Figure 5-31 _ Receiver PCB TP7 Figure Receiver PCB TP8 {Top) TP9 (Bottom 6082, p ,. l l

164 Figure 5-33 Receiver PCB TP8 {Top) TP9 {Bottom) 1 J 6042, p. 5-83

165 KHz Bandpass Filter Adjustment (See Figure 6-16) The following procedure is used to tune the 76.8 Hz. bandpass filter of the Receiver PCB. This filter should only be adjusted when any defective components are replaced in the bandpass filter circuitry. A. nitial Procedure (1) Remove Receiver PCB from the Decoder Logic drawer. (2) Remove Carnauba wax seal from inductors Ll, L3 and L4. (3) Remove jumpers Jl, J2, J3 and J4 on the Receiver PCB. (4) Arrange test set up as per Figure B. Tuning Procedure (1) With the AC voltmeter connected across the 820 ohm resistor, short leads "A" and "B" in Figure 5-34 and adjust the signal generator for a continuous sinewave signal of 3.0 ±0.5 volts RMS indicated on the AC voltmeter, and a frequency of 76,837 ±1 Hz. indicated on the frequency counter. (2) Open the shorted leads "A" and "B" of Figure 5-34 and connect the AC voltmeter across them. (3) Connect leads "A"' and "B" between Test Points TP2 and TP3 on the Receivr PCB. Adju9t.. _t_he slug in inductor Ll for a null indicated on the AC voltmeter. (Minimum Reading) (4) Connect leads "A"' and "B" between Test Points TP3 and TP4 on the Receiver PCB. Adjust the slug in inductor L3 for a null indicated on the AC voltmeter. (Minimum Reading) (5) Connect leads "A"' and "B" between Test Points TP4 and TP5 on the Receiver PCB. Adjust the slug in inductor L4 for a null indicated on the AC voltmeter. (Minimum Reading) (6) Disconnect leads "A" and "B" and reinstall jumpers Jl, J2, J3 and J4. (7) Seal slugs of inductors Ll, L3 and L4 with Carnauba wax. 6042, p. 5-84

166 ELECTRONC COCJNTER C NPUT AC VOLTMETER "C" C Sro-PLX 620i. LEAD "A" SNEWAVE 1,,.-----'----"AA.,... L_EAD "-B-" OSCLLATOR JJ. Figure _ _ _, p. 5-85

167 2. Receiver Sensitivity and Phase Locked Loop Frequency Adjustments NOTE: Adjustments should be made to only those areas where where the troubleshooting procedures indicate. A. nitial Procedures for Sensitivity and Phase Loop Adjustment. (1) nstall the Receiver PCB that is ready for adjustment into a working Decoder Logic Unit and make all internal connections (see cover of Decoder Logic drawer for hook-up instructions). (2) Arrange test set up as per Figure (3) Disconnect all cables to connectors J6 and.j7 on the back of the Decoder Logic drawer and install power cable to connector J8. (Make sure Decoder Unit: is turned off before connecting 115 VAC power). (4) Connect leads "C" and "D" in Figure 5-35 between pins 1 and 3 of connector J7 on the Decoder Logic Unit. (5) Turn on Decoder Logic Unit. (6) Set the Test Switch Sl on Receiver PCB to "Normal" - Position 2. (7) Apply a co1t.i1uous _sinewave signal of_ 78 ±0.2 millivolts.rms, indicated on the AC vo.ltmeter., -----a-t a frequency o{.. 76, 800 ±50 Hz, indicated on.. the frequency co"!=er, to_pins_l.and 3 of connector J7. B. Receiver Sensitivity Adjustment (1) Connect oscilloscope probe to Test Point TP7 and common to Tes,t Point TP19 on the Receiver PCB and adjust po.tentiomeer R4 for a 5.0 ±0.2 V p-p sinewave asi indicated on the oscilloscope. (Seal may have to be broken on R4 to make adjustment.) (2) After adjustment,, seal R4 with torque seal. C. Phase Locked Loop Frequency Adjustment NOTE: f receiver sensitivity needs adjustment, complete part B before continuing. 6042, p. 5-86

168 OSCLLOSCOPE c ELECTRONC COUNTER TO 115 VAC POWER LEAD "C" LEAD "D" E SNEWAVE OSCLLATOR C 1----' 1. 3K ohms AC VOLT.METER Figure _, p.. 5_:-:_8_7_

169 (1) Remove Carnauba wax from inductor LS. (2) Connect oscilloscope probe to Test Point TPlO and common to Test Point TP19 on the Receiver PCB and adjust inductor LS until maximum amplitude is indicated on the oscilloscope. (3) Disconnect oscilloscope and counter to Test Point TPlO. frequency should be 153,600 on the electronic counter. connect frequency The measured ±100 Hz, indicated (4) Seal inductor LS with Carnauba wax. 3. Carrier Detect Delay Adjustment NOTE: This adjustment can only be performed if the rest of the Receiver PCB is operating properly. f receiver operation is questionable,.refer to the receiver troubleshooting procedure. :Cl) nstall. the Receiver PCB that is ready for adjustment into a working Decoder Logic Unit and make all internal connections (see cover of the Decoder Logic drawer for instructions). (2) Switch on the Decoder Logic Unit. ( 3) Connect channel 1 of a dual channel oscilloscope to the XMT signal at pin 3 of C A30 on the Decoder Logic Panel N (4) Connect channel Z of a dual channel oscilloscope to TP18 of the Receiver PCB and common to TP19. (5) Set Test Switch Sl on the Receiver PCB to 11 T-RCVR" _- position 3. ( 6) ( 7) Trigger oscilloscope in the normal mode on channel 1. Display the signal in the chop mode. Adjust potentiometer R35 until the carrier detect signal t r;re_--- oint _TP8 _on _channel. 2 goes-low, l millisecond after:the transmit signal a f channel:. 1" goes positive, as displayed on the oscilloscope. seal R35 with torque seal after adjustment. 6042, p

170 4. Clock Frequency Adjustment (1) nstall Receiver PCB in the Decoder Logic Unit and energize drawer. (2) Connect the frequency counter between the collector of transistor Q6 and common on the Receiver PCB. Adjust trimmer capacitor C20 until 153,600 ±100 Hz is indicated on the frequency counter. (3) Seal capacitor C20 with torque seal after adjustment Decoder Logic Panel Troubleshooting (N ) Basic Troubleshooting (Refer to Figure 5-37) A. Preliminary Set Up 1. Refer to the detailed circuit operation of the decoder in Section of the manual before performing this procedure. 2. Verify that the Decoder Logic Panel to be tested is free of shorts in its power wiring (Between +V and Gnd). 3. nstall the suspect Decoder Logic Panel securely into the Decoder Logic Unit drawer of a known working AV system, leaving out all connections from the decoder to any optional interfaces. (See the cover of the Decoder Logic Unit for connections.) B. Procedure NOTE: Should any of the succeeding steps fail, troubleshoot the decoder to correct any problems, then repeat this entire procedure to verify that the decoder is working properly. 1. Place the Test switch Sl on the Receiver PCB to the Normal position. -2. Switch on the AC input to the Decoder L.ogic Unit..... _ -Check for- be -voltage ori the decoder panel of ;2p_r9ximLy 12 volts between +V and ground. f no voltage is present, check for a broken power wire on connector Jl-3' (BJl) on the Decoder Logic Panel. 6042, p. 5-89

171 2a. All LEDs on the decoder panel should be off (dark), provided a Transponder Coil is not present over a Wayside Coil in the system. f not, check the wiring and components of the master reset (MSTR) circuitry on: Schematic (Figure 6-18) Gates Al2 pins 12 and 15 Diode 1N4005 (component mount Al3) Resistor 22K Capacitor 4.7 p.f Assure that the appropriate pulses are present atpins 12 and 15 of inverters Al2 when the decoder is first turned on (logic 1 at pin 12, logic Oat pin 15), to reset the decoders circuitry.. 3. Switch on the 12 VDC track circuit power supply connected to the Decoder Logic Unit. (See Figure 5-14.) 3a. Key-On and Track LEDs on {lit) - indicates normal operation - Go to Step 4.. 3b. Key-On LED, Track LED or both LEDs off (dark). Check the wiring and operation of the Key-On and Track circuitry on: (Track Circuitry) Schematic (Figure 6-19) Gates A25 pin 12 BS pin 2 Flip-Flop B9 pin 15 (TRAK) LED and Resistor 2K (Key-On Circuitry) Schematic (Figure 6-20) Gates Bl5 pin 10 (TEST) A30 pin 13 Al2 pins 10 and 12 (Key) LED and Resistor 2K Trace circuit inputs to other Cs when necessary. 4. 4a. 4b. s. Sa. Turn off the track circuit power supply. Key-On and Track LEDs should go off (dark) - Go to Step 5. normal. f not off, check the clock reset input B9 pin 11 to the Track Occupied Flip-Flop. Place the Transponder Coil approximately 12-14" over the Wayside Coil (use non-metallic spacer). Carrier Detect LED on (lit) - operation - Go to Step 6. indicates normal 6042, p. 5-90

172 .. Sb. Carrier Detect LED off (dark). Check the wiring and components of the Carrier Detect circuitry on: Schematic (Figure 6-18) Gates A25 pin 4 A20 pin 2 LED and Resistor 2K Check receiver carrier output to other Cs when- neceifs.ary: Trace circuit inputs 6. Remove Transponder Coil from over the Wayside Coil. 6a. Carrier Detect LED should go off (dark) - normal operation - Go to Step 7. 6b. Should the Carrier Detect LED stay on, refer to Section on Receiver PCB and check sensitivity. T. Turn on.the track circuit power supply. Pass the Transponder Coil over the Wayside Coil and remove. 7a. Good Message LED on (lit) indicates normal operation Go to- Step 8. 7b. Good Message LED off (dark) or Error Message LED on. Problem--Received data was possibly processed incorrectly due to malfunction on the decoder input timing logic. Refer to Section for detailed Decoder Logic Panel Troubleshooting before proceeding. 8. Activate the Lead Car and Cab Signal input to the Programmer, using the status input test cable (Figure 5-9). Switch off the track circuit power supply till all LEDs on the Decoder Logic Panel go out, then switch back on. Pass the Transponder Coil over the Wayside Coil and remove. 8a. Cab Signal and Good Message LEDs on (lit) - indicates nol operation - Go to Step Cab Signal LED off (dark) and Good Message LED on (f Error Message LED on, go to 7B). Check the wiring and components of the Cab Signal circuitry on: Schematic (Figure 6-19) Gates Bl4 pin 3 B8 pin 4,6 and , p. 5-91

173 6042 P Flip Flop B9, Pin 1 (Cab Signal FF) Shift Register Al pin 3 (Cab Signal) Al pin 10 (Lead Car) Trace circuit inputs to other Cs when necessary. 9. Turn off.the track circuit power supply. 9a All LEDs should be dark. f not, go to step 3B and check the track circuitry and step 8B and check the cab signal circuitry. 10. Repeat the procedures in Steps 8 and 9 usirrg only the Cab.s.ignal bit, then repeat the procedure in-step--& using only the Lead Car bit. Cab Signal LED should not come on when the Good Message LED lights. 11. Without clearing the track circuit, energize the Cab Signal and Lead Car switches. Pass the Transponder Coil over the Wayside Coil and remove. Cab Signal LED must not be lit. f it does, check the wiring and operation of the first Message Flip-Flop (B7 pin 1) on schematic (Figure 6-19). Serial Data Output Check 12. Set the Programmer thumbwheel switches to route 19 and the car number to Energize only the Lead: Car input to the Programmer using the status input: test cable (Figure 5-9). Energize the track circuit power supply. Refer to the decoder output timing chart (Figure 6-23}. Connect the XMT signal at C A30 pin 3 to the external trigger input: of a dual channel oscilloscope. (Set oscilloscope to trigger on a positive going signal). Connect channel 1 of the oscilloscope to the CLOCK signal at C A2 3 pin 3!. Connect channel 2 of the oscilloscope to the DATA OUT signal at C Bl4 pin 12. Pass the Transponder Coil over the Wayside Coil and remove.

174 12a. The DATA OUT signal displayed on the oscilloscope should correspond to the signal pictured on the output timing chart (Figure 6-23) this indicates deceder output logic circuitry is operational. f not, there is a possible malfunction on the decoder's output timing logic. Refer to Section for detailed decoder panel troubleshooting before proceeding Repeat Step 12 with channel 2 of the oscilloscope connected to the DATA signal at connector BJl pin 13 on the decoder instead: of C A30 pin 3 (See schematic Figure- 6"201: a. The DATA signal displayed on the oscilloscope should correspond to the DATA OUT signal pictured on the output timing chart. 13b. Repeat Step 12 with channel 2 of the oscilloscope connected to the DATA signal at connector--bjl pin 12 on the decoder instead:of C A30 pin 3 (See schematic. Figure 6-20). 13c. The DATA signal displayed on the oscilloscope should be an inverse of the DATA OUT signal. f the DATA and/or DATA signals are iric0rrect,_check the wiring and res of the decoders data output circuitry on: Schematic (Figure 6-20) Gates A3 0 pin 12 A24 pin 10 (DATA) A9 pin 12 A20 pin 15 (DATA) Trace circuit inputs to other res.and to the Power Distribution and nterface PCB (Section 5.9.5) when necessary. 14. Deenergize the track circuit power supply and remove all external status inputs to the Programmer. Test Mode Check 15. Place switch Sl on the. Receiver PCB to the Test Decoder position. 6042,

175 15a.. The Track LED should be lit and the Good and Error Message LEDs should alternately flash. This indicates correct operation. 151:>. ncorrect indications on the Test Decoder mode indicate possible malfunctions in the decoders Test Message generator or Error Message detection circuitry of the input timing logic. Refer to Section for detailed decoder panel troubleshooting before preceeding. lsc. Check for alternate 10: millisecond logic O ood and Error Message strobe pulses (GMST and EMST) at connector AJ2 pins 9 and 8 on schematic (Figure 6-20). Thee pulses must be present: for parallel transfer of data from the decoder. f no pulses are present, check the wiring and operation of NAND gate A4 pins 3' and 4 on schematic {Figure 6-20)... Trace circuit inputs to other Cs when necessary. 16. Place the Test switch Sl 6n the Receiver PCB to the Test Receiver position. 16-a-. The Track LED should. be lit, the Carrier Detect LED should flash rapidly, and the Good and Error Message LEDs should alternately flash. This "indicates normal operation. 16b. ncorrect LED indications in the Test Receiver mode and correct indications in the Test Decoder mode indicate problems with: the operation and wiring of the following Cs on: Schematic {Figure 6-20X Gates A9 pin 13 DATA (TO RCV) B23 pin 13 A23 pin 11 {RDD) Trace: circuit inputs to other Cs and check Receiver PCB when necessary. 17. f no problems were encountered in any of the previous steps, the Decoder Logic Panel is operating properly. 6042, p. 5-94

176 Detailed Troubleshooting A. General This procedure is intended as a guide for troubleshooting the most common failures of the Decoder Logic Panel N Perform the following procedure only if referred to by the Basic Troubleshooting guide for the decoder in section of this manual. After completing this section, repeat the procedure given in the Basic Troubleshooting guide (Section ) and verify the Decoder Logic Panel is operational. B. Preliminary Setup nstall the defective Decoder Logic Panel into a working Decoder Logic Unit drawer as per section of this manual. switch on the AC input to the Decoder Logic Unit c. Preliminary Diagnosis (Refer to Figure 5-38) 1. Place the Test Switch Sl on the Receiver PCB to the Test Decoder position. Z.. The Track LED should be on (lit} - indicates normal operation - Go to Step a. f not, check for a logic 1 simulated track input signal (TEST} at the Track Occupied FF (B9 pin 9) on schematic (Figure 6-19} and troubleshoot associated circuitry. J. Key-On LED must be off (dark) - normal operation Go to Step 4. <ta. f not, check for a logic O TEST input signal at NANO gate A30 pin 14 on schematic (Figure 6-20} and troubleshoot associated circuitry. 4. Observe the Good and Error Message LED indications. 4a. Good and Error Message LEDs should alternately flash, indicating normal operation. f not, the following erroneous conditions may exist:. Good and Error Message LEDs both off (dark).. Error: Message. LED flashing.

177 . Good Message LED flashing. V. Good and/or Error Message LEDs on steady. Refer to the following sections relating to the indications observed and troubleshoot as required. Repeat this step as required till correct indications are observed. Should multiple problems occur; for example, one of the message LEDs may be on steady while the other is flashing, correct all steady or solid conditions first theri repeat the preliminary diagnostic tests , p. 5-96

178 . Good and Error Message LEDs Both Off (Dark) 1. Refer to the decoder test timing charts (Figure 6-24 and 6-25). 2. Check the following output timing signals as per timing charts listed above. NOTE: t is advisable to trigger the oscilloscope on the logic O edge of the CYCLE TEST signal (C A26 pin 14) when observing the decoder output timing. The output timing signals are the same for both Good and Error Messages. Signal Location Cycle Test A26 pin 14 XFER B28 pin 6 SMCD A29 pin 14 XMT A30 pin 3 CLOCK A23 pin 2 XMT CLOCK A24 pin 6 RESE'l! XM!'l! B30 pin 6 ENDX B30 pin 10 2a. Also refer to timing chart (Figure 6-23) and check the following: CT4 A29 pin 1 CT52 A28 pin 12 Set XMT B28 pin 10 The timing for these s:ignals as listed should also occur in the Test Decoder mode. 2b. The signals listed in Sections 2 and 2A are the basic output timing signals in the decoder's logic and they must be present for proper operation. f any signals are incorrect, troubleshoot the decoders output timing as per timing charts. Replace all defective wiring and Cs. 3. f the decoder's output timing signals are correct,. check for the proper occurrence of the data related signals in Step 3A; as per timing charts (Figure 6-24 and 6-25). NOTE: n normal decoder operation, the Data Load FF - (B27 pin 2) should toggle, resulting in alternate Good and Error Messages being _9_i_c11J.:tE39,_j::hr_q_µ g_l:l.t_h.e gcoder _(.See c;ie=_coder test message timing, Step 3A). Error test message data can be observed by triggering the oscilloscope on the logic O DATA LOAD signal. (Data Load FF set). 6042, p. 5-97

179 3a. Check the following signals and reference the data bits states and positions to the output Clock signal at A23 pin 2: DATA LOAD TEST DATA DATA OUT ROD B27 pin 2 Bll pin 3 Bl4 pin 12 A23 pin 12 3b. Signals must correspond to the timing charts for either a Good and/or Error test message indicating normal operation. f correct, skip sections 3C, 30, and 3E and go to Step 4. 3c. f the TEST DATA signal is incorrect, check the wiring and C s of the decoder test message generator circuitry on: Schematic (Figure 6-20) Shift Registers Bll pin 3 (TEST DATA) Bl6 pin 3 B21 pin 3 B22 pin 2 B26 pin 3 Gate Bl5 pin 15 Trace circuit inputs to other Cs when necessary. 3d. f the TEST DATA signal is correct, but the DATA OUT signal is incorrect, check the wiring and C's of the decoders serial message output circuitry on: Schematic (Figure 6-19) Gates Bl4 pin 12 (DATA OUT) Bl5 pin 6 Bl2 pin 12 Bl2 pin 3 Bl3 pin 13 Shift.Register Bl7 pin 3 Check that bilateral switches Bl2 are enabled at pins 5 and 14 by a logic O TEST signal (Figure 6-19). Trace circuit inputs to other C's when necessary. 3e. f the TEST DATA and DATA OUT are correct, but the ROD signal is incorrect, check the wiring and operation of the phase encoder C's on: Schematic (Figure 6-20) Flip-Flop B27 pin 15 Gate! A23 pin 12 (ROD) Trace circuit inputs to other C's when necessary. 6042, p. 5-98

180 4. f the decoder's output timing logic is functioning and either a valid Good and/or Error test message is being outputted, from the test shift register, at least one of the message indication LEDs (Good or Error) should be working (see Schematic, Figure 6-19). Go to preliminary diagnosis Section Part C and observe LEDs. 4a. f not functioning, check the wiring and operation of the message received, data good, and good and error message indication circuitry on: {Message Received Circuitry) Schematic (Figure 6-20) Flip-Flop A26 pin l (MSG REC FF) Counter A21 pin 1 Gates A27 pin 3 A28 pin 11 (C'Jr 44) and associated circuitry (Data Good Circuitry) Schecmatic (Figure 6-18} Gates Al6 pin 5 (DATA GOOD) A25 pin 3 A20 pin 4 Counter Al8 pin 1 (Good and Error Message ndication Circuitry) Schematic (Figure 6-19) Flip Flop B6 pins 15 and 1 (GOOD MSG, ERROR MSG) GATES Bl3 pin 4 Bl5 pin 2 and 4 LEDs and Resistors Trace circuit inputs to, other Cs when necessary. Troubleshoot the above circuits as required per timing charts (Figure 6-24 and 6-25) until at least one of the message indication LEDs are lit. Return to Preliminary Diagnosis guide, Section Part C for additional checks and troubleshooting information. _ 6042_,_p_._ 5'.'.'."9.9 _

181 . Error Message LED Flashing 1. Observe the RDD data signal {A23 pin 12) being fed into the decoders input timing logic and reference the data bits, states and positions, to the output clock signal at A23 pin 2. Note whether the RDD signal is in correct form for either good, error, or alternate good and error test messages. {See timing charts Figure 6-24 and 6-25.) f the data does not correspond to the timing charts, go to Section (Good and Error Message LEDs both off) and perform steps 1-3 inclusive. 2. f RDD consists of a continuous error test message from the test shift register, check the wiring and operation of the Data Load Flip-Flop (B27 pin 2) on schematic (Figure 6-20). Troubleshoot as per timing chart (Figures 6-24 and 6-25). When problem is corrected, the LED indication should change. Return to Preliminary Diagnosis guide Section Part C for further troubleshooting information. 3. f ROD consists of alternate or random good and error test messages, check the wiring and operation of the good message indication circuitry on: Schematic (Figure 6-19) Flip-Flop. B6 pin 15 (GOOD MSG) Gate Bl5 pin 4 LED and resistor Also, check the wiring and operation of the Data Load Flip-Flop (B27 pin 2) on schematic (Figure 6-20). Troubleshoot as required per timing charts (Figures 6-24 and 6-25) When problem is corrected the LED indications should change. Return to Peliminary Diagnosis Section Part C for further troubleshooting information. 3a. f RDD consists of a continuous qood message output, check for the occurrence of logic O pulses at the input of NANO gate:-all pins.j, 4.. and 5, during the RDD signal message. (See Schematic Figure 6-18). Pulses occurring on pins 3, 4 or 5 of gate All indicate BCH, Excess Zero, or Sync Errors respectively. Refer to Steps Jc 6- d and 3. NOTE.: Excess Zero Errors can occur between messages during normal operation. 6042, p. s-100

182 After any or all of the error circuits have been checked and repaired, the test mode operation should change. This will be reflected by a change in LED indications. Return. to the Preliminary Diagnonsis guide Section 5.9.7L2 Part C for further trouble- sc?.i-<j. _as;_ rqrd _ 3b. f no errors are occurring, check the wiring and operation of the following Cs on: Schematic (Figure 6-18) Flip-Flop Bl8 pin 1 (ENABLE DATA) Bl8 pin 15 (ON) A6 pin 14 (RESET} Troubleshoot as per timing chart (Figure 6-24 and. 6-25}. f LED indications do not change, repeat step 3a and check for errors. 3c. f Excess Zero Errors are occurring during the message, causing the decoder to, reset during a good message, check the wiring and operation of the following Cs on schematic (Figure 6-18). Counter Al 7 pin 1 ( ZERO TEST COUNTER) Gates All pin 11 A4 p,in 13 A24 pin 12 B.20 pin 4 ("l" RESET PULSE) Al6 pin l Single-shots Al4 pins 7 and 9 Flip-Flop A6 pin 14 (RESET) - Trace circuit inputs to other Cs when necessary. Excess Zero Errors should occur only under those conditions given on.timing chart (Figure 6-2:J.-" Troubleshoot as required, using timing charts Figures 6-24 and -25) whenever poss-ible : f LED indications do not change, repeat Steps. 3a and check for additional types of errors. 3d. f BCH Errors are occurring during a good message transmission, check the RESET (BS pins 6 and 14), DATA (BS pin 7), and BCl Clock (Bl3 pin 11 and 12) inputs.to the data shift registers (BS, Al, A2, A3 and B22) on schematic (Figure 6-19). Verify that the first stage of the data register at BS pin 5 is receiving a valid message, as per timing chart (Figure 6-25). f not,. check the operaton_ an_<!_:i,ring _6042,_:g_. 5-10_],

183 of the RESET Flip-Flop (A8 pin 14) on schematic (Figure 6-18) and NAND gate Bl3 pin 12 on schematic (Figure 6-19). Also verify that none of the data shift register outputs DB1-DB28 are fixed at one logic level. f so, check for shorts in the parallel data output lines. f BCH Errors still persist, check the wiring and res of the BCH check circuitry on:,,,...,,.. Schematic (Figure 6-18) Flip-Flop A6 pin 2 (BCH CHECK) Gates Al6 pin 1 Al2 pin 4 Schematic (Figure 6-19) Shift Registers BS, Al, A2, A3 (All Stages) B22 pin 10 Parity Generators BlO, B4 Flip-Flop B7 pin 14 (BCH =-=..--,,.-- ERROR) BCH Errors should occur only under those conditions given on timing chart (Figure 6-26). Troubleshoot as required using timing charts (Figures 6-24 and 6-25) whenever possible. f LED indications do not change, repeat Step 3a and check for additional types of errors e. f Sync Errors only are occurring during a message and resetting the decoder,, check the wiring and operation of the following Cs on schematic (Figures 6-18): Flip-Flops A7' and A8 (SYNC DETECTON CS) AlO and 15 (DATA and PHASE) Bl8 pins 1 and 15 (ENABLE and ON) Single-Shots Al4 pins 7 and9 B24 pin 9 (DELAY CLOCK) Gates A9 pins: 3 and 4 and associated Cs Trace circuit inputs to other Cs when necessary. Refer to timing chart (Figure 6-21) for detailed timing operation. Sync Errors should occur only-under those conditions given on timing chart (Figure 6-26). Troubleshoot as required using timing charts (Figures 6-21, 6-24-and 6-25} whenever possible. 6042, p

184 . Good Message LED Flashing 1. Refer to the procedure for the Error Message LED flashing in Section and perform Step f ROD (A23 pin 12) consists of continuous good test messages from the test shift register, check the wiring and operation of the Data Load Flip-Flop (B27 pin 2) on Schematic {Figure 6-20). Troubleshoot as per timing chart (Figures 6-24 and 6-25). When problem is corrected, the LED indications should change. Return to Preliminary Diagnosis guide Section Part C for further troubleshooting if required. 3. f ROD consists of alternate or random good and error. test messages, check the wiring and operation of the error message indication circuitry on: Schematic {Figure 6-19) Flip-Flop B6 pin 1 (ERROR MSG) Gate Bl5 pin 2 LED and resistor Also, check the wiring: and operation of the Data Load Flip-Flop (B27 pin 2) on schematic (Figure 6-20). Troubleshoot as required per timing charts (Figures 6-24 and 6-25). When problem is corrected, the LED indications should change. Return to Preliminary Diagnosis guide Section Part C for further troubleshooting if. required. 4. f a continuous error test message is being outputted from the test shift register, verify that the RESET signal from flip-flop A8 pin 14 (Figure 6-18) to the data shift registers (BS, Al, A2, A3 and B22 on Figure 6-19) is alogic O after the correct start code has been received. f: not, check the wiring and operation of the RESET'. flip-flop AS pin 14 on.(figure 6-18) 4a. f problems persist, check the wiring and operation of the Cs listed in Step1 3d of Section (Error Message Flashing) and troubleshoot as required using timing chart (Figure 6-24). When problem is corrected, the LED indications should change. Return to Preliminary Diagnosis guide Section Part C for further troubleshooting if required , p :. ::=

185 V. Good and/or Error Message LEDs on Steady 1. Place the Test Switch Sl on.the Receiver PCB to the Normal position. 2. Observe if the Good and/or Error Message LEDs go off. 2a. f the LEDs go off, there is a problem with the reset signal to the Good and' Error Message Flip-Flop (BG pins land 15) generated"by the SMCO signal. Place the Test Switch Sl on.the Receiver PCB back to the Test Decoder position and check the reset signal (CD TRAK SMCD) to the: Good and Error Message FFs at NANO gate Bl3 pin 5 on. schemat±c(figure 6-19). Also, check the wiring and operation of the SMCO flip-flop (A29 pin 14) on schematic (figure.6-20). 2b. Troubleshoot as required per timing charts {Figures 6-24 and 6-25). Go to Step 3. f LEDs do not go off,. verify that a logic O TRAK sign_l ;Ls_pres.ent_-atND ga_'=. ]3-1_3_ p 6 fom 1=-_h---. j Track Occupied flip-flop (B9 pin 15) on schematic Figure 6-19, otherwise check the wiring and operation. of the - Tr a.ck. 6c-cupied -f l.ip-:..f lop ; f a logic O TRAK signal is present, check the wiring and operation of the following Cs on schematic F1 6-_1 - d--_r--1:001:as_.e.:ui:1::_-=-:: Flip Flops B6i pins 15 and l Gates Bl3 pin 4 Bl5 pins 2 and 4 (GOOD MSG, ERROR:MSG) 3. When problem is corrected, place the Test Switch Sl on the Receiver PCB back to the Test Decoder position. When troubleshooting i.s completed, the LED indication, should change. Returnt to. Preliminary Diagnosis guide, wlien --reqtif"red ,_, section P-art. C for further troubleshooting J , p

186 WABCO,-; + NffERCONNlCTNG """""' CULHFROM OPTlONAL CNTERFACU CHECK FORAN Ol'EN... N _ POWR PQl,ORJCWER OUTPUT ANO TUNNG AO.JJSHT ONA WORKNG HTRROOATOR USNG A GOOO CAR AT AND OCOD. ORAWE 1. RP.AC CA8U B ndlfl RECEVER ANOOl!:COOR. rf STLL UDP ATVE 2.fflOUal.UMOOT RECEVER. l. TROUBLUHOOT OECOOU. 1. TROU1H.ESHOOT PCM&R DfSTRtBUTON AHO fhttllface l'anl, F fflll HOPRATVE :Z. TOU&USHOOT _.._ CONNECT AN TMlil!CQSUiMA,. A.AYCOHTACff fteou:oo TROWLEHOOT- fnta.l Of:F&CTV OCOOER ORAW1Eft N PUCE Of TH WORKNG OECOO l.ogcunt CONNCT STATUS Nf\lTTEST CAR. TO NOQAMER AHO tnrglft CAii SGNAL AHDLEAOCAR swm:ku lhergz:e TRACK ' CRC\UT JO,dll SWPt.Y: PAST1AQill!OftO OVJtWA'SOCOff.. 4"DEMDV SHDCOOl! TJtOUSLUtfOOTJNG REPLAC PUN Oii DPECTV SWTCH t, CHECK FOii A N.OWN...,.. F STLL lffohratry'. Z. TROULUHOOt l'owl;r - Sii R CtlVR TRWOUSNOOTHG TO CHECK AOTAY SWl'TCH ANDUD S.OECOOR TROUeLSHOOTHQ 1. Rll'\.AC CARL FROM POWR OtSTRfBUTOH l'anl TO OCOOER.,, mu.1non11attvf z. TROU8U:SH001' POWR DSTUTON... l. TROUUSHOOT OCOOU, EHEAGZ TRACK CRCUT l'qwl:r SUf'P1. Y: Pl.S TRAHBl"OHDR OVR WAYSD COL AHOR MOVE SEflOWR OSTRUT«>N ANO NTERFACE PC8 TROUB.UHOOTtNG TO CHCK RLAY: F STLL NOfllftATV&, RlnAC CAM. FROM CONNECTOR JJ 1101.AC DtfECTV WRNG OR SHORTED VARtSTOtl ON,OW OtSTRl9UTOH PANeL l"lac TAAfC8il'OHOlR COL OVR WAYSO COL AT 1J.14- HEGHT, USHC NON METALLC SPAClA SHDCOOER TROUll.ESHOOTNG 1 -- tlftpaca PC VO.TAGa RCUU.O CHCKJUTAHO OUTPUTYO.TAOUOF RGU.ATOR ON ntm: POWaA DtfflltlllUTOM AHO NTERFAl:! PC CHCK FORA SHCMT Ht RCVE OR OUOO PANEL POR lfflllnc SURECQVR TftOU.UHOOTH TOCHCK ROTARY swm:tf ANOLD,._ -- t. El't.ACaCMU U1WN RCEY F STLL tnoplflattve OecoolR. - S&a ECVE TO CHECK ROTMY SWTCffANOUD CHCK WUNG FAOM COtfffECTOR R THROUGH POWER o,cnulutoh ANO llfffafac! l'"anl TO MCVR PANEL -- TRAC SKlNA. FROM CONNCTOR n THROUGH AND ttnl!afac PAN.L TO 118:1:VD ANO - - Sii POW.R DJSTRl9UTON A8D NTEAPAC Pea TQtJti.llHCXJTNG: CMECKCMLE FROM CONMCTOR J3 ANO W1PUHQ AT Dfl:00! TROUBLESHOOT POWEii DtSTRUTON ANO NTERFACE -L F fflll HOPATV 2. TROUtlt.ESHOOT OECOOl!A. - BASC r>ec:onfl LOGC UNT FUCTfONMJ. REFlfl TO OPTON CMECKNGPROCEDURS TUTS EHAGDCM 8GtlAL SWTTCH..,... DU:MJGULEAOCM SGNAL SWTCH ON STATUS Hl'UT TUT' CMU " "'" AND NT OtSTR*"lON RF ACE flc8 AHDCHECKJNTE& CONNCTHG CAAi FRmlCOMNECTOW SL,r:mu NONJATV. 2. TAOUSLEMOOT OCOOR. Figure 5-36". Basic Decoder Loc Unit Troubleshooting Guide na'l C-"tn,,,.,,.

187 WABCO """...,, VERFY DECODER LOGC PANEL S FREE OF SHORTS N DC POWER WRNG CHECK TRACK AND KEY ) NO ON CRCUTS. SECTON STEP 3b CHECK RECEVER ) NO SENSTVTY. SECTON PART Z GO TO DETALED DECODER PANEL TROUBLESHOOTNG. SECTON Z NSTALL DECODER PANEL N WORKNG DECODER LOGC UNT DRAWER. SECTON ' PLACE ROTARY SWTCH ON RECEVER TO POSTON 2 (NORMAL) SWTCH ON AC POWER TO DECODER. CHECK DC VOLTAGE ON DECODER PANEL. OEENERGZE TRACK CRCUT POWER SUPPLY ' NO CHECK TRACK CRCUT. ;::.,,_... SECTON STEP 4b ENERGZE TRACK CRCUT POWER SUPPLY PASS TRANSPONDER COL OVER WAYSDE COL AND REMOVE CHECK CAB SGNAL CRCUT. SECTON STEP 8b NO CHECK FOR OPEN POWER WRE, CONNECTOR Jl-3 (BJl) ON DECODER PANEL PLACE TRANSPONDER COL OVER WAYSDE COi LAT 12" - 14" HEGHT, use NON-METALLC SPACER NO GO TO DETALED DECODER PANEL TROUBLESHOOTNG. SECTON 5.9.7,2 DEENERGZE TRACK CRCUT POWER SUPPLY CHECK MASTER RESET ) NO.1 CRCUT. SECTON STEP 2a CHECK CARRER DETECT NO CRCUT. i) SECTON STEP 5b CONNECT STATUS NPUT TEST CABLE TO PRO GRAMMER. ENERGZE CAB SGNAL ANO LEAD fl SWTCH!:.$_, TURN TRACK CRCUT POWER SUPPLY OFF; THEN ON DEENERGZE CAB SGNAL SWTCH, LEAVE LEAD CAR SWTCH ENERGZED ON PROGRAMMER CHECK TRACK ANO CAB SGNAL CRCUTS. SECTON STEPS 3b AND 8b ENERGZE TRACK CRCUT POWER SUPPLY REMOVE TRANSPONDER COL FROM OVER WAYSDE COL PASS TRANSPONDER COL OVER WAYSDE COL ANO REMOVE ENERGZE TRACK CRCUT POWER SUPPLY. PASS TRANSPONDER COL OVER WAYSDE COL ANDREM_OV:. DEENERGZE TRACK CRCUT POWER SUPPLY (TO SHEET 2 OF 21 Figure BasiC'. Decoder Log-ic: Panel.. Traub-1.esooting Guide i (Sheet l of 2) i , p /108

188 WABCC (FROM SHEET 1 OF 21 NO CHECK CAB SGNAL CRCUT. SECTON ;.9.7.B STEP Sb CHECK FRST MESSAGE ) NO Jil FL1P-FLOP CRCUT. SECTON B STEP 11 CHECK DAT A OUTPUT ) NO.i CRCUT secr:on STEP 13C NO CHECK GA TE A4 SECTON B STEP15C OEENERGZE TRACK CRCUT POWER SUPPLY DECODER SERAL DATA OUTPUT CHECK OEENERGZE TRACK CRCUT POWER SUPPLY PLACE ROTARY SWTCH ON RECEVER TO POSTQN 3 (TEST RECEVER ENERGZE CAB SGNAL SWTCH AND OEENERGZE LEAD CAA SGNAL SWTCH ON PROGRAMMER SET PROGRAMMER MESSAGE TO ANO LEO CAA SWTCH ON. ENERGZE TRACK CRCUT POY'/Efl SUPPLY. DECODER TEST MODE CHECK NO CHECK CRCUTS. SECTON B STEP 16b ENERGZE TRACK CRCUT POWER SUPPLY. PASS TRANSPONDER COL OVER WAYSDE COL AND REMOVE. ENERGZE LEAD CAA SGNAL SWTCH ON PROGRAMMER PASS TRANSPONDER COL OVER WAYSDE COL ANO REMOVE NO OEENEAGZE TRACK CRCUT POWER SUPPLY CHECK CAB SGNAL CRCUT. SECTON STEP Sb PASS TRANSPONDER COL OVER WAYSDE COL AND REMOVE CHECK DATA OUT SGNAL. SECTON ; STEPS 12 ANO 12a PASS TRANSPONDER COL OVER WAYSDE COL AND REMOVE NO GO TO DETALED DECODED PANEL TROUBLESHOOTNG. SECTON PLACE ROTARY SWTCH ON RECEVER TO POSTON 1 (TEST DECODER CHEC-K FOR GOOD ANO ERROR MESSAGE STROBE PULSES. SECrlON B STEP15C NO GO TO DETALED DECODER PANEL TROUBLESHOOTNG. SECTON DECODER LOGC PANEL OK REPEAT PROCEDURE > 1111 AGAN. YES NSURE ALL STEPS ARE CORRECT. l i i j! i CHECK DATA ANO r5ai'a SGNALS. SECTON B STEPS 13A, B, ANO C Figure Basic Decoder Logic Panel, T:roub.leshooting. Guide (Cont' ct.) Sheet 2 of 2) 6042, p /110

189 WABCO '-,/',A)y' DETALED DECODER PANEL TROUBLESHOOTNG GOOD AND/OR ERROR MESSAGE LEDS ON CONTNUOUSLY. PART V PLACE ROTARY SWTCH ON RECEVER TO POSTON 1 {TEST DECODER} YES GOTO GOOD ANO ERRORS MESSAGE LEDS BOTH OFF AT PLACE ROTARY SWTCH ON RECEVER TO POSTON 2 (NORMAL} NO CHECK TRACK AND KEYON CRCUTS SECTON ZC STEPS Za ANO 3a YES GO TO < AND ERROR ) NO ERROR MESSAGE MESSAGE LEDS.. j 4 4 i LED FLASHNG AT OBSERVE GOOD AND ERROR MESSAGE LEDS GOOD MESSAGE LEDS FLASHNG PLACE ROT ARY SWTCH ON RECEVER TO POSTON 1 (TEST DECODER) CHECK TRA! SGNAL RESET TOG OD AND ERROR ME SAGE FLP-FLOPS, TEP Zb. YES RETURN TO BASC DECODER TROUBLESHOOTNG PROCEDURE SECTON GO TO SECTON: GOOD MESSAGE LED FLASHNG AT CHECK RESET SGNAL TO GOOD AND ERROR MESSAGE FLP-FLOPS. STEP Za NO CHECK TRACK OCCUPED FLP-FLOP CRCUT, STEP Zl> CHECK GOO!. AND ERROR ME SAGE CRCU S STeP b, YES GOTO GOOD AND/OR ERROR MESSAGE LEDS CONTNUOUSLY ONAT NO YES NO RETURN TO DECODER PANEL TROUBLESHOOTNG AT PLACE ROTARY SWTCH ON RECEVER TO POSTON 1 (TEST DECODER} Figure 5-l8'. Detailed Decoder_ogic Panel Troubleshooting Guide csheet 1 of 3}_ , p /112

190 WABCO GOOD AND ERROR MESSAGE LEDS BOTH OFF?ART ERROR MESSAGE LED FLASHNG PART 11 (FROM SHEET 3 OF 3) RETURN TO DECODER PANEL TROUBLE SHOOTNG AT CHECK DECODER OUTPUT TMNG SGNALS STEPS 1, 2, AND Za -NO TROUBLESHOOT OUTPUT TMNG LOGC STEP 2b RETURN TO DECODER PANEL TROUBLESHOOTNG AT LOOK AT ROD SGNAL TO DECODER NPUT TMNG LOGC. NOTE WHETHER SGNAL S CORRECT,.E., ETHER ALL GOOD ANO/OR ERROR TEST MESSAGES OUTPUTTED FROM TEST GENERATOR STEP 1 RETURN TO DECODER PANEL TROUBLESHOOTNG AT Ri::>01flGNALHS" CONTNUOUS GOOD MESSAGE. CHECK DECODER NPUT LOGC AS FOLLOWS: CHECK FOR ERRORS AT GATE A11 STEP 3a i NO LOOK AT DATA RELATED SGNALS FROM TEST GENERATOR. NOTE WHETHER TEST DATA. DATA OUT, AND ADD SGNALS ARE CORRECT,.E. ETHER ALL GOOD ANO/OR ERROR TEST MESSAGES OUTPUTTED. STEPS 3, 3a AHO 3b CHECK TEST MESSAGE GENERATOR CRCUT. STEP 3C NO NO YES CHECK MESSAGE RECEVED, DATA GOOD, AND GOOD AND ERROR MESSAGE CRCUTS STEP 4a YES NO YES CHECK DATA LOAD FLP-FLOP STEP 2 NO YES - CHECK ERROR DETECTON CRCUT STEP :Sb CHECK ZERO ERROR DETECTON CRCUT STEP :Sc CHECK SERAL MESSAGE OUTPUT CRCUT STEP 3d YES CHECK GOOD MESSAGE NDCATON CRCUT ANO DATA LOAD FLP-FLOP, STEP 3 -YES CHECK BCH ERROR DETECTON CRCUT STEP 3d CHECK PHASE ENCODER CRCUT STEP.3' RDDSGNAL MUST BE NCORRECT SYNC ERRORS ONLY ARE OCCURRi iig DURNG MESSAGE CHECK SYNC ERROR DETECTON CRCUT STEP 3 Figure s38. Detailed Decoder Logic Panel Troubleshootingr Guide (Cont'd. (Sheet 2 of 3) 6042, p /114

191 WABCO (TO SHEET 2 OF 31 a LOOK AT ADD SGNAL TO DECODER NPUT TMNG LOGC. NOTE WHETHER SGNAL S CORRECT,.E., ETHER ALL GOOD ANO/OR ERROR TEST MESSAGES OUTPUTTED FROM TEST GENERA TOR STEP 1 RETURN TO DECODER PANEL TROUBLESHOOTNG AT CHECK RESET SGNAL TO DATA SHFT REGSTERS STEP4 4 NO -NO NO CHECK f'eset FLP-FLOP STE!P 4 l YES YES CHECK DATA LOAD FLP.FLOP STEP 2 CHECK DATA SHFT REGSTERS, PARTY GENERATORS, BCH CHECK, SCH ERROR, ANO RESET FLP-FLOPS N ORDER AS STATED. STEP 4a NO CHECK ERROR MESSAGE YES NDCATON CRCUT... ll. AND DATA LOAD FLP-FLOP STEP3 ROD SGNAL S CONTNUOUS ERROR MESSAGE. CHECK DECODER NPUT LOGC AS FOLLOWS: Figure Detailed Decoder Logic Panel Troubleshooting Guide (Cont'd.) (Sheet 3 of 3) 6042, p /116

192 SECTON V DRAWNGS AND PARTS LSTS This section contains assembly drawings, schematics, logic diagrams, timing charts, component locations and parts lists for the AV system. 6042, p. 6-1/2

193 WRSCC &'5104 DESCRPTON ]ll OAW& RJ4Sl4&6h401(CHASS S (WELDMENT (Ml4514E,Gjl301COVER,FRONT Dl4514E,,j 13 4 Jlso1262J SC.R,G-32x la PtJH.STL 4 s. J04i662' WASHER,*& ST... LK. s 4. JS&0840j FSTNR,li>-:!>"t SELi' C.LNC.H. E, 4. J(SE,0865) FSTNR,10 32 SELF CLNCH r-.. -* 1 rµ J. -,;;:- -1co.,_,..,,!,t (REF.) (REF) 1l.., "?, l i6 m..1 '&" _J,_ VEW ''A" SHOWNG CABLE CONNEGTOR FOR JS C.ONNECTON (SCALE; 12.N.= FT.) 7. Ni4Sl466jl'O!C.ABLE joj4s14&6f cr,4 40JC'!ila PNH. sstjvjson97l 01 q 12. WASHER, *4 STL.LK JUT,4 40 ME.X. STL.. Nl4St4&G 11qoztCABLE. Dl4s14G Jtsz1oa, lsc.r, 2-s&x 3/e FLH. STL && ĪS. TE.,CABLE SELF LKG. 16. CLAMP,CABLE.. MP 4N 17. SCR,6 32X '12. PJH. SST. 18. WASMER,6 PLAN STL. 1q. J )NUT, HEX. STL + l +... r c.r , 1 L J r-,tex> <", -411L 20, Nl4SS lPC8, AV TR... NSPONDERDl NSERT,AL.4-40>< 1/ SCR,4-40X S/10 8DGH )WASHE.R,.. 4 P\..AN STL 24, Ml4S 139 l'1701la6el '11 '17 25, 'Mf4Sl496(4001jPLATE, NAME j8f4sl4'16f 40 2&,. 07(,CONNEC.TOR MS lS 27, Jl70'!160!CA8L.E CL.AMP 28. :J( USH NG,AN3420- Z.!< 2q.. J06S004 6AG,SX8 MUS...J (TO BE: CENTERED' ltj COVE.R(TEM 2) SEE VEW "A' TEMS 26.zi' 8:. 28 TO 6E PL.ACED J MUSL.N - 6AG(1TEM 2'3)8c.TEO TO OUTSDE OF.CASE. & & &. WMEN NSTALNG PLUGS Pl 8c?2 OF' TEM 8c:. PLUG P3 F' TEM 7 ALGN!'"LAT ON PLUGS WTH!'"LATO SOCKETS! CRCUT D.i.GRAM PER D'WG 0451'!1110 5H.-1?.01, 1?.0?. & 1?.0:l E.$T Pe:.A. Sl>E:C.. E:.U &?.44 l,!-! RUBBER STAMP 1 /a MGH CHARACTERS USNG SL.ACK NK_ US AS SHOWN MATClt1111t../WCCll'CATtOl9 :::: i:;;;;:;;;;;;:,;;;.;;;,;;;.;;;;1,;;;,!:;.f'-'::::;:;f;:f"::;-:-;:'4 1t:-1:1-::-... 1"11rr.r---:::J:::T.:r-'""!l"T-,-r:r... r--,...:.. o ==.;.-E:."'.::-::F.:.-::..: ;::::.:::-:::-.:::::!:;;::::::=::::::::::::::::::::::::: f 10 -fl J :; ;gr- :...7..:=-==-:::: L ::.::::..s:;::,..:.3"!:rdj %":>Ull.tl ;> a :. :=:=:.:.-::, _,._.. Q - 4 fll!:4,jcl)q, Q _...,.,..._... AHOUf.AA'Ol'MNOHS.:.1 ro_--- :... 0 :c:2 o ; ::..-...:.:-::-..=:::.:-:.: SWSSYAU PA lull u S.,t :;::: Figure 6-1. AV PROGRAMMER ASSEMBLY 6042, p. 6-3/4

194 u ,SS -, - g,t...,----:.r-r-1:. 0 1;:: 2 ;,. : L- -.,.-t-'1;1;;;-,o! -.. ' P> 1j 01 y :,; ShEET 1202 J! r 1 T T r l' 1 - O<. Ml 029 SPARE sn "3 0]0 ll SPARE 81 T fft SPARE 91 T #-1 D 'H DG T pee UNTS CA.ft NO. 02,4 acoa 0 ' 14 en, D 14 ilctl; O 1 l4 iicil1 OS.. ijco 011 lll icoi 2 1 l.. i'co'i o,,-14 D O 14 8CD ac, 1, l r 01, till iic6i DZ< t4 ilctl; D!> 14 nl Q! w : 13 9 P4 P5 Pl P1 Pl P 401 Q ol C$ 12 B T SH FT REQ STER 0_?1 OU..., N914ALL i 010 C O 15 '... l '" GT!.!.r--.l. M NO!.!1r-.'....fTHOGT HUNDR 0S CAR DGT _!.;,4 UH TS ROUTE' J J2 FR JRD DGT THOUSANDS CAR NO FOO ST DGT TEPfS ROUT!: c 1: ' '" SHEET fzoz 1 ; r.. 1li 1;:1:: e 1..,- OUMP PUSE GC' p 9 PAA TY t oct VSS BCH N vss 11,.,,,,J,... : - -,4049 lc7, 10! :_o i ii'(jcloc! ; -.. vss i N.. "... ;: 8 " 4027 p '. r! C> Q!--... ""OUNr r "., OA 108 A 118 lza rza t'ja 1:sl' ' J 4519 C4 QUAD 2 M'UT MUX B 14 8CH OUTPUT ENASU ZO Z l Z DATA OUT r.;p " voo T BNARY RPttt..E: COUNTER A SE'rj 1 CJ 'ESET re tcz w 9J 919, o:.7 7'a'J' t 4 JJ 12 e "' FA r COUNT,.:'Jl_Q ,a,, lc7, vss S[T J '1c.';: r, ""k,od,010 CU 4010 lcjz 11EsET Q olt!-- )'9,ss tjnus 0.:.ATES voo---- vss vss ',010 tcr o C PN 5,01 4 'JOO.!.....,ss l c, 2 +. J.(F'O OK r TAHT VSS.M OUT S [C9 SHf:ET 1102 C!::> SH!!T 1202 WABCO! i l i 1 i i z.,kkz CLOCK BCl:f_ C_l_flt:tJU_r... Z 9 CLOCX Q,015 C &1 T 9ttlFT REG"STER 4011 CO o 1c11 t')!l d<o 1C9. OUTPUT SH FT CLOCK 'Q PULSE E:_St.!. vss 9CH C_RCULATE' CLOCK 4015 C 4 81 T SHFT ----a REGSTER Ql "i[ C C z PllOGl!Ml R!JNT Pr:_11 Ty_ 8C..tLR N45US j F'5U15 SH_ - 1 U(a Cl f_'.)_.:!)j o '. OMN.. RB c:-;! ::; < STD CRCUT DAGRAl.6 FOii A!JTll VEHClf OENTF'CATON VEHClE Tl) WAVSO: CO.WNCATOt.S!'VSTEl.l W,..BCC WUT1NHOU$(-AJR BA COMPANY DU( CN 4-! 3-1, 'l=irti::l5s::::; fi:,. 1TscS:lutTstsG1vc.. o'i.!!j.. SU-..l1..o T ==fllt TO'' 1'M1SbOCV t:n1'0 tt};1,"1'sa N01'TG-OOa fl\t :t.i(tf t'iw=f ":"'::{ r, 81 W:TO,,, l... OQJHJ.ANO K- C. jo,,cjatol'j THTS - Q f -,ot Yf.;;g H.C1'10f'J Oii'" SUCH A SVSK NTO &l77$..u oaa... NU... 5:Wi'LYr:r'g:: -..., ,m UNO SWTCH SCAL DVSON l Figure 6-2. PROGRAMMER LOGC DAGRAM 6042, p. 6-5/6

195 WABCC txternat.. NPUTS JS""' J... JS-<: JS n:: WHT& J3- JJ-lS JS- t. t J.&K J.&K f.:tt.:tl Rll R).--,,;-,-, CS N:;A _......; :... L_l L t!?..j. r-:;;.7-, Lw JT!.,K 1Ntl4A 044 -,- --,- '-..lc!,! -.. rrsj L..!.C!_l. _J R... Vl>O,, _,srspar lo {LEAO CAR)... J OOK NO SPARE (caal SHEET ZO SHEET 1201 SHEl!T 1201 NOTE. VOO CONN :CT 0 TO PN'' Ok 1c1,.z,1.,s,11. TO PN l4 ON lc1,1,10,11,1s,1.c ANO ro,... OH 1CJ.. NOTE z vssco ECTtO TO PN ON,lct,Z,J,,5,7,11 TO PN 1 ON JCl,t,O,lt,J[,.14 NOTE 3 UNLESS OTHERWSE NOT 0 AL R S STORS AU a, sc NOTE 4 CAB\..ASSEMBLY UH.&SJ 4Sl-t) 01 JS-<' llltlnt J'..1-J JS.. J-fl,J-l 4 -ET 120l SRT llof : : 4N2sl7 K 1Ntl4A ou 1. C '-----' 2N3'4S Q R7., - OOK 4THSPARE,.. SHEET Nll 4A 03& N 4A... _<) r---- TR - -- AN.MT COil {;:;:, J4<--,iffii,i," ls.sotz 6 (.ooaa 111'0-1 u TURNS 8.;!UA J1-1 J4-f:.,. T!" E un s1,,s-oso1 ( VOLET) L--...!'"!.NS!! ';!!!t._ - _ J (ca11u:) J H) (s1uu.ol ( J>-t 10 O ( :),u; l+ TANT.!SYT 500 ton ti VOLT ZOR tn474za RO,rom i. tos4 ZENER ln5s519 S llmtt POSJTtW: J.+ Cl 1111'0 VOLT' l5v TANT.... COMON R UK v NOTt SHEET 1201 TO?CS SHEET 1201 r , R CEVE COL A, n.tmnz. 215 UFD 2" Z TUAHJ i' uth L - = "!!L_ - j t.t NOnt SHtET 1201 r::, tcs PlftlGRAMER UNT._ :.,..,. STO CRQT OAGRi\16 FOR AUTO VEHCLE DENTFCATON g VEHCLE TO WAYSDE COWJCATONS SVSTEM Cl Q Figure 6-3. PROGRAMMER LOGC DAGRAM (Cont'd.) 6042, p. 6-7/8

196 WABCO RC= lc-pn...,.to '., "HZ C..OCK lcz...ph Z en COUHT A STAR lct... ln 4 81TCTU,l STAU t ----' tcz-f'n ii at"t COUNT 11 ST"31[ 1 CZ-fllN Z e ,-- FWE q tcl.flllh - tcl...pn ' s Cl-,,N l,; - ---!. 11CH RCSltT C3...PN 14 l CH OUTl'T ""... C1-,, CUW"'LS tcl-fll'n 4 OUTPUT.n n n n. n, n. 9HFT "'"" ' lc... N O :=-;"ff ru---u-u n, u Lil 1- ARN ru ZCU...,,NU 1. ful _ Lfl_fl_J ru L.l u 1, 1 :;... : n_ru LJ LJ LJ!ml n DATA OUT lc4.pn 11 PSJl OATA CJ-PN '-... nsu LJ LJ LJ n r1j. llj '., 2 l l 1 0 " '2 l ",..,, j " " " 1 l u n H Sl"NC BTS ROUTE TENS icls ROUTE UNlfS ico CAA NO THOUS R15,R NO l«hdfleos 'RD1 CAR NO TENS e CAA no UNTS R"f> XTRA BTS lf:1 &CH CHCK BTS : l at,.., u,,o " u " " '",. 1 37,,. " '" l ", " " J '" l " J NOTE SET SWTCHES.,....EAO CAft BT. PROGRAlllER UNT TAN:...,...!,-_1_1: STD CRCUT DAGP.A16 FOR AUTO VEHCLE DENTFCATON & VEHCLE TO 111\YSOE CCMJNCATONS SYSTEM Figure 6-4. PROGRAMMER TMNG DAGRAM 6042, p. 6-9/10

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208 WABCO... t c l9pf m RU 1100.J' RU z.nt (1'1.1-zlrl'ST > \N, OS.?Nl, TP... U OOHZ 4 q -----u 4..._Jl t C2l CM llopf! T ""! ->SPFD xfn!l--le---<o,...--,clock FREQUENCY ADJUST G f J9PF TP-5 l R...SK fpt_1- l ,PN ] CL::X:'( :lvt 2. 71( Z lk -f ) P.N 1 Pt.1-8} r.. Rc" -----! -..:,. oi,1 ;Pll-10) NOlltl. < i-- --.,. i:-t,t 5 (PLl ct) ':'-OC:>0.. LEO. LLWNATt'D N S fs lff T-RVCR :>A T..COOO. PSJTl:>N.. '"( '-'"'\ 4 (:.'.-:) ]!)Tl T-RCVR-.1.l ll,... ll (Pl.,-..) lz c TPZ L r Cl AJ : - 1${4 OOOF... TP') Ll C2.. = 500 OOOPF,.net: OOOPF... Cl J. J.. C25 PF, " " J2 Y )) n L4... R7 M C21 lspfo TP6 r "'.:----e j"'l' :ci,,., Rt SOK C7 OOPF TP7 ca RO.OWO ZOK R ZOK... 1/1/11 20K Rll \N, ZOK PU, Ctl+... CU vw----lf- ZOK MFD CZ7 SOOPF... S.11( H$2l K R! OK TP 6 l ,tA CS.OMFO (P1.1-ol Pfl'!f RECEVED OATA 06 NSllS RU OK. "" 1.:;uC. (PLl-f) PN 15 CXR OET. 1-,l.-P,H 16 V UHRE.GULAf 0 lok D Ml14 2TSUH ;11 1 " ±_Cl.:,.oollfMl'D cu - "'- ltlc T'Pff y CJ JOOPF' C0404aA! 8 TP,J Jf JC2 C0402?M!: tcs f 2 Q C RU OK Rl7... Of NU cu.j.+..,.,. 1"' t...;.-;-- 1i ::;.. r - N47«Jl+Ctl WD +elf,ov14,7 TPl9 UC 45131G. O"O f e _. ) N l..,u,o. l,.11iwo. wo (PLl-,l 17 +y R 0ULA TED ,>) (PLl-11 T:) PH PC8 REC VER _g_aq_uho isl STD. CRCUT DAGRAMS F AUTO VMCL1! OE:NTRCATON 4 VE-\CLE. TO '.A'(510E c;::.r,,mu1'jc.ton 5YTE"M :J ;:;....,..t Ud lr.'211 t:l!!hf-'. -ruo-. WABCO W SlllliilDU$E 811AU CG11PAiiY Li:!>.. / UNGtt SWTCH & SGllll OMSO -- -Ml-!!!!,P!fflWLPf.1:.<:'",,,_,_,, 1-..:- 1 D. 4513'16 c1ns _.. "... Figure RECEVER PCB SCHEMATC 6042, p. 6-33/34

209 tf e - 4.Goo'... z,oo"" WASCO a, ooa 1.00, DESCRPTON KOLE =ll Dllll S1Z 1115 HOU 1 =ll UlllL $.Z[ G33 NOL 1 =fl Ollll Sil( ; ljtl HOU: 1 =51 OltU SU ;! a t.ll! OLE =66 Hill Sill 19 Gil MOLE! =51 Gllll SZE >,1,, ( e 'o.. 1 't!>' l("'\..1'"1 C5 U /! n L FOR APPLCATON luraed!hus SEE OWG. SERES MMEDATElY AFTER ETCHNG CRCUT REAT PER PT : BRUSHCOAT ll OVER. AFTER All COPONENS ARE MOUNTED. REAT PER PT ispraycoat ALL OYER & 9 32 LENGTH OF =22 BARE TNNED COPPER WRE UA43183 TO BE USEO AS Piii THROUGHS. SEND.OVER AND SOLDER TO PADS ON EACH SDE. SEE APPLCATON DRAWNG SH.0205 VEW T ( PN 'rhru ON T RMNALS l THRU t8j. & RUBU STAMP SERAL NO. OF EACH PART NUER SEQUENTALLY USNG BLACK NK US idn UPPER LEFT SDE OF CRCUT 80lRD. 5 aouo TO BE TESTED PER EU SPEC HO. EU-59<19. RUSSER STAMP THE Pt\OPER SUFFX NQ USNG BLACK NK US340.45? l Cl.bl+ CJ CS.12._!'.S C7.ll c::,11.2 C Cl9.Z2.U cw CZ -Z: RZ. z... -m QNllflCAltG Dt...C WRBCC Clhlll ouuw,,.. t... f&}t'... r:t1 1mlsn,,.,.g f.l. N COi! v.a. POT tlzw ))!OK 114W M 114W sioi<ii,iii ToiCT,iw ;11t 114W Ult_t14W 47tL[14W lzkj... W ll,,_ 114 4l!Ul l/4w J.6K_t14W. 12,n,.n u 81. 0,! -... Tl XT4Ll LEOl SW?L TP!-TP C9 C1_& l} JJ J l! )} }] ' F PCB rs ASSEMBLED 6Y HANO SOLDERNG re, NDCATED.Mll.ll BE NSTALL D USNG GROUNDED RON ANO BENCH, AFTER ALL OTHER COM PONENTS HAVE BEEN NSTALLEP AND SOLDERED BOTH TOP A BOTTOM SDES. F PCS S ASSEMBLED av WAVE: SOLDERNG re,!ndcateo MUST 6E NSTALLED, AFTER ALL OTHER' COMPONENTS. UTLZNG GROllNPED 8ECH ALL TOUCH UP AND TOP SOLDERNG Mlli BE COMPLETED USNG GROUNDED RON AND BENCH ;-t 'r' ' UN45! j CRCUT SDE '-- Jl ' '"""' - V J,8 F ON USED ::: l ll ,_...:i: m MAX. COMPONENT H 1&MT it ",,o " '" "" - m ' ' ' - - m ""' = """Rooi;:\o OF BDAr c'1louct011 CRCUT SDE / './ --, L UTSRPNMLKJ Hf EOC8 COMPONENT SDE MU. COMPNENT HEGHT a if A r;;;; SS '\ j COMPONENT SDE \\ ' // PRNT 0 CRCUTS ON BOTH SDES MUST BE MASTERED EXACTLY OPPOSTE EACH OTHER USNG TOOLHG M0l S@., L-..; r- \ _,s-,oftypj F"OR SCHEMATC DAGRAM SEE OWG SH.0701, N4 H 404 s,01 j PC8. AV 11 C:EYEJ! ;,!! ii STANDARD P...Ult N HNTED CACUT AD.(... ::-. ""' H siiiJ).. -.,r ( VA.CQ.:,.... " :... u...,r..., -:;....,.),.,,,,o......,... 11,..,...,.,..,., Figure RECEVER PCB COMPONENT LOCATON 6042, p. 6-35/36

210 WAS CC PN PN,.., ov..,: PU l 15- 'u PalER WRNG LOC' :!A::f!;:A; :All.Alt. Aal,AU',A2S,All,A2:,AJO, au.au,au.,aa:o,a11,12s Al.,A2.,AJ,A.,A'P,Al,AO, Au- A22 Al. A ,81 81.a,,ato,ai,,et,,iin,a,i, eu.,zz.. 11,atT,az1,a,o 9J NTERFP.Cf l'rng 8J SG A 14 - ti Sl8 8 & OV ov - UOY 15-uov l-tsov JUW!'R: ajt - s,,,r "' v.! $ 'l'j ::' Q ov - _!C_! OC,-!J )"!.., :; ::::qi Q CP J! Z RO TEST COUNffR 4014 AT,) 15S.,CNZ (icp. AJ n AS-S 21C az-11,,... :ex" ocr,.,..... ll_l ll_.l! l! Q Qt QS Q4 Q5 Q <U R - a,-,... CLOCK ov DA..A 19_ ov RESET AJ ua-7 w -,.. :. Atl-4 AU-t All-tO t2k AU-7 T 1UP 1 '" :,os AU- All-,..,.... ov 4.Nff OY + eu-11 a,...,...,... N400S ou OEcaER L<JalC 1iOllA.E PAEL.;y, STD CRWT OMiRMS FR AUT<l-'El!la..E OEM'FCATCN & VEHla..E TO AYSE CCMUflCATla«i SYSJEM 020 Figure DECODER LOGC PANEL LOGC DAGRAM 6042, p. 6-37/38

211 WABCC..._ 3 TC'T BJ R : 10) TR GNO C> hlstr, - MSG REC SJ-Z.S ov ' loolt +A5-3 AS-14.j, '! l {Do ERROR SSAGE 10 J Q TRACK CUPtE:D s ea _, TRA,CK Bl- Bl- Ol l L 0 2K 8J.,,., \.5ln11J 83-2' az ::' 915' O j ? ,.. J Q Bl-7 1 ica8snal GOOOMSG CLOCK' ,Y.,V'-O..-+ a2-,s K q!j.: ;:E>J OV R 40tl >w,w.... " 11 & 811 f,, ov TRAK Ll _g!rolt g_ - 1 GOOO MSG u. RRO!! "50 r;!.,.. - J.. ti AJ nu Q Ell ov J BO 1:0_J 01_ 0 1>!.o.:z _o o <H,1 > z1 ot r,i, Q - l QV -,.,., n,,'-.. oe:t is vse oa, :J., z t}- BZ, -- OJ' X_!_....,J =rau j,1.,t.f T,, i5r, :v.---tlp(s 401:1 l ;;1 CLOCK SJ 1. Qt Bl \-. 2 SER N 11 G.t UC rn:a:ia. 104s hou-w u-11-u _(_Fffl.OR DATA ::UT recooer LOGC WlllE PAt,EL 1-. c :,.. J # J i.. ;ii r i,! <5 flt._... "-="';'" l't - l:i!iji i K O-,!t-7.C Figure DECODER LOGC PANEL LOGC DAGRAM (Cont'd.) 6042, p. 6-39/40

212 WABCO.;. mnaclo 1 >Qf:CL 'de -. > JST SN entr C:T44 AU ot, S 4 10 AU ft l,,!uh,!' '110 Q9 qlql i "' CZ r"<f. HT... CHTR z -Y=-----r L!!<l.:::. JOOHZ.OHZ 14,ZCZ z.tlqtz t t c.., "'. HW H! O v. - i,:_. - -C--u_ C 4027 SK AU!- ::j-., - _lst&chtr' erst 4C>tl c U AJ au All AH )2, f -"- L., - AU s R i ov h s , ct, 4 ovj.tx ':!: Lf.- - L...., htl... :,--n-,,.,a ov usa, OMC. BJ0/1. j)j) ov AJ! GM+ EM } GST +... '"' + $MC AJ TEST ) 10 iiioi,, b + rj!- 1:),!:RROR-1 J 401? l:j Al tl -,,... Nt-S ) :!Y UNllfl.eJ AS-S > Tffi"'iif "C.. z DATA OUT AS- "1 DATA -- ',c OM> q,p, ""t " J All..,.. AU ;...!. J ut-10 aa... ; + H ov J45Z OM1 C Bzt X 0 + X R az,-,.... Tl ov ZOOl'' aa...,1 t45z 2USEC au.<1.1!. H + 8H tl OK qf'---' + TRAK,...; ,--l ,...-t-,p""1--t-...--?"""-,.-t--,...f--10-,-<n 4015 w R 0\/ ll'ac lll:.j\?/\'j TST DATA z 2 OJ )... CP'Y :io!.. Ol 10 Sl1T1J a.s-t az- a1 t KEY OH ROD XFEA OAA 2 TUT DATA l 2 L COOER LCJGC J,dlU..E PA-EL '... Tlftt. CONllltCTOM -J-J_.. 4 O-t'l-74 STOCRCUT DM.RAMS Fa! AUTO-EHlctE 111:NTFCATON & EHClf TO WA'Slt CCJM.NCA TONS SYSTEM Figure DECODER LOGC PANEL LOGC DAGRAM (Cont'd.) 6042, p. 6-41/42

213 WAS CC ;;: T CT -----' AE'CE VE OATA AZJ PN ro AO PJN 10 START,no PM l 2U,... QS-CL All PN f DtCAY CLOCK az, PH ' zus-- l u u Li '.( C GATA ll PUt PHASE,, AO PH S OATA thl'ut AO PN. OATA Ffl AO,.N SYNC Cttt;CK A? i'n Z,vNC fjrofl At JllH 4 RCSCT Al l'h 14 C.OCK Alt PH S SC All PN Jt BT COUNTU STAM All l"n S 11 :1,sa r SHl,.T M&STEJt STAK t 81 fttn S L l«lte: Mll!SMiE DATA 11tOUT!: t CAR...at OUJ +- t.eao CAJ DtT ZERO BT l'ux,,_,. ',,:.,,_ '.! SYNC WOflO OK, 11 T couttnw SHf'1' U81STD tna81.!'0 a T COUNT J ROUT!' HQ. f!n - DATA NTO SMP'T Rl!81SffR DECOOER togc NUT Tll.tllC STD C CU T O AGRAAS FOil AUTO-VEJllctf OEHrlFCATlorf.t VEHCLE Tl) 'M'ffllOE COMJNCATONS svsm, Figure Decoder Logic nput Timing Chart 6042, p. 6-43/44

214 WABCC U TRAK i "'i PN 1..JJ CAMl R lllm!ct A25,1N 5 flcy DATA AtS fil'h ' (uo AO PN 10) START PN l qe-ci. Alt PN 4 zus.,. 1111:n ctae ' 824 "'" 1 J i tm llwl& GATA ll l't -.S! AO J'N GATA A.10,,.. i CSltT AaPN, C At6 Pfft 81 T COUNTllt STAM t ' AU PN J. ""' : rlr LJ U-U i"> 81 l'n S an coufff z All PN illilciir1l A61'fN Z ;- (1) M.SSM& DATA 1 OVTr t CMt HO.OU) + lead CAR 8 T (z) JltCV OATA AZ> l'u 10 (AO PUt JO) AND PHA8C AO.. N 1, fml" H OPPOelff P'MAH: WTHOUT Af"P'CTNe Cl'!:ATON.. rt All PN , DECOON9. UH i9 T i. i. i. i. i. i. r. i. i. T.,. i. r. i. i.'i. i. i. r. r.'f. T. T T.'LJ!.T. T. LJ. 1. T. T. r. T. r.1 L- SYNC WORD - l.._ ST oren," ZHO 01en, --L..-,wo 01e1T.,,. _J. TH 01en'1 ---l...- STH Df8tT""'2 --L- tth DGT,- STATUS WOltO----"'an &Cit CHCCC WORD - - ROUT«fENS Roun UNTS c1ttt NO. 'tmcc,jsac)9 CMt NO. HUNOftEOS CM NO. TENS 1 CAR NO. UNTS,- P«JTE t sh" RUS?Er DATA ""'"' OECOO H8 NDS llecooer LOGC 11\FUT T NG STD CRa.llT DAGRAM! FOR AUT'D-E!llct.E OENl'FCATON & VEHCLE TD MYSOE COJ,NJNCAT ONS SYSTEM WA BCD E :r Figure Decoder Logic nput Timing Chart. (Cont'd.); 6042, p. 6-45/46

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216 Al PN 14,A,!_C! ' DAfA LOAD 8! ,.,.,.. 5 SMCO Al9 Plfrl 14 DT AJO Pfllf J CLOCK AtJ "'N t...,... XHT CLOCC TEST DATA..,... :, nnnnnnnnnnn J L L L u L u L u u u l DATA OUT au l'fh fltffft XUT JO l'h ('D x aso,.,,. 10 Q-C\. Mt P'N 4 ROD 127,.N S AU PN EN-'BLC OATA U PN l DATA,:p, AJO Plff OC AU PN 14 s 10 U J 16 S 11? U. Z4 ZS ti 2T 21 Zti- JO Sffll'T Jltl:ellfflt ST""" S l'n S ic'iieti'c'ic Aa -"N Z RiTTiiioii'.,... t SYNC -tilao At JltN Ml&Rl'.C" Al.,.N f:lt PN STAll1' G' JC88 OECOON8 81!81NS DECODER M'UT j LOC A!SCT...,.,.. '-- ND "" W:SSME -, : kl_l-7i Dl:CODl!:11' TEST EUOJ MSe T MU STNT 0,, - Pett li&ssm'. TD CR.."UT DAGRAM! FOR AUTO-EHC.E ENTFCATON t.. VEHCLE TO WAYSE COMUCATl(JlS SYSTEM ;;--. 1.alll6 Figure Decoder Test Error Message Timing. Chart 6042, p. 6-49/50

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