REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. J Updated drawing paragraphs. -sld Charles F. Saffle

Transcription

1 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED E Added vendor cage for device types 01 through 05. Figure 1; Added the pin reference numbers on the top view of case outline Y to indicate the pin orientation. -sld A. Cottongim F G Added vendor cage for the case outlines U and T. Table I; VOL test changed the test condition IOL from 12.0 ma to 8.0 ma. Redrew entire document. -sld Added vendor cage 0EU86 for device types 01 through 05. Updated drawing to reflect the latest requirements of MIL-PRF sld Raymond Monnin Raymond Monnin H Figure 1; Case outline Y, changed the dimeion "D" min from inches to 1.6 inches. Editorial changes troughout. -sld Raymond Monnin J Updated drawing paragraphs. -sld Charles F. Saffle Update drawing to the latest requirements of MIL-PRF gc Charles F. Saffle REV REV REV STATUS REV OF S PMIC N/A MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A PREPARED BY Steve L. Duncan CHECED BY Michael C. Jones APPROVED BY endall A. Cottongim DRAWING APPROVAL DATE MICROCIRCUIT, MEMORY, DIGITAL, FLASH EPROM, 128 X 8-BIT, MONOLITHIC SILICON A CAGE CODE DSCC FORM OF E DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

2 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph and MIL-PRF A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: H X A Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) \ / (see 1.2.3) \/ Drawing number Radiation hardness assurance (RHA) designator. RHA marked devices meet the MIL-PRF specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-rha device Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 F CQ5, F /Q FLASH EPROM, 128 x 8-bit F CQ5, F /Q FLASH EPROM, 128 x 8-bit F CQ5, F010-90/Q FLASH EPROM, 128 x 8-bit F CQ5, F010-70Q FLASH EPROM, 128 x 8-bit F CQ5, F010-60Q FLASH EPROM, 128 x 8-bit Device class designator. This device class designator is a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF and require QML Certification as well as qualification (Class H,, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class H G Device performance documentation Highest reliability class available. This level is intended for use in space applicatio. Standard military quality class level. This level is intended for use in applicatio where non-space high reliability devices are required. Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Ipectio with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance ipectio (Group A, B, C and D). E Designates devices which are based upon one of the other classes (, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to eure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. 2

3 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style T See figure 1 32 Flatpack, ceramic, single cavity U See figure 1 32 Flatpack, ceramic, single cavity, lead formed X See figure 1 32 SOJ, ceramic, single cavity Y See figure 1 32 DIP, ceramic, single cavity Lead finish. The lead finish is as specified in MIL-PRF Absolute maximum ratings. 1/ Supply voltage range (VCC) 2/ V dc to +7.0 V dc Signal voltage range (any pin except A9) 2/ V dc to +7.0 V dc Power dissipation (PD) mw Storage temperature range C to +150 C Lead temperature (soldering, 10 seconds) C Data retention years minimum Endurance (write/erase cycles)... 10,000 cycles minimum A9 voltage for sector protect (VID) V dc to V dc 1.4 Recommended operating conditio. Supply voltage range (VCC) V dc to +5.5 V dc Input low voltage range (VIL) V dc to +0.8 V dc Input high voltage range (VIH) V dc to VCC V dc Case operating temperature range (TC) C to +125 C A9 voltage for sector protect (VID) V dc to V dc 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE S MIL-STD Test Method Standard Microcircuits. MIL-STD Interface Standard for Electronic Component Case Outlines. 1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Minimum DC voltage in input or I/O pi is -0.5 V dc. During voltage traitio, inputs may overshoot VSS to -2.0 V dc for periods up to 20. Maximum DC voltage on output and I/O pi is VCC +0.5 V dc. During voltage traitio, outputs may overshoot to VCC +2.0 V dc for periods up to 20. Minimum DC input voltage on A9 is -0.5 V dc. During voltage traitio, A9 may overshoot VSS to -2.0 V dc for periods up to 20. Maximum DC input voltage on A9 is V dc which may overshoot to V dc for periods up to 20. 3

4 DEPARTMENT OF DEFENSE HANDBOOS MIL-HDB List of Standard Microcircuit Drawings. MIL-HDB Standard Microcircuit Drawings. (Copies of these documents are available online at or from the Standardization Document Order Desk, 700 Robbi Avenue, Building 4D, Philadelphia, PA ) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulatio unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and shall be in accordance with MIL-PRF Compliance with MIL-PRF shall include the performance of all tests herein or as designated in the device manufacturer's Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and ipectio herein, however the performance requirements as defined in MIL-PRF shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, cotruction, and physical dimeio. The design, cotruction, and physical dimeio shall be as specified in MIL-PRF and herein Case outline(s). The case outline(s) shall be in accordance with herein and figure Terminal connectio. The terminal connectio shall be as specified on figure Truth table(s). The truth table(s) shall be as specified on figure Timing diagram(s). The timing diagram(s) shall be as specified on figure 4, 5, and Block diagram. The block diagram shall be as specified on figure Output load circuit. The output load circuit shall be as specified on figure Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Programming procedure. The programming procedure shall be as specified by the manufacturer and shall be available upon request. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked. 3.7 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance ipection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime -VA) upon request. 4

5 3.8 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturer's product meets the performance requirements of MIL-PRF and herein. 3.9 Certificate of conformance. A certificate of conformance as required in MIL-PRF shall be provided with each lot of microcircuits delivered to this drawing Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This reprogrammability test shall be done for the initial characterization and after any design process changes which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase cycles listed in section 1.3 herein over the full military temperature range. The vendors procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall be done for initial characterization and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity. 5

6 TABLE I. Electrical performance characteristics. Test Symbol Conditio -55 C TA +125 C unless otherwise specified Group A subgroups Device type Min Limits Max Unit DC parameters Input leakage current ILI VCC = 5.5 V dc, VIN = GND to VCC Output leakage current ILO VCC = 5.5 V dc, VIN = GND to VCC 1,2,3 All 10 µa 1,2,3 All 10 µa VCC Active current for read ICC1 CS = VIL, OE = VIH 1,2,3 All 35 ma VCC Active current for program or erase ICC2 CS = VIL, OE = VIH 1,2,3 All 50 ma VCC standby current ICC3 VCC = 5.5 V dc, CS = VIH, f = 5 MHz 1,2,3 All 1.6 ma Input low level VIL 1,2,3 All 0.8 V Input high level VIH 1,2,3 All 2.0 V Output low voltage VOL VCC = 4.5 V dc, IOL = 8.0 ma 1,2,3 All 0.45 V Output high voltage VOH1 VCC = 4.5 V dc, IOH = -2.5 ma 1,2,3 All 0.85 X VCC V VOH2 VCC = 4.5 V dc, IOH = -100 µa 1,2,3 All VCC Vdc V Dynamic characteristics OE capacitance COE VIN = 0 V, f = 1.0 MHz, TA = +25 C 4 All 15 pf A0-A16 capacitance CAD VIN = 0 V, f = 1.0 MHz, TA = +25 C 4 All 15 pf See footnotes at end of table. 6

7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditio -55 C TA +125 C unless otherwise specified Group A subgroups Device type Min Limits Max Unit Dynamic characteristics - continued CS capacitance CCS VIN = 0 V dc, f = 1.0 MHz, TA = +25 C 4 All 15 pf WE capacitance CWE VIN = 0 V dc, f = 1.0 MHz, TA = +25 C 4 All 15 pf I/O0-I/O7 capacitance CI/O VIN = 0 V dc, f = 1.0 MHz, TA = +25 C 4 All 15 pf Functional testing Functional tests See 4.3.1c 7A,8A,8B All Read cycle AC timing characteristics Read cycle time trc See figure 4 9,10, Address access time tacc See figure 4 9,10, Chip select access time tce See figure 4 9,10, Output enable to output valid toe See figure 4 9,10, See footnotes at end of table

8 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditio -55 C TA +125 C unless otherwise specified Group A subgroups Device type Min Limits Max Unit Read cycle AC timing characteristics - Continued Chip select to output high Z tdf See figure 4 9,10, , Output Enable to output high Z tdf See figure 4 9,10, , Output hold from address, CS or OE change, whichever is first toh See figure 4 9,10,11 All 0 Write cycle AC timing - Write/Erase/Program operatio WE controlled Write cycle time twc See figure 5 9,10, Chip select setup time tcs See figure 5 9,10,11 All 0 Write enable pulse width twp See figure 5 9,10,11 01, Address setup time tas See figure 5 9,10,11 All 0 Data setup time tds See figure 5 9,10,11 01, , Data hold time tdh See figure 5 9,10,11 All 0 See footnotes at end of table. 8

9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditio -55 C TA +125 C unless otherwise specified Group A subgroups Device type Min Limits Max Unit Write cycle AC timing - Write/Erase/Program operatio WE controlled - continued Address hold time tah See figure 5 9,10,11 01, Write enable pulse width high Read recovery before write twph See figure 5 9,10,11 All 20 tghwl See figure 5 9,10,11 All 0 Write cycle AC timing - Write/Erase/Program operatio CS controlled Write cycle time twc See figure 6 9,10, Write Enable setup time tws See figure 6 9,10,11 All 0 Address setup time tas See figure 6 9,10,11 All 0 Data setup time tds See figure 6 9,10,11 01, , Data hold time tdh See figure 6 9,10,11 All 0 Address hold time tah See figure 6 9,10,11 01, Chip select pulse width tcp See figure 6 9,10,11 01, Chip select pulse width high Read recovery before write tcph See figure 6 9,10,11 All 20 tghel See figure 6 9,10,11 All 0 See footnotes at top of next page. 9

10 TABLE I. Electrical performance characteristics - Continued. 1/ Unless otherwise specified, 4.5 V VCC 5.5 V and VSS = 0 V. 2/ Unless otherwise specified, the DC test conditio are as follows: Input pulse levels: VIH = VCC V and VIL = 0.3 V. Unless otherwise specified, the AC test conditio are as follows: Input pulse levels: VIL = 0 V and VIH = 3.0 V. Input rise and fall times: 5 nanoseconds. Input and output timing reference levels: 1.5 V. Parameters shall be tested as part of device characterization and after design and process changes. Parameters shall be tested to the limits specified in table I for all lots not specifically tested. 10

11 Case outline T Millimeters Inches Symbol Min Max Min Max A b C D E E E TYP.050 TYP e 1.27 TYP.050 TYP L Q NOTES: 1. The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound units shall rule. 2. For solder lead finish, dimeio b and C will increase by inches (+0.08 mm). 3. Pin numbers are for reference only. 4. The case outline T is available in either a pedestal or non-pedestal package. The Q dimeion only applies to the pedestal version of case outline T. FIGURE 1. Case outline. 11

12 Case outline U FIGURE 1. Case outline(s) - Continued 12

13 Case U outline - Continued Symbol Millimeters Inches Min Max Min Max A A A b C C TYP.030 TYP D D TYP.750 TYP E E E E TYP.050 TYP e 1.27 TYP.050 TYP ea TYP.436 TYP L 1.52 TYP.060 TYP Q R 0.18 TYP.007 TYP NOTES: 1. The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound units shall rule. 2. For solder lead finish, dimeio b and C will increase by inches (+0.08 mm). 3. Pin numbers are for reference only. 4. The case outline U is available in either a pedestal or non-pedestal package. The Q dimeion only applies to the pedestal version of case outline U. FIGURE 1. Case outline(s) - Continued. 13

14 Case Outline X Symbol Millimeters Inches Min Max Min Max A A b C D D E e 1.27 TYP.050 TYP ea R 0.89 TYP.035 TYP NOTES: 1. The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound units shall rule. 2. For solder lead finish, dimeio b and C will increase by inches (+0.08 mm). FIGURE 1. Case outline(s) - Continued. 14

15 Case outline Y Symbol Millimeters Inches Min Max Min Max A A A B B D D D e e NOTES: 1. The U.S preferred system of measurement is the metric SI. This item was designed using inch-pound units of measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound units shall rule. 2. For solder lead finish, dimeio B and e1 will increase by inches (+0.08mm). 3. Pin numbers are for reference only. FIGURE 1. Case outline(s) - Continued. 15

16 Device types All Device types All Case outlines All Case outlines All Terminal number Terminal symbol Terminal number Terminal symbol 1 NC 17 I/O3 2 A16 18 I/O4 3 A15 19 I/O5 4 A12 20 I/O6 5 A7 21 I/O7 6 A6 22 CS 7 A5 23 A10 8 A4 24 OE 9 A3 25 A11 10 A2 26 A9 11 A1 27 A8 12 A0 28 A13 13 I/O0 29 A14 14 I/O1 30 NC 15 I/O2 31 WE 16 VSS 32 VCC FIGURE 2. Terminal connectio. 16

17 CS OE WE Mode Data I/O Device Current H X X Standby High Z Standby L L H Read Data Out Active L H L WrIte Data In Active NOTES: 1. H = VIH = High Logic Level 2. L = VIL = Low Logic Level 3. X = Do not care (either high or low) 4. High Z = High impedance state FIGURE 3. Truth table. 17

18 FIGURE 4. Read cycle timing diagram. FIGURE 5. Write/Erase/Program operatio, WE controlled. 18

19 Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figures indicate the last two bus cycles of a four bus cycle sequence. FIGURE 6. Write/Erase operatio, CS controlled. 19

20 FIGURE 7. Block diagram. FIGURE 8. Typical output test circuit. 20

21 TABLE II. Electrical test requirements. MIL-PRF test requirements Subgroups (in accordance with MIL-PRF-38534, group A test table) Interim electrical parameters 1,4,7,9 Final electrical parameters 1*,2,3,4,7,8A,8B,9,10,11 Group A test requirements 1,2,3,4,7,8A,8B,9,10,11 Group C end-point electrical parameters End-point electrical parameters for Radiation Hardness Assurance (RHA) devices 1,2,3,4,7,8A,8B,9,10,11 Not applicable * PDA applies to subgroup VERIFICATION 4.1 Sampling and ipection. Sampling and ipection procedures shall be in accordance with MIL-PRF or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DLA Land and Maritime -VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA as specified in accordance with table I of method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Conformance and periodic ipectio. Conformance ipection (CI) and periodic ipection (PI) shall be in accordance with MIL-PRF and as specified herein. 21

22 4.3.1 Group A ipection (CI). Group A ipection shall be in accordance with MIL-PRF and as follows: a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 shall be omitted. c. Subgroups 7 and 8 shall include verification of the truth table on figure Group B ipection (PI). Group B ipection shall be in accordance with MIL-PRF Group C ipection (PI). Group C ipection shall be in accordance with MIL-PRF and as follows: a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test, method 1005 of MIL-STD-883. (1) Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DLA Land and Maritime -VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA as specified in accordance with table I of method 1005 of MIL-STD-883. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD Group D ipection (PI). Group D ipection shall be in accordance with MIL-PRF Radiation Hardness Assurance (RHA) ipection. RHA ipection is not currently applicable to this drawing. 5. PACAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applicatio (original equipment), design applicatio, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated as specified in MIL-PRF Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and the applicable SMD. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime -VA, telephone (614) Comments. Comments on this drawing should be directed to DLA Land and Maritime -VA, Columbus, Ohio , or telephone (614) Sources of supply. Sources of supply are listed in MIL-HDB-103 and QML The vendors listed in MIL-HDB-103 and QML have submitted a certificate of compliance (see 3.7 herein) to DLA Land and Maritime -VA and have agreed to this drawing. 22

23 BULLETIN DATE: Approved sources of supply for SMD are listed below for immediate acquisition information only and shall be added to MIL-HDB-103 and QML during the next revisio. MIL-HDB-103 and QML will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime -VA. This information bulletin is superseded by the next dated revisio of MIL-HDB-103 and QML DLA Land and Maritime maintai an online database of all current sources of supply Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ HTA HTA HTA HTC HTC HTC HUA HUA HUA HUC HUC HUC HXA HXC HYA HYA HYA HYC HYC HYC HTA HTA HTA HTC HTC HTC HUA HUA HUA HUC HUC HUC HXA HXC HYA HYA HYA HYC HYC HYC AS29F010F-150/Q WMF FEQ5 ACT-F1288N-150F6Q AS29F010F-150/Q WMF FEQ5 ACT-F1288N-150F6Q AS29F010DCG-150/Q WMF FFQ5 ACT-F1288N-150F7Q AS29F010DCG-150/Q WMF FFQ5 ACT-F1288N-150F7Q WMF DEQ5 WMF DEQ5 AS29F010CW-150/Q WMF CQ5 ACT-F1288N-150P4Q AS29F010CW-150/Q WMF CQ5 ACT-F1288N-150P4Q AS29F010F-120/Q WMF FEQ5 ACT-F1288N-120F6Q AS29F010F-120/Q WMF FEQ5 ACT-F1288N-120F6Q AS29F010DCG-120/Q WMF FFQ5 ACT-F1288N-120F7Q AS29F010DCG-120/Q WMF FFQ5 ACT-F1288N-120F7Q WMF DEQ5 WMF DEQ5 AS29F010CW-120/Q WMF CQ5 ACT-F1288N-120P4Q AS29F010CW-120/Q WMF CQ5 ACT-F1288N-120P4Q 1 of 3

24 BULLETIN Continued. DATE: Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ HTA HTA HTA HTC HTC HTC HUA HUA HUA HUC HUC HUC HXA HXC HYA HYA HYA HYC HYC HYC AS29F010F-90/Q WMF FEQ5 ACT-F1288N-090F6Q AS29F010F-90/Q WMF FEQ5 ACT-F1288N-090F6Q AS29F010DCG-90/Q WMF FFQ5 ACT-F1288N-090F7Q AS29F010DCG-90/Q WMF FFQ5 ACT-F1288N-090F7Q WMF DEQ5 WMF DEQ5 AS29F010CW-90/Q WMF CQ5 ACT-F1288N-090P4Q AS29F010CW-90/Q WMF CQ5 ACT-F1288N-090P4Q HTA HTA HTA HTC HTC HTC HUA HUA HUA HUC HUC HUC HXA HXC HYA HYA HYA HYC HYC HYC AS29F010F-70/Q WMF FEQ5 ACT-F1288N-070F6Q AS29F010F-70/Q WMF FEQ5 ACT-F1288N-070F6Q AS29F010DCG-70/Q WMF FFQ5 ACT-F1288N-070F7Q AS29F010DCG-70/Q WMF FFQ5 ACT-F1288N-070F7Q WMF DEQ5 WMF DEQ5 AS29F010CW-70/Q WMF CQ5 ACT-F1288N-070P4Q AS29F010CW-70/Q WMF CQ5 ACT-F1288N-070P4Q 2 of 3

25 BULLETIN Continued. DATE: Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ HTA HTA HTA HTC HTC HTC HUA HUA HUA HUC HUC HUC HXA HXC HYA HYA HYA HYC HYC HYC AS29F010F-60/Q WMF FEQ5 ACT-F1288N-060F6Q AS29F010F-60/Q WMF FEQ5 ACT-F1288N-060F6Q AS29F010DCG-60/Q WMF FFQ5 ACT-F1288N-060F7Q AS29F010DCG-60/Q WMF FFQ5 ACT-F1288N-060F7Q WMF DEQ5 WMF DEQ5 AS29F010CW-60/Q WMF CQ5 ACT-F1288N-060P4Q AS29F010CW-60/Q WMF CQ5 ACT-F1288N-060P4Q 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Not available from an approved source of supply. Vendor CAGE number Vendor name and address Mercury Corp. - Memory and Storage Solutio 3601 East University Drive Phoenix, AZ The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. 3 of 3