Submarine Cable Power Transmission using DC High- Voltage Three-Level Converters

Transcription

1 Submarine Cable Power Transmission using DC High- Voltage Three-Level Converters João Luís Prata Antunes Dissertation submitted to obtain the Master degree in Electrical and Computer Engineering Jury President: Supervisor: Co-Supervisor: Member: Prof. Paulo José da Costa Branco Prof. José Fernando Alves da Silva Prof. João José Esteves Santana Prof. Sónia Maria Nunes dos Santos Paulo Ferreira Pinto April 2009

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3 ii À minha mãe

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5 Acknowledgments I would like to take this opportunity to thank all people who gave me their help and encouragement during the work described in this dissertation and all previous work along my graduation. It is a great pleasure to me to acknowledge them. From start, I would like to thank my Supervisor, Prof. José Fernando Alves da Silva for the subject of study and confidence in assigning the work, his guidance, dedicated help, support, sympathy and seek for enlightening advises with quotidian examples. To all my friends, oldest to youngest, for all the laughs, fellowship and comfort when they were most needed. I thank for all the strength, support, dedication, concern and time since I know them. To my family, whom I deprived from my attention, time and affection during several times, in particular my father, my grandparents and my cousins. iv

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7 Abstract This MSc dissertation presents the behaviour of diode-clamped converters, with three, five and sevenlevels sets, operated as a three-level converter for a possible submarine cable power transmission in a high voltage direct current system. The converter works as the inverter placed in the end of the direct current link with 500 kv supplying an inductive and monophasic load. For five and seven-level converters is shown the importance of a clamping diodes network in the semiconductors voltage balancing. The active semiconductors chosen are insulated gate bipolar transistors and are forced to short-circuit separately to demonstrate the influence of such faults in the operation of the converter. The advantages of higher level topologies for these systems in short-circuit conditions are demonstrated also as some difficulties created by the high density of semiconductors. Estimated values of shortcircuit currents are calculated and a general equation for such current in n-level converters is presented. All results presented arise from simulations executed in Matlab/Simulink environment for several situations being discussed and analyzed as so for all options taken during this study. Keywords Multilevel Converters; Diode-Clamped Converters; Three-level converters; HVDC systems; shortcircuit faults; vi

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9 Resumo Esta dissertação para obtenção do grau de Mestre estuda o comportamento de conversores com díodos ligados ao ponto de neutro, com arquitecturas de três, cinco e sete níveis, controlados por três níveis para transmissão de energia por cabo submarino num sistema de alta tensão com corrente contínua. O conversor é estudado na sua situação de inversor, situado numa extremidade da ligação de corrente contínua com 500 kv alimentando uma carga monofásica e indutiva. Nas arquitecturas de cinco e sete níveis é mostrada a importância da ligação em rede dos díodos ligados ao ponto neutro para o equilíbrio das tensões nos semicondutores. A escolha dos semicondutores comandados cai nos transístores bipolares de porta isolada, que são forçados separadamente a um curto-circuito, para demonstrar a influência dessas falhas na operação do conversor. As possíveis vantagens de arquitecturas com maior número de níveis para um funcionamento em curto-circuito são expostas assim como os problemas criados pela existência de uma grande densidade de semicondutores. Valores estimados de curto-circuito e uma expressão geral para o cálculo destas correntes em conversores de n-níveis são apresentados. Todos os resultados apresentados surgem de simulações efectuadas em Matlab/Simulink para diversas condições, sendo discutidos e analisados assim como todas as opções tomados ao longo do estudo. Palavras-chave Conversores Multi-nível; Conversores com Díodos ligados ao ponto neutro; Conversores de três níveis; Sistemas HVDC; Falhas de curto-circuito viii

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11 Table of Contents List of Figures... xii List of Tables... xvi List of Acronyms... xviii List of Symbols... xx Chapter 1 Introduction Scope of the work Motivation Objectives Dissertation Outline...4 Chapter 2 Multilevel Converters Introduction The Concept of Multilevel Conversion Diode-Clamped Converter Pulse Width Modulation Strategies Chapter 3 Operation of Diode-Clamped Three-Level Converters Introduction Three-level Diode-Clamped Converter Five-level Diode-Clamped Converter Seven-Level Diode-Clamped Converter Chapter 4 Short-circuit Faults in Diode-Clamped Three-Level Converters Introduction Three-level Diode-Clamped Converter Short-circuit fault in IGBT Short-circuit fault in IGBT Short-circuit fault in IGBT Short-circuit fault in IGBT Five-Level Diode-Clamped Converter Short-circuit fault in IGBT Short-circuit fault in IGBT Short-circuit fault in IGBT Short-circuit fault in IGBT Short-circuit faults in the lower IGBTs Seven-Level Diode-Clamped Converter n-level Diode-Clamped Converter Chapter 5 Conclusions x

12 5.1 General Conclusions Future Works References Annex A Annex B B.1 Operation of Seven-Level Converter B.2 Five-Level Converter Short-Circuit faults in lower IGBTs B.3 Seven-Level Converter Short-Circuit Faults xi

13 List of Figures Figure 1.1 Different types of overhead transmission lines studied for Three Gorges Shangai (modified from [1])....2 Figure 1.2 CSC technology in an HVDC system (modified from [2])....2 Figure 1.3 VSC technology in an HVDC system (modified from [2])....3 Figure 2.1 General multilevel converters schematics (modified from [7])....6 Figure 2.2 Two-level converter with synchronized switches....8 Figure 2.3 Three-level diode-clamped converter....8 Figure 2.4 Positive directions in neutral point Figure 2.5 Generic multilevel diode-clamped converter Figure 2.6 Five-level diode-clamped converter Figure 2.7 Three-level SPWM strategy Figure 3.1 Load voltage and current in three-level converter Figure 3.2 Capacitors and load currents in three-level converter Figure 3.3 Three-level converter in state Figure 3.4 Voltage sharing in lower semiconductors in state Figure 3.5 Three-level converter in state Figure 3.6 Three-level converter in state Figure 3.7 Five-level diode-clamped converter Figure 3.8 Five-level converter in state Figure 3.9 Five-level converter in state Figure 3.10 Capacitors currents in five-level converter Figure 3.11 Voltage in diode network in five-level converter Figure 3.12 Current in diode network in five-level converter Figure 3.13 Voltage in IGBTs in five-level converter Figure 3.14 Voltage distribution in capacitors in five-level converter Figure 3.15 Evolution of voltage in capacitors in five-level converter Figure 3.16 Voltage distribution in capacitors in five-level converter with different values of resistance Figure 4.1 Capacitors and load voltages in three-level converter with short-circuit fault in IGBT Figure 4.2 Load Current in three-level converter with short-circuit fault in IGBT Figure 4.3 Discharging loop of C in three-level converter Figure 4.4 Short-circuit current peak in three-level converter with short-circuit in IGBT Figure 4.5 Currents circulation in three-level converter with short-circuit fault in IGBT Figure 4.6 Voltage and current in IGBTs in three-level converter with short-circuit fault in IGBT Figure 4.7 Voltage and current in clamping diodes in three-level converter with short-circuit fault in IGBT Figure 4.8 Currents in capacitors in three-level converter with short-circuit fault in IGBT Figure 4.9 Load and capacitors voltage in three-level converter with short-circuit in IGBT Figure 4.10 Short-circuit current peak in three-level converter with short-circuit in IGBT Figure 4.11 Discharging loop of C in three-level converter Figure 4.12 Currents circulation in three-level converter with short-circuit fault in IGBT Figure 4.13 Voltage and current in IGBTs in three-level converter with short-circuit fault in IGBT Figure 4.14 Voltage and current in clamping diodes in three-level converter with short-circuit fault in IGBT Figure Capacitors and load current in three-level converter with a short-circuit fault in IGBT Figure Currents circulation in three-level converter with short-circuit fault in IGBT Figure Voltage and current in IGBTs in three-level converter with short-circuit fault in IGBT xii

14 Figure Voltage and current in clamping diodes in three-level converter with short-circuit fault in IGBT Figure Capacitors and load current in three-level converter with a short-circuit fault in IGBT Figure Currents circulation in three-level converter with short-circuit fault in IGBT Figure Voltage and currents in IGBTs in three-level converter with short-circuit fault in IGBT4. 47 Figure Voltage and currents in diodes in three-level converter with short-circuit fault in IGBT4. 48 Figure Capacitors and load current in three-level converter with a short-circuit fault in IGBT Figure Voltage in diode network in five-level converter with short-circuit fault in IGBT Figure Current in diode network in five-level converter with short-circuit fault in IGBT Figure Voltage sharing in IGBTs in five-level converter with short-circuit fault in IGBT Figure Load and capacitors voltage in five-level converter with short-circuit fault in IGBT Figure Voltage in diode network in five-level converter with short-circuit fault in IGBT Figure Voltage sharing in IGBTs in five-level converter with short-circuit fault in IGBT Figure Discharging loop of C in five-level converter Figure Short-circuit current peak in five-level converter with short-circuit in IGBT Figure Currents in diode network in five-level converter with short-circuit fault in IGBT Figure Currents in IGBTs in five-level converter with short-circuit fault in IGBT Figure Currents in the capacitors in five-level converter with a short-circuit fault in IGBT Figure Load voltage and current in five-level converter with a short-circuit fault in IGBT Figure Voltage in diode network in five-level converter with short-circuit fault in IGBT Figure Voltage in IGBTs in five-level converter with short-circuit fault in IGBT Figure Currents in diode network in five-level converter with short-circuit fault in IGBT Figure Load and capacitors voltage evolution in five-level converter with fault in IGBT Figure Voltage in diode network with short-circuit fault in IGBT Figure Voltage sharing in IGBTs in five-level converter with short-circuit fault in IGBT Figure Discharging loop of C in five-level converter Figure Capacitors current in major discharge in five-level converter with short-circuit fault in IGBT Figure Currents in the diode network in five-level converter with short-circuit fault in IGBT Figure Currents in IGBTs in five-level converter with short-circuit fault in IGBT Figure 4.46 Currents in the capacitors in five-level converter with short-circuit fault in IGBT Figure 4.47 Load Voltage and Current in five-level converter with short-circuit fault in IGBT Figure 4.48 Load and capacitors voltage evolution in five-level converter with fault in IGBT Figure 4.49 Voltage in diode network in five-level converter with short-circuit fault in IGBT Figure A.1 PWM command signals Figure A.2 Three-level converter model Figure A.3 Subsystem IGBT with anti-parallel diode Figure A.4 Short-circuit fault and fuse Figure A.5 Five level converter model Figure A.6 Series connection of upper IGBTs Figure A.7 Column of diode network Figure A.8 Seven-level converter model Figure B.1 Voltage in diode network in seven-level converter Figure B.2 Voltage in IGBTs in seven-level converter Figure B.3 Currents in diode network in five-level converter with short-circuit fault in IGBT Figure B.4 Voltage in diode network in five-level converter with short-circuit fault in IGBT Figure B.5 Currents in IGBTs in five-level converter with short-circuit fault in IGBT Figure B.6 Voltage in diode network in five-level converter with short-circuit fault in IGBT Figure B.7 Voltage in IGBTs in five-level converter with short-circuit fault in IGBT Figure B.8 Currents in diode network in five-level converter with short-circuit fault in IGBT Figure B.9 Voltage in diode network in five-level converter with short-circuit fault in IGBT Figure B.10 Currents in IGBTs in five-level converter with short-circuit fault in IGBT xiii

15 Figure B.11 Voltage in IGBTs in five-level converter with short-circuit fault in IGBT Figure B.12 Voltage in diode network in five-level convert with short-circuit fault in IGBT Figure B.13 Voltage in IGBTs in five-level converter with short-circuit fault in IGBT Figure B.14 Load and capacitors voltage in seven-level converter with short-circuit fault in IGBT Figure B.15 Voltage in diode network in seven-level convert with short-circuit fault in IGBT Figure B.16 Voltage in IGBTs in seven-level converter with short-circuit fault in IGBT Figure B.17 Voltage in diode network in seven-level convert with short-circuit fault in IGBT Figure B.18 Voltage in IGBTs in seven-level converter with short-circuit fault in IGBT Figure B.19 Voltage in diode network in seven-level convert with short-circuit fault in IGBT Figure B.20 Voltage in IGBTs in seven-level converter with short-circuit fault in IGBT xiv

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17 List of Tables Table 2.1 Two-level converter command signals....8 Table Command signals for the three-level diode-clamped converter...9 Table 2.3 Command signals for the five-level diode-clamped converter Table Three-level command signal Table Voltage sharing in state Table Voltage sharing in state Table Voltage sharing in state Table Voltage sharing in three-level converter Table 3.6 Three-level command signal for five-level converter Table Voltage distribution in five-level converter Table Voltage distribution in five-level converter IGBTs Table Three-level command signal for seven-level converter Table 3.10 Voltage distribution in diode network in seven-level converter Table Command signals in three-level diode-clamped converter with short-circuit in IGBT Table Voltage sharing in three-level converter with short-circuit fault in IGBT Table Command signals in three-level diode-clamped converter with short-circuit in IGBT Table Voltage sharing in three-level converter with short-circuit fault in IGBT Table Command signals in three-level diode-clamped converter with short-circuit in IGBT Table Command signals in three-level diode-clamped converter with short-circuit in IGBT Table Command signals in five-level diode-clamped converter with short-circuit in IGBT Table Command signals in five-level diode-clamped converter with short-circuit in IGBT Table Command signals in five-level diode-clamped converter with short-circuit in IGBT Table Command signals in five-level diode-clamped converter with short-circuit in IGBT Table Command signals in five-level diode-clamped converter with short-circuit in IGBT Table 4.12 Command signals in five-level diode-clamped converter with short-circuit in IGBT Table Command signals with all possible short-circuits creating a discharge in seven-level converter xvi

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19 List of Acronyms AC DC HVDC CSC VSC GTO IGBT FACTS PWM NPC SPWM SVM SHEPWM FFT KCL KVL Alternate Current Direct Current High Voltage Direct Current Current Source Converter Voltage Source Converter Gate Turn-Off Thyristor Insulated Gate Bipolar Transistor Flexible Alternating Current Transmission Systems Pulse Width Modulation Neutral Point Clamped Sinusoidal Pulse Width Modulation Space Vector Modulation Selective Harmonic Elimination Pulse Width Modulation Fast Fourier Transform Kirchhoff s Current Law Kirchhoff s Voltage Law xviii

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21 List of Symbols Latin Symbols: U u u n Maximum voltage from the DC link Voltage in capacitor Voltage in a general semiconductor General number of levels du dt General derivative of voltage u S D C u i i u r r u, u u u _ i Voltage output referenced to zero Semiconductor IGBT number j Semiconductor Diode number j Capacitor number j Voltage applied to load Neutral current Current in the capacitor General voltage difference between anode and cathode in the diode Conduction resistance in semiconductors Parasitic resistance in capacitors Voltage applied to semiconductor IGBT Voltage applied to semiconductor Diode Voltage drop in the parasitic resistance of capacitor Current flowing in load Greek Symbols: γ Discrete variable concerning load voltage referenced to zero and phase k xx

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23 Chapter 1 Introduction 1.1 Scope of the work The transmission of electrical energy is mainly made using alternate current (AC) networks at high voltage levels in power systems. These networks are usually reliable and well designed, respecting safety and human/industrial needs. Also distribution grids work with AC and all the connections established between different voltage levels are adequate. Therefore these networks are a successful way to conduct electrical energy from generation to all distribution points. However power transmission could be enhanced reducing costs, losses and being more environmental friendly in some specific applications. So a new technology was developed, meeting that special requirements, based in direct current (DC) which is identified as high voltage direct current (HVDC) technology. It is mostly applied to power transmission through long distance in overhead lines, to submarine cables and to interconnect separated power systems. HVDC systems obviously interact with AC networks; hence at least two converter stations, AC to DC and DC to AC, are needed and represent an important part of these systems, together with a DC cable link. The technology late development was also due to the necessity of reliable and economic power electronic devices (since valves to semiconductors) working with high voltages and is now wide spreading facing the opportunities where it can compete with AC. One power system could be represented as all the electrical network of one country and the interconnection with other countries is useful to reinforce both systems, assuring more balance with power transmission between them. This interconnection is manageable to be made in AC but for example in South America bordering countries present 50 and 60 Hz networks not allowing a direct connection between the two systems. And even in Europe, where all countries have the same 50 Hz nominal frequency, with slightly difference lower than ±0,1 Hz between power systems, it turns also impossible to establish the connection with AC [1]. The overhead transmission lines in HVDC are competitive for long distances (approximately 600 km or more) due to a reduced cost when compared with AC transmission. A positive feature is the use of only two main conductors in DC systems differing from AC with three main conductors. The conducting losses are smaller and even land is saved as it is illustrated in Figure 1.1 with a comparison between the two 3000 MW DC transmission lines actually installed in Three Gorges at Shangai and the five 500 kv AC lines that would be needed instead [1]. On the other hand converter 1

24 stations built to HVDC systems are quite expensive, so the cost of these stations needs to be saved in the power lines and their infrastructures and that is the reason for the use of DC transmission lines only for long distances. In opposition to overhead lines for long distances exists the possibility of some underground cables, or even submarine and undersea cables which face special purposes [1]. For example islands very often are isolated from the continent having a local grid implying all generation to be produced locally. It is not easy to build power plants to constantly face load growing and it is even more difficult to build them when land is more limited, so interconnecting islands to the continents is a valid option. Using submarine or undersea cables allows a connection between island and continent. Before HVDC, the use of AC underground or undersea cables existed but was limited to small distances due to the time variant inherent characteristics of AC sinusoidal sources. Figure 1.1 Different types of overhead transmission lines studied for Three Gorges Shangai (modified from [1]). The HVDC systems are now widespread around the world with more than 92 projects transmitting more than 75 GW employing two different technologies [2]. The first one to appear is based in linecommutated current source converters (CSCs) using thyristors, shown in Figure 1.2, while the second one uses forced-commutated voltage source converters (VSCs) with gate turn-off thyristors (GTOs) or insulated gate bipolar transistors (IGBTs) represented in Figure 1.3. They are named as HVDC Classic and Light respectively, where HVDC Light as the youngest technology, offers improvements in stability, reactive power control and even has black start capability [3]. Figure 1.2 CSC technology in an HVDC system (modified from [2]). 2

25 A VSC set can be built using different multi-level converter topologies once it respects all the voltage input and output concerns which are a feature of VSCs in opposition to CSCs with concerns related with current. Figure 1.3 VSC technology in an HVDC system (modified from [2]). 1.2 Motivation The growing concern about energy quality and needs of industrial facilities encouraged the development in power electronics area which also allowed the posterior innovation in HVDC systems with the Light technology. VSC were initially used for industrial purposes with the substitution of thyristors by semiconductors with on and off control. As it brought advantages to industrial drives its application and adaptation to transmission systems was seen as feasible. The constant study and regular use of VSC, together with semiconductors development, is a demonstration of potential in the technology that can still be improved. When working with high voltages, semiconductors do not have capability by themselves to withstand those voltages, so they usually are distributed along a series connection, to divide the voltage, being controlled as a group. Multilevel converters can reduce the voltage applied to a single semiconductor as the number of levels increases due to the specific built of multilevel topologies. So assuming the interest in VSCs used in HVDC systems for submarine cables, with the requisite of power semiconductors withstanding very high voltage, the study of multilevel converters is appropriate. Within multilevel converters, which are identified with several topologies, the diode-clamped converter is chosen to represent the VSC. The use of semiconductors, despite being the major contributor for the evolution in power electronics area, is not immune to faults as it can suffer short circuits or can even fail to respond at command signals not working properly. The behaviour in such conditions and the influences in the overall working system/converter is an important study and the work should be an extra for the existing knowledge of multilevel power converters. 3

26 1.3 Objectives The main objective of this dissertation is to study the behaviour of n-level diode-clamped converters, controlled as a three-level converter, working in fault situations. The study is made in converters with an odd and lower number of levels, which trend to increase, and is intended to extend the behaviour to n-level cases. The faults created simulate a short-circuit situation where the semiconductor is forced to conduct during all the time since the occurrence of the anomaly. The work is based in computer simulation using models and tools of SimPowerSystems inherent to Matlab/Simulink program. This Toolbox offers a variety of power electronics devices and the Matlab/Simulink provides interesting potentialities in processing and post-processing simulation data results. The simulation results are verified, discussed and analyzed to assure solid conclusions in the work and managing of diode-clamped converters. 1.4 Dissertation Outline This dissertation is divided in five chapters where the first one introduces the thesis subject providing the reader the information about alternatives to common AC energy transmission systems and the importance of power electronics and multilevel converters in these different solutions to enhance their potential. Motivation, study objectives and outline are also presented in this chapter. The second chapter presents the concept of multilevel converters and the state of art in diodeclamped converters. In addition is also presented a brief topic about the converter three-level control. In the third chapter is studied the operation of the converter in all three architectures presenting voltages applied and currents through the semiconductors resultant from simulations performed assuming non ideal electrical components. The clamping diodes behaviour is analyzed and discussed writing several Kirchhoff s Voltage Laws (KVLs). The fourth chapter studies the same converter architectures behaviour with short-circuit faults created. The causes of discharge are verified, short-circuit currents are calculated and simulation results are presented and analyzed. A possible extension in the number of levels of the converter is evaluated concerning the advantages to reduce short-circuit values together with some parallel solutions In the fifth chapter are presented conclusions about this study and possible future developments are pointed out. In Annex are placed the simulation models and some redundant simulation results presenting symmetric behaviours. 4

27 Chapter 2 Multilevel Converters 2.1 Introduction The development of multilevel converters has been motivated by the increasing industry needs of higher power equipments, namely in the last three decades. In fact, these types of converters may respond adequately to the problems raised by medium voltage motor drives and utility applications that require medium or high voltage and megawatt power levels, simultaneously respecting both the energy quality and the economic patterns. The direct clamping of a single power semiconductor switch to a medium or high voltage grid can be problematic, so multilevel converters appear as an alternative in high power and higher voltage situations, being also a useful element which enables the use of renewable energy sources, quite important in current environmental issues. The development observed in the area of power electronics, namely new concepts of electronic conversion, new command and control systems and new power semiconductors allow multilevel converters to work with high voltage (kv) and high currents (ka). These converters are also currently used in high velocity traction, in equipments to improve energy quality, in flexible alternating current transmission system (FACTS), in HVDC transmission systems, and in electrical energy storage with superconductors or flywheels [4], [5], [6]. Following it will be presented the main concept of multilevel conversion, a review of diode-clamped converters and also a simple Pulse Width Modulation (PWM) control which is used. 2.2 The Concept of Multilevel Conversion Multilevel converters are based in a system with an arrangement of power semiconductors which interconnect adjacent circuits. Working as a VSC type and as an inverter, the switches interact with several lower voltage DC sources to perform the power conversion by synthesizing a staircase voltage waveform. Switches work in a commutation mode, blocking or conducting, at khz frequencies while DC sources are allowed to be capacitors, batteries or renewable energy voltage sources. The commutation of switches allows the addition of the multiple DC voltage sources reaching a high output 5

28 voltage, while semiconductors withstand only small voltages (specifically the rating of the DC source to which they are connected). Also this commutation is controlled externally according to the output desired changing conducting times for each semiconductor. An example of general circuits of multilevel converters is presented in Figure 2.1, where U represents the voltage drop between the highest and the lowest point (the maximum voltage available in DC side) and the number of levels is the number of possible inputs which are accessible to the converter. It is noticed that the number of capacitors placed in series is shorter than the number of levels in one unit and that their terminals represent the number of levels. Obviously the inner point between two adjacent capacitors only represents one output level. Figure 2.1 General multilevel converters schematics (modified from [7]). The series connected capacitors are assumed, primarily, to be any kind of voltage sources presenting the same value and the voltage at their terminals is then u = U (n 1), (2.1) where U is a nearly constant voltage which is the maximum voltage drop in the DC side; n is the number of levels in the converter; and i the number of the source. So the power semiconductors are arranged in the multilevel converter in such a way to enable each of them to withstand a voltage which is described the same manner by u = U (n 1). (2.2) Equation (2.1) also represents the magnitude difference of each level because the difference between two adjacent levels is the voltage supplied by the source. So considering U as the highest voltage point and zero (0) as the lowest, the evolution of output voltage referenced to zero is described by a discrete variable, γ, where k assumes any possible phase identification. This variable presents one of the n values in {0, 1 (n 1), 2 (n 1),, (n 2) (n 1), 1} [4]. A multilevel converter is only called as multilevel for n > 2, but starting as an example, the simplest two-level converter, which allows only two output values (0 or U ), is considered, so it can be verified a growing performance of converter increasing the number of levels. With two levels of operation the rated voltage needed in semiconductors is equal to all the voltage available in DC, (2.3). In industrial 6

29 applications using medium or high voltage, semiconductors are placed in series working as a single switch, trying to divide equally the voltage applied along them. u = U. (2.3) When the output possibilities of the two-level converter are compared against those from an n-level converter, and (2.2) against (2.3), there are some advantages of multilevel converters, namely [4]: a larger number of states can be obtained to transfer energy; output voltages present n steps (or levels) in the waveform allowing the reduction of the total harmonic distortion as n increases, avoiding, therefore, the use of filters. The increase of n allows the semiconductors to withstand lower voltages, using the same U ; The use of semiconductors with the same capacity to withstand voltage allows the feeding voltage of the n-level converter to be (n 1) times higher. As seen, a two-level converter has only two operating levels: 0 or U, and this implies a severe du dt (the sum of all du dt of every switch in the series) stress between the states, which could be a problem bearing in mind the electromagnetic compatibility. In fact, if electromagnetic compatibility is not observed, it may cause errors in the surrounding lower power circuits and insulation problems in electric machines windings. Thus, this kind of problem results in another advantage for a multilevel set because du dt is (n 1) times smaller for the same commutation times and feeding voltage. This advantage becomes crucial when respecting international standards to electromagnetic noise. However, multilevel converters present some disadvantages: more levels in the converter imply a more complex working system, as more dc sources and more power semiconductors switches are needed, each switch requiring a related gate drive circuit (command and control system). This causes the overall system to be more expensive and more complex. In addition, the increase of levels also introduces voltage imbalance problems. 2.3 Diode-Clamped Converter Among the many multilevel converter topologies devised during the last decades, there are three wellestablished ones [4], [5], [8]: the diode-clamped, the capacitor-clamped [9],[10] and the cascaded multicell with separate DC sources [11], [12]. Besides these three well-established topologies, there are also some new emerging ones: mixed-level hybrid multilevel cells, asymmetric hybrid multilevel cells and soft-switched multilevel inverters [8]. From the three major topologies referenced, the diode-clamped converter was introduced first by Nabae et al in 1981 [13]. This inverter appears as a sequence of a two-level inverter where semiconductors are placed in series to support higher voltages, as shown in Figure 2.2. This is a 7

30 n = 2 converter where U and 0 are the possible voltage outputs referenced to zero, u, if working with a synchronous command system applied to switches. Figure Two-level converter with synchronized switches. The command system for this two-level inverter is represented in Table 2.1, where S represents the semiconductor device in its current working state (S = 0 means it is open, S = 1 means it is closed). Table 2.1 Two-level converter command signals. S S S S u U To obtain a balanced voltage distribution in the semiconductors it is necessary to upgrade this twolevel converter with two additional diodes and two capacitors, as shown in Figure 2.3. This will limit the maximum voltage change applied in the semiconductors to U /2. When the output voltage is set to U, D balances the voltage sharing of S and S with S blocking the voltage across C and S across C. Figure Three-level diode-clamped converter. 8

31 For this same structure, changing the command signals in the semiconductors it is possible to achieve a third voltage output level. This change implies to stop the synchronous working plan and make S and S conduct simultaneously. So Table 2.2 is built for this purpose and it is noticed that the last combination does not correspond to a valid operating state. The middle point between the two capacitors is defined as the neutral point, and the two diodes connected to the neutral point allow the current to flow in this new working state (level). This is called the Neutral Point Clamped (NPC) converter. Table Command signals for the three-level diode-clamped converter. S S S S γ u u U U /2 U U Non defined - Among a lot of different switch combination possibilities, only a few of them have a practical interest because the load, usually inductive, cannot be interrupted or the common dc source cannot be shortcircuited. Hence, despite of the complementary pairs observed in Table 2.2, S, S and S, S, the combination S, S, S, S = 1, 0, 0, 1 is not allowed. Also to avoid some commands to act simultaneously, and to correctly balance the voltage along the semiconductors, there should only exists transitions between adjacent levels [4]. Observing the neutral point and using the Kirchhoff s Current Law (KCL) some considerations can be made. So assuming as positive the currents charging the capacitors and the neutral current entering the node, as in Figure 2.4, it is written i + i = i i = i i. (2.4) A KVL is also useful to write U u + u, (2.5) disregarding parasite resistors in capacitors and the source impedance. Using the derivative it can be extended to du dt + du 0 du du dt dt dt. (2.6) 9

32 With a simple analysis at the capacitors, it is written the current dependence from the voltage across their terminals: i = C du dt i = C du dt (2.7) (2.8) With C = C and using (2.6), (2.7) and (2.8) results i = i (2.9) Substituting (2.9) in (2.4), the neutral current becomes i = 2 i = 2 i (2.10) meaning that current flows only when the capacitors are charging or discharging, and never in a stand-by situation. Also i and i are only equal when they are zero. Figure Positive directions in neutral point. Extending the converter to n levels allows the inverter to have an n-level output phase voltage and a (2n 1)-level output voltage between two phases. If a three-phase load is connected in wye, the number of steps in the phase voltage is 2 (2n 1) 1. The extension to n levels requires the implementation of (n 1) capacitors and 2 (n 1) active switches [7]. To assure bidirectional behaviour in current and to withstand direct voltage, allowing inductive loads to work properly, each switch S is arranged together with an anti-parallel diode as shown in Figure

33 The different level ratings in the output voltage are achieved using the (n 1) capacitors to divide the voltage U in several steps given by U = j U n 1 (2.1) where j = 0, 1,, n 1. Figure Generic multilevel diode-clamped converter. 11

34 Also for this same structure presented, although the commanded switching devices require only a blocking voltage level, (2.2), the clamping diodes need different ratings for reverse voltage blocking. Notice as an example the five-level diode-clamped inverter presented in Figure 2.6 with the corresponding command signals combination in Table 2.3. Figure Five-level diode-clamped converter. 12

35 When all lower switches (S S ) are turned on, corresponding to u = 0, D must block 3U 4, D must block 2U 4 and D must block U 4. Table 2.3 Command signals for the five-level diode-clamped converter. S S S S S S S S γ u U /4 3 U /4 2 U /4 1 U To balance the reverse voltage rating between all diodes, series connections are needed but the number of the diodes rises in quadratic ratio. The number of clamping diodes, for each phase, will be (n 1) (n 2). It is also noticed that exists an unequal conduction duty between all the switches. For example the switch S only conducts in one working state, u = U, while S conducts in all the cycle except for u = 0. So the current ratings in switching devices must be different, otherwise if the inverter is designed considering the average duty for all the switches then the inner switches may be undersized and the outer switches may be oversized. When considering the worst case each phase will have 2 (n 2) outer devices oversized [5]. 2.4 Pulse Width Modulation Strategies The control of voltage output in the converters is made through the command signals distributed in the active semiconductors. There are different techniques used to enhance all the features in every converter but three PWM strategies are most common, namely: sinusoidal pulse width modulation (SPWM),[14] [15], space vector modulation (SVM) [16] and selective harmonic elimination (SHEPWM) [16]. Here is presented the easiest design, SPWM, which uses several triangle carrier signals (according to the number of output levels, n 1 carriers) and one reference signal representing the output desired. Usually is desired a sinusoidal output wave in the converter, hence the designation SPWM. So for a three-level control is presented Figure 2.7 where two triangle carriers and the reference signal are identified. The comparison between the reference and the carriers creates the solution for the output desired in the converter. When the reference is bigger than the carriers U 2 is applied to load, while on the other hand when is smaller than the carries the voltage applied is U 2. The zero level is achieved when the reference signal is placed between both carriers. The frequency ratio chosen is 13 13

36 and the carriers start their evolution already in a descendent orientation once it eliminates the even order harmonics due to the half wave symmetry created. Figure Three-level SPWM strategy. One of the major problems in diode-clamped converters is the balancing of capacitors and also PWM techniques can be helpful trying to reduce this problem. Some solutions to improve this problem are discussed in [17]. In this dissertation the study is during few periods of operation where this unbalance is not of major importance despite being clearly identified. 14

37 Chapter 3 Operation of Diode-Clamped Three- Level Converters 3.1 Introduction Many considerations for several different technologies are nowadays made possible by the use of powerful simulation tools instead of construct real prototypes. Obviously simulation results are not as accurate as experimental ones because of the non ideal characteristics of all the elements and the differences in between the same type of elements, but they are reliable. To simulate a more realistic environment non ideal features are introduced to semiconductors, namely: forward voltage, current tail time, current 10% fall time and snubbers, equal to all of them. To introduce differences between the same type of semiconductors resistances are placed in parallel with every single one of them with randomly selected values. All these resistances present the same magnitude order of MΩ. The software used is Simulink, available in Matlab. Simulink is a powerful tool used in simulation and analysis of dynamic systems of several different fields, gathering different solvers and solving methods either for linear and non-linear systems. Concerning power electronics, Simulink presents a toolbox identified as SimPowerSystems with several models of elements from electronics area. The schematics elaborated for simulation are the three-level, the five-level, and the seven-level diodeclamped converters, therefore a different number of capacitors and semiconductors are used for each scheme. For all the converters, every each one of them is controlled as working only with three levels, so a PWM control for only three levels of operation is made. This consideration is made not only because of the complexity of logical systems in higher levels but also because a major concern is related with reverse and direct voltages applied. So, as described, multilevel structures allow not only an output waveform with several output levels but also a lower voltage through all semiconductors as the number of levels increases and even a five-level control as inherent to himself the three-level operating points desired. Another reason lies in the unequal conducting duty of semiconductors using higher number of levels while on the other end with the use of three-level control it is necessary to group a number of switches as related to the operating point. The five and seven-level converters present groups of two and three semiconductors respectively and as the number of levels increase the same pattern is followed for the number of switches in the groups. These groups represent the same manner the single semiconductors in the three-level converter. 15

38 There are several semiconductors available nowadays and in continuous development every single one of them, but currently, the most commonly used for high voltage situations are the Gate Turn-Off thyristor (GTO) and the Insulated Gate Bipolar Transistor (IGBT). With wider choice options it is natural then the existence of a trade-off between power devices and the current trends indicates the switching frequency (higher in IGBT) and voltage-blocking capability (higher in GTO) as the differences. So despite the greater capability of GTOs to work with higher voltages and currents, its switching frequency is not as good as the one shown by an IGBT [17]. Since the withstanding voltages decrease with n in multilevel converters, and therefore assuming the differences of the semiconductors voltage-blocking capability as less important, the option lies in the use of IGBTs. Also the control system for a GTO is more complex, expensive and more power needs to be available. So using the Matlab/Simulink environment the converters designed present a common DC bus, which is represented by a DC source with 500 kv (U ), capacitors with μf and 0,1 Ω parasitic resistance each. The source simulates the ideal voltage immediately established after the rectification in a converter station between the positive and the negative cable in a bipolar connection. The cable is represented only by a resistance with 6 Ω which follows a DC reactor [19], usually placed to smooth the current, with 500 mh. The load is an inductive branch, RL, with R = 10 Ω and L = 100 mh to illustrate the reversibility in the converter. All converter models designed are presented in Annex A together with important and non-redundant subsystems and control signals. 3.2 Three-level Diode-Clamped Converter The three-level converter is the basic cell of diode-clamped converters and as already been initially described in 1.4. A basic schematic and a command signal table were presented, respectively in Figure 2.3 and Table 2.2. Substituting the generic U value, an updated command signal table is presented in Table 3.1, where State ID represents an identification of each working state. Table Three-level command signal. State ID S S S S u [kv] The output voltage, obviously, presents the three distinct levels supplied to load (250 kv, 0 and 250 kv) and the resultant current follows, almost, the desired sinusoidal evolution with a peak value of 6,056 ka. This value is not extremely important once load impedance can be higher reducing it or if the semiconductors are not able to conduct such magnitude several can be displaced in parallel to divide it. In Figure 3.1 is presented precisely the voltage and current in the load during 0,1 s. The voltage evolution respects the PWM control designed with a working frequency of 50 Hz (T = 0,02 s), 16

39 where the firsts 0,01 s correspond to a positive half cycle and the following 0,01 s to a negative half cycle. Figure Load voltage and current in three-level converter. Despite what is described in (2.9) the current in the capacitors is not symmetric. That is only achieved assuring equal capacitors, with equal parasite resistors, as specified for the simulations, and with no impedance in the common DC bus. Since the converter can be part of a HVDC system, such impedance exists and is supposed to represent the DC cable supplying a nearly constant current. So the current contribution of each capacitor to the load is represented in Figure 3.2. Figure Capacitors and load currents in three-level converter. 17

40 The higher peaks in capacitors currents correspond to a positive or negative state, while the intervals between happen for the zero voltage state. In state 1 and state 3, the load current, either positive or negative, is related with currents i and i, respectively. In state 2 is noticed a positive current always circulating in the capacitors, capacitors are charging, which is equal in both and is totally supplied by the source through the cable. In the first state, the converter uses the upper semiconductors, connecting the first terminal of the load to the highest voltage level (U ) while the other terminal is always connected to the neutral point. As the neutral point corresponds to the middle point between the two capacitors, its voltage is, ideally, U 2. So the load voltage in this state is described as the difference between the highest voltage level and the neutral point. This description also represents the voltage across C, which means they are in parallel and the voltage existing in the capacitor is the same in the load. This state is represented in Figure 3.3 with the most important currents flowing in the circuit. The load current influences the direction of the currents in the converter, and affects the charging and discharging dynamics of capacitor C. When positive, C discharges and obviously C charges for a negative load current. The anti-parallel diodes in the semiconductors are essential here, allowing the negative current to flow adequately. It is noticed that load current corresponds to neutral current and in capacitor C flows the same current supplied by the common dc bus. Figure Three-level converter in state 1. The voltage distribution along all the semiconductors is different according to state ID, but all respecting some limits inherent to multilevel converters theory. So for state 1, the voltage sharing is presented in Table 3.2, where in S positions is represented the voltage across IGBT j, and the respective diode in anti-parallel withstands a symmetric voltage. The assumption is made to simplify the table and to respect the usual u orientation in diodes. 18

41 As S and S are conducting, is ideally considered that no voltage is applied across the semiconductors terminals, but despite the consideration being acceptable, the real voltage those semiconductors withstand is dependent of their internal conducting impedance and load current. u, = r, i (3.1) When S is turned ON, diode D is considered as arranged in anti-parallel with C and within that situation no current flows through D. To verify, KVL is written. u r i + r i u = 0 (3.2) Assuming r i and r i as the smaller terms, the reverse voltage in diode is approximately u u. (3.3) Table Voltage sharing in state 1. S S S S D D u 0 u 0 u 250 kv u 250 kv u 250 kv u 0 The series of the lower semiconductor is exposed to all the voltage available, 500 kv, which is divided along S and S. With the connection of the clamping diodes such division should be balanced. Looking to Figure 3.4, which represents the working conditions of state 1, is possible to describe the voltage sharing along the lower semiconductors bearing in mind some voltage loops. Figure Voltage sharing in lower semiconductors in state 1. 19

42 In this state the voltage in C is applied to load so two loop can be written: u u + u u U 2 + u (3.4) u + u = U (3.5) So if u < U 2 u < 0 (3.6) the diode is off and the voltage across both IGBTs should be approximately equal u u U 2 (3.7) if the leakage currents, also in both transistors, are approximately equal. On the other hand if u > U 2 u > 0 u < U 2 (3.8) the diode conducts the leakage currents until u U 2 u U 2. (3.9) The second state, which corresponds to zero voltage applied to load, uses the clamping diodes to assure the current circulation in the converter due to the load inductive nature. The diodes do not conduct simultaneously; it depends on the load current orientation. For positive load current it is D that works, while for negative current the circulation is assured by D. With this arrangement of semiconductors the middle point is connected directly to the other load terminal, no voltage being supplied by any source. The voltage really applied to load is due to conduction, considered, ideally, zero. 20

43 In Table 3.3 is presented the voltage distribution where fewer semiconductors withstand larger voltages. In this state only two switches present great voltage at their terminals, while on state 1 high voltages are present in three. Figure 3.5 Three-level converter in state 2. Table Voltage sharing in state 2. S S S S D D u 250 kv u 0 u 0 u 250 kv u 0 u 0 The two clamping diodes and the inner IGBTs naturally present only a small voltage drop which is dependent on their internal conducting impedance and the load current. Despite the loops not being simultaneous, when D and S are conducting, S and D see a voltage due to that conduction and they will present a voltage drop along them also as the load. On the other hand to S and S is applied a direct voltage of approximate 250 kv each, corresponding C to S and C to S due to the connection established by D and D, where middle point voltage is seen in the other load terminal. The capacitors, now, present the same current, totally supplied through the cable, charging them. Finally the third state, where 250 kv are supplied to load, semiconductors S 3, S 4 are ON and S 1, S 2 are turned OFF. This state is similar to the first one where the highest voltage point were connected directly to load, but instead, now, the load is directly connected the lowest voltage point, 0 (zero). Once again the load voltage is the difference between zero and the middle point which allows achieving the negative output value. Now is the voltage in C 2 that is seen by the load. The currents arrangement is represented in Figure 3.6 for the separated situations with positive and negative load current and also influences the capacitors charge and discharge. 21

44 As this state is symmetrical from state 1, the voltage across semiconductors is precisely the opposite, now the upper switches and D withstand the high voltages. The diode becomes arranged in antiparallel with C and no current passes through it. Figure Three-level converter in state 3. Table Voltage sharing in state 3. S S S S D D u 250 kv u 250 kv u 0 u 0 u 0 u 250 kv To abridge the voltage distribution along all semiconductors in all the three different states, is presented Table 3.5 where is indicated the relation with each capacitor. Table Voltage sharing in three-level converter. ID S S S S D D u u u 0 2 u 0 0 u u u u 3.3 Five-level Diode-Clamped Converter The five-level converter appears as the following converter with a smaller and odd number of levels. The number of semiconductors increases now to eight IGBTs with eight anti-parallel diodes and twelve clamping diodes. The clamping diodes are connected as a network [19] as a completion to their series connection limiting and balancing the voltages of the different clamping diodes. Such is due to the different maximum reverse voltages each diode really withstands according to its tolerance rate. 22

45 Also four capacitors are needed instead of only two and the 500 kv supplied by the DC source are divided in 125 kv for each capacitor. So the five-level converter is presented in Figure 3.7 with a diode network with the respective command signals applied to active semiconductors described in Table 3.6. Figure Five-level diode-clamped converter. Three alignments of diodes can be identified which are specifically numbered to an easier interpretation when needed. Table 3.6 Three-level command signal for five-level converter. State ID S S S S S S S S u [kv] The voltage output is the same as the three-level converter due to the same control and grouping of semiconductors but now the voltage from DC bus is equally distributed between four capacitors which are connected to load as described 23

46 u 250 kv u + u (3.10) u 250 kv u u (3.11) Load current is consequently also the same. The connections established in the three different states can be described the same manner as for the three-level converter. In state 1 semiconductors S S connect one load terminal to the highest voltage level while the other terminal is connected to the neutral point which is now placed between C and C. The same way, state 3 connects the load, through the bottom semiconductors, to the lowest voltage level and state 2 uses the clamping diodes to assure current circulation when no voltage is applied to load. Such circulation is made using the second column of diodes, D and D for positive load current and D and D for a negative one. This column mirrors the clamping diodes in the three-level converter because they are the ones clamping the neutral point. A converter with this formulation, five-level topology working as a threelevel converter, only uses the second column of clamping diodes to conduct current while the rest of such network is only useful to improve the voltage distribution in all semiconductors. The current circulation in states 1 and 3 is also similar to the previous converter and is presented in Figure 3.8 and Figure 3.9 respectively, where the only significant characteristic is, ideally, the equal behaviour noticed for the capacitors in pairs demonstrated by the result simulation in Figure Figure 3.8 Five-level converter in state 1. 24

47 A first approach to state 1 demonstrates that D shares the voltage with C ; D and D share with C and C ; and D, D and D share with C, C and C. On the other way around the same can be stated for state 3 where D is in parallel with C ; D and D with C and C ; and D, D and D with C, C and C. Figure 3.9 Five-level converter in state 3. Figure 3.10 Capacitors currents in five-level converter. 25

48 Some other inner loops can be written helping to prove voltage distribution created in the diode network, specifically u u _ u u = 0 (3.12) u u _ u u = 0 (3.13) and u + u + u + u + u + u + u + u = 0 (3.14) u + u + u + u + u + u + u + u = 0 (3.15) u + u + u + u + u + u + u + u = 0 (3.16) The same manner that in the three-level converter when state 1 is activated the second diode is considered to withstand a zero voltage, in the five-level converter diodes D, D, D, D, D and D also can be considered as withstanding zero voltage in state 1. Symmetrically in state 3 the diodes D, D, D, D, D and D are the ones in those conditions. This assumption is not entirely truth and easy to satisfy because as the number of capacitors is higher its balancing becomes also more complicated, as so for the number of semiconductors which are all interconnected establishing even more loops that can be analyzed. Also this problem with capacitors and the difficulty to control their voltage keeping it the most approximate as possible is noticed for the maximum voltage in all semiconductors obviously. So the maximum voltage along each diode on the three states is presented in Table 3.7, complemented by the period of simulation results in Figure 3.11 where each column with results represents a column of diodes. Table Voltage distribution in five-level converter. State ID i D D D D D D D D D kv 128 kv 128 kv 0 kv 0 kv 0 kv 0 kv 0 kv 0 kv 2 0 kv 122 kv 122 kv 122 kv 0 kv 0 kv 121 kv 0 kv 0 kv 3 0 kv 0 kv 125 kv 0 kv 0 kv 125 kv 125 kv 126 kv 0 kv 4 0 kv 0 kv 0 kv 0 kv 0 kv 0 kv 128 kv 128 kv 127 kv With the use of this diode network is seen a better balanced voltage distribution along the clamping diodes which could not be possible using only the series connection. Some perturbations are noticed due to great complexity in the system with switching behaviour, parasitic capacitances in semiconductors and different equivalent resistances placed, but the maximum reverse voltage each diode withstands rounds 125 kv as desired. 26

49 Figure Voltage in diode network in five-level converter. In state 2, the zero voltage state, the inductive load needs a loop where current can circulate freely. As said, the second column of diodes manages such concern with no other column involved in current circulation either for this or any other of the states. To attest that statement is presented, in Figure 3.12, for the same period of time as before, the currents circulating in those diodes. Figure Current in diode network in five-level converter. Is easily noticed the great magnitude difference between second and other columns where only small perturbations exist which never have a reasonable influence in the currents circulating so they can be ignored. 27

50 Also for the active semiconductors, is presented Table 3.8 with the voltage along them in all three states. A simulation result for voltage across IGBTs is presented in Figure Not to forget is the existence of anti-parallel diodes which are considered to have a symmetric voltage from the one in IGBTs. Table Voltage distribution in five-level converter IGBTs. State ID S S S S S S S S 1 0 kv 0 kv 0 kv 0 kv 126 kv 120 kv 125 kv 125 kv kv 125 kv 0 kv 0 kv 0 kv 0 kv 125 kv 125 kv kv 125 kv 115 kv 135 kv 0 kv 0 kv 0 kv 0 kv The major difference in all the voltages withstand by the semiconductors are the ones applied in S and S when on state 3. It also can be seen that their voltages are complemented by each other, during their evolution, where when the voltage in S decreases, it increases in S. Figure 3.13 Voltage in IGBTs in five-level converter. The IGBTs in the left correspond to the sequence S S, upper IGBTs, while the right side represents S S. In this converter is complicated to establish a direct connection between the direct voltages applied to semiconductors and the respective capacitors as it was presented in the previous one. Theoretically and ideally was expected, for each state, that the IGBTs turned OFF were related with the capacitors by the order they are arranged in the converter. For example in state 2, S, S, S and S were supposed to represent the voltage in C, C, C and C respectively. Also for the diode network the diodes are related with the capacitors directly through its number, D is related with C where x is the number of the column in the network. A voltage distribution in the capacitors for the same period of time always used is presented in Figure

51 Figure Voltage distribution in capacitors in five-level converter. In this case the second capacitor presents the smaller voltage but it is important to state that the mean voltage in all capacitors suffer a constant change along the simulation, specifically the voltage in C and C as seen in Figure 3.15 for this case. This is the already known problem with the voltage unbalance in diode-clamped converters which is also a consequence of the different parallel resistances placed. If other random values of resistance are selected a better result can be achieved during more time as seen in Figure 3.16 but the continuous evolution trends to the same behaviour as before. Figure Evolution of voltage in capacitors in five-level converter. 29

52 Figure Voltage distribution in capacitors in five-level converter with different values of resistance. 3.4 Seven-Level Diode-Clamped Converter The seven-level converter is the following in the chain of converters with an odd and lower number of levels. The number of active semiconductors increases to twelve IGBTs with twelve anti-parallel diodes and thirty clamping diodes which represents a high density rate of semiconductors in one converter. The clamping diodes are obviously also arranged in a network, distributed in five columns with six diodes each, to improve voltage balance among them. The converter also presents six capacitors ideally charged with approximately 83,3 kv each to perform the 500 kv from the DC bus. All this creates more inner loops which follow the same pattern as for five-level converter. The command signals are presented in Table 3.9 where is noticed the groups of three semiconductors needed to work as a three-level converter. Table Three-level command signal for seven-level converter. State ID S S S S S S S S S S S S u [kv] The current distribution is the same as for the other converters, where the upper IGBTs conduct for state 1 and the lower IGBTs for state 3, taking into account also the anti-parallel diodes. State 2 uses the network diode and the similitude between the seven-level and the five-level converter is great in the diode network once the number of columns is also odd. This way the only diodes who conduct are 30

53 the ones in the third column which clamp the middle point where load is connected. All the rest of diodes only conduct some leakage current and their main purpose is to balance voltage in the converter which is more complicated than in the five-level converter due to a higher density of semiconductors. Ideally they withstand only the maximum reverse voltage, which is 83,3 kv, or zero so Table 3.10 describes the ideal voltage sharing where M represents the maximum reverse voltage applied. Table 3.10 Voltage distribution in diode network in seven-level converter. ID i D D D D D D D D D D D D D D D 1 M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M The behaviour is identical as the one seen for the five-level converter only with more columns. If the columns 1 and 5 are removed, as also diodes 1 and 6 from each column, the same result as in the five-level converter appears. With this voltages in the clamping diodes, is expected the same ideal behaviour in IGBTs with a maximum direct voltage applied of 83,3 kv. All voltages and currents are presented in Annex B once the results are ideally very similar. In simulation results is proven the voltage balancing problems with a voltage trade-off between the diodes much more evident than for the five-level case. The elevated number of switching devices complicates this task but in any case the use of the diodes network creates some boundaries to maximum voltages applied, once no semiconductor withstands more than 100 kv in the worst cases which are few. Without the network arrangement the voltage differences between semiconductors is worse and can round more than 100 kv in adjacent diodes. The problem with the unbalance of capacitors also still persists for this architecture even if not pronounced so actively as for the five-level case where C and C rapidly trade their voltages. The parallel resistances values also influence this unbalance. 31

54 32

55 Chapter 4 Short-Circuit Faults in Diode-Clamped Three-Level Converters 4.1 Introduction The option taken for fault situations is to create a fault separately in each IGBT and simply one fault per study, i.e. only one IGBT is short-circuited for simulation. As the number of levels pretended is three, this means that for every single fault the analysis must observe the behaviour of the converter in the three working levels. 4.2 Three-level Diode-Clamped Converter Short-circuit fault in IGBT 1 In the faults, the first simulation is made for a short-circuit in the first semiconductor, S, and this can be represented as a permanent S = 1 in the table of command signals. So from the moment shortcircuit happens, the new signals are presented in Table 4.1, where State ID is, again, the identification for each working state. Table Command signals in three-level diode-clamped converter with short-circuit in IGBT1. State ID S S S S This way the converter presents one operating point using the same semiconductors, another operating point placing three IGBTs in series and a last operating point where the IGBT short-circuited is alone. In these working conditions is rapidly seen the capacitor C discharging and necessarily C assuming entirely the voltage difference achieving a new steady state. So, the voltage mean value in C is in a much smaller magnitude order than before, u 0, and the voltage mean value in C is all the voltage in the common dc bus, u 500 kv, approximately as seen in Figure 4.1. It is not totally 33

56 exact due to the cable impedance which now is travelled by a larger steady state current and even C is never absolutely zero. During the evolution until the new steady state, the discharge happens more suddenly than the charge in the complementary capacitor due to the behaviour of the current through DC cable. Considering the load voltage compound by two different levels, 0 and 500 kv, this implies a negative mean value applied, therefore a negative dc component is also found in the load current as shown in Figure 4.2. Figure 4.1 Capacitors and load voltages in three-level converter with short-circuit fault in IGBT1. Figure Load Current in three-level converter with short-circuit fault in IGBT1. 34

57 Besides the dc component, load current also presents a significant distortion in its evolution. Running the Fast Fourier Transform (FFT) Analysis provided in Powergui interface for SimPowerSystems models, it can be noticed the existence of a second harmonic rounding 20% relative to fundamental (50 H ). The precise instant when short-circuit occurs in Figure 4.1, represents a negative working level ( U 2) but the discharge of C only happens when the transition to zero state is done. So state 2, now presenting the series of three IGBTs conducting, natural S, S and short-circuited S, is responsible for the discharge. Another possible instant for the occurrence of the discharge, is in state 1 but since no differences from a regular situation are created in the predisposition of the semiconductors, it is assumed state 2 and the series of three IGBTs as the cause of discharge in capacitor C. So in state 2 a new loop is created, with smaller impedance than usual being seen by the capacitor and that is the cause of discharge. Using KVL it is written the equation of such loop u u _ + u + u + u + u = 0. (4.1) To calculate such current, at least its highest peak which is an important reference, the superposition theorem could be used assuming the capacitors work as dc voltage sources. But since the cable impedance is much bigger than the other ones where currents circulate and also semiconductor S is OFF offering a big impedance not allowing a closed circulation to C, the loop in (4.1) is enough to calculate the short-circuit current. The conducting impedance in the semiconductors is assumed to be only a resistor and equal for all of them, r = 0,1 Ω, the same of the capacitor parasite resistance. The reactor placed in series with the cable (500 mh) is useful to limit great current changes in the cable and in this situation short-circuit current that flows through semiconductors is practically supplied by the discharging capacitor. So assuming in the exact instant immediately before the short-circuit a voltage of 250 kv across C, and re-writing (4.1) with all resistances and dependence on current appears I = r = 500 ka. (4.2) It is then expected a current peak of 500 ka flowing in semiconductors S, S, S and D in the first transition to state 2. Such current peak obviously causes the destruction of the switches and also the sudden decrease in the voltage observed in the capacitor. In Figure 4.4 is presented the simulation result describing the evolution of capacitors current in the first instants. It is possible to see the first peak current from capacitor C rounding 500 ka as expected while C maintains a more regular behaviour. 35

58 A load current positive in malfunction is almost only observed in a small portion of time and while C is still naturally discharging until a new steady state is achieved. Anyway, the discharge with its high current peak is not felt directly by load due to its inductive nature. Figure 4.3 Discharging loop of C 1 in three-level converter. Figure 4.4 Short-circuit current peak in three-level converter with short-circuit in IGBT1. It was already stated that a major discharge occurs in the first passage in state 2, but afterwards a new steady state is achieved. Each state is analyzed, showing the currents flowing and voltages 36

59 withstand by each semiconductor in the precise instant. So with IGBT 1 short-circuited, u = 0, the first diode, D, is always directly exposed to C and withstands its voltage, if parasite resistance is disregarded, u u. Despite the capacitor discharges, it never presents a negative voltage, not even presents zero voltage through its terminals, so this diode is no longer available for conducting. The voltage sharing for all the other semiconductors, in all three working states, is presented in Table 4.2 together with evolution in capacitors. The evolution marked is a cause of a negative load current in steady state. Table Voltage sharing in three-level converter with short-circuit fault in IGBT1. ID u 0 u U S S S D u 1 0 u u 0 u u 0 u 3 u 0 0 u u To be more accurate, the values related with C, such as the voltages applied to D, S and even u, can vary according to its current since the voltage magnitude order is now much different from normal operation and current levels are higher. So the parasite resistance and the conducting resistance with current orientation are important to obtain a more accurate result. In Figure 4.5 is presented the most important currents flowing in the converter in each one of the three different states after the steady state is achieved where load current is always negative. No differences exist primarily from the functional three-level converter for states 1 and 3 in the currents distribution for a negative load current. Obviously current values are different and the voltages applied to semiconductors are not balanced anymore due to the voltage difference in the capacitors. Figure Currents circulation in three-level converter with short-circuit fault in IGBT1. To confirm current circulations and voltages applied, the results of simulation for all semiconductors during a single period are presented in Figure 4.6 and Figure 4.7 as well as the currents in capacitors and load current in Figure

60 Figure Voltage and current in IGBTs in three-level converter with short-circuit fault in IGBT1. Since load current is negative, the upper IGBTs when in state 1 do not present current through themselves because such conduction is assured by the anti-parallel diodes. For state 2 conduction exists in semiconductors S, S and S. In this state the current in S and S is the sum of the discharging current in C and the current supplied by the DC bus while in S is also summed load current. In state 3 is visible the conduction of load current in semiconductors S and S. Figure Voltage and current in clamping diodes in three-level converter with short-circuit fault in IGBT1. In the clamping diodes analysis only D conducts current as expected and always in state 2. Such current is equal to the one circulating in S in the same state. All high voltages applied to the semiconductors are related with the voltage available in capacitors. 38

61 Figure Currents in capacitors in three-level converter with short-circuit fault in IGBT1. Observing the evolution of the currents in Figure 4.8 is easily identified the charging of C in state 1 due to load current and DC bus, its discharge in state 2, and again charging in state 3 only due to the DC bus Short-circuit fault in IGBT 2 After verifying the behaviour in the converter with the first semiconductor, S, short-circuited, now is presented the results for a fault in S. The same way as before the command signal representing short-circuit is made with S = 1 permanently and all the command signals are presented in Table 4.3. Table Command signals in three-level diode-clamped converter with short-circuit in IGBT2. State ID S S S S This time states 1 and 2 present no changes because S is a semiconductor with a larger conduction duty. The only difference exists in the transition to state 3 introducing once again a series connection of three IGBTs. In this working conditions the discharge of C happens, with a respective voltage compensation by the other capacitor. So the voltage mean value in C is reduced to nearly zero, u 0 and C assumes the voltage in the DC bus, u 500 kv. In Figure 4.9 is presented the voltage applied to load and the one available in the capacitors being noticed the referred discharge. 39

62 Figure Load and capacitors voltage in three-level converter with short-circuit in IGBT2. In this case is clear the existence of a positive voltage mean value applied to load and consequently a positive dc component will be observed in current. The cause of discharge can be considered as symmetric from the one motivated by the fault in S because also C sees now a much lower impedance characterized by the loop u u _ + u + u + u + u = 0. (4.3) Assuming once again that the contribution from the DC bus to the short-circuit current is negligible, being fed only by the capacitor presenting a voltage of 250 kv, is calculated the highest peak in the current which has the same value as in (4.2), 500 ka. It happens because the number of semiconductors travelled by the current is the same and they all have the same conducting resistance. A simulation result with the behaviour of the currents in the capacitors in the time interval corresponding to the highest current peak is presented in Figure 4.10 while the discharge loop is represented in Figure Since the discharge loop only happens in state 3, which has a smaller frequency of use, the discharging of C in this situation takes more time and for such reason, in Figure 4.10 exists a gap of time where the converter operates regularly. It corresponds to the positive half cycle in the PWM control. With short-circuit in S none of the clamping diodes withstands a direct voltage from any capacitor, therefore both are able to conduct if needed. So as only S presents a previously defined voltage applied, Table 4.4 is presented with the voltage distribution in all the other semiconductors. 40

63 Figure Short-circuit current peak in three-level converter with short-circuit in IGBT2. Figure 4.11 Discharging loop of C 2 in three-level converter. What was written about the values related with C in the other case are now again important for these values related with C. 41

64 Table Voltage sharing in three-level converter with short-circuit fault in IGBT 2. ID u U u 0 S S S D D u 1 0 u u u 0 u 2 u 0 u u u u In Figure 4.12 is presented the currents circulation in the converter separated for the three states when on steady state. In this working conditions is represented the load current as always positive. The first two states present a regular circulation for a positive current which is demonstrated by the result simulations in Figure 4.13 and Figure Figure Currents circulation in three-level converter with short-circuit fault in IGBT2. Figure 4.13 Voltage and current in IGBTs in three-level converter with short-circuit fault in IGBT2. The first IGBT only works on state 1 conducting the positive load current simultaneously with S. In the second state, since load current has an always positive evolution, S continues to conduct but now 42

65 together with D. When the converter operates in state 3, the short-circuit loop is active where S, S, S and D conduct. The current circulates through S and D during the entire negative half cycle of PWM, being bigger than in S and S, specifically in state 3. This difference is related with the conduction also of load current. Figure 4.14 Voltage and current in clamping diodes in three-level converter with short-circuit fault in IGBT2. The second diode conducts some leakage current, in state 1, because u > u u > 0. (4.4) This way the diode conducts until the voltage in the capacitor equals the voltage through the semiconductor. The load current and the currents charging and discharging the capacitors are presented in Figure The charging of both capacitors is only made through the DC bus during state 2 and state 3 for C and during state 2 and state 1 for C. Figure Capacitors and load current in three-level converter with a short-circuit fault in IGBT2. 43

66 4.2.3 Short-circuit fault in IGBT 3 This third semiconductor is part of the branded lower IGBTs of the converter and a short-circuit fault created on it results in the same series connection of three IGBTs as for the fault in S, as demonstrated in Table 4.5, but now happening when the converter is in state 1 instead of state 2. Table Command signals in three-level diode-clamped converter with short-circuit in IGBT3. State ID S S S S On state 1 the series set of the three IGBTs origins the same type of short-circuit through the loop described in (4.1) discharging C, charging C and creating a negative load mean voltage. Also shortcircuit highest peak is equal to both cases before. However two differences from the fault in S can be stated: no clamping diode is directly connected to a capacitor being unable to conduct as D was; and the great loop is associated with a minor conducting duty state. The converter operates the regular way when on state 2 and 3 once again due to a larger conduction duty. These features are related to the inner diodes because a short-circuit fault in IGBT 2 creates the same conditions. So the results obtained for short-circuit in IGBT 3 are symmetric from those caused by a fault in IGBT 2. In Figure 4.19 is presented the currents circulation in the converter in all the three states with a short-circuit fault in IGBT 3. The symmetry with the fault in IGBT 2 is obvious and the simulation results presented in Figure 4.17, Figure 4.18 and Figure 4.19 prove such fact. Figure Currents circulation in three-level converter with short-circuit fault in IGBT3. 44

67 Figure Voltage and current in IGBTs in three-level converter with short-circuit fault in IGBT3. Figure Voltage and current in clamping diodes in three-level converter with short-circuit fault in IGBT3. 45

68 Figure Capacitors and load current in three-level converter with a short-circuit fault in IGBT Short-circuit fault in IGBT 4 With the symmetry in the converter it is expected that this fault origins the same work conditions seen with S short-circuited. The same way a fault in IGBT 1 connects D directly to C disabling its conduction, a fault in IGBT 4 connects D to C, and the series connection of three IGBTs happens again in state 2. The command signals described in Table 4.6 represent the behaviour of active semiconductors with a fault in S. Table Command signals in three-level diode-clamped converter with short-circuit in IGBT4. State ID S S S S Regarding the symmetry, the currents behaviour in the converter are presented in Figure 4.20 where load current achieves an always negative value. 46

69 Figure Currents circulation in three-level converter with short-circuit fault in IGBT4. The result simulations are presented in Figure 4.21, Figure 4.22 and Figure 4.23 which when compared against those resultant from the short-circuit fault in IGBT 1 is visible the symmetry. Figure Voltage and currents in IGBTs in three-level converter with short-circuit fault in IGBT4. 47

70 Figure Voltage and currents in clamping diodes in three-level converter with short-circuit fault in IGBT4. Figure Capacitors and load current in three-level converter with a short-circuit fault in IGBT Five-Level Diode-Clamped Converter The five-level converter is expected to have its short-circuit fault behaviours different than the threelevel converter due to the higher number of semiconductors and capacitors. Despite the groups of semiconductors arranged with the command signals, the switches are short-circuited independently to study such influence in the converter. If the entire group is forced to malfunction instead of a single 48

71 semiconductor, probably representing a problem in the primary command signal, the results obtained are similar to a three-level converter where the group in the five-level converter represents a single semiconductor in the three-level one. In this converter, the usual number of active semiconductors turned ON is four Short-circuit fault in IGBT 1 Maintaining the same identification as before, using S = 1 to represent a permanent short-circuit in semiconductor j, a fault in IGBT 1 in a five-level converter influences the command signals in the manner represented in Table 4.7. Table Command signals in five-level diode-clamped converter with short-circuit in IGBT1. State ID S S S S S S S S Making a parallel between this fault and in first semiconductor in the three-level converter is noticed the non existence of a special series arrangement of semiconductors, five in this case, here. State 1 remains unchanged, conducting current along the upper IGBTs or the respective anti-parallel diodes according to the load current value. In the following states the only difference they provoke is the immediate arrangement of D in parallel with C disabling its conduction. Since this diode is not used for any significant conduction in the regular operation, only some leakage current flows, no major problem assaults the current circulation in the converter changing its behaviour. All the rest of the diodes in the network withstand the usual voltages ( 125 kv) and no discharge of any capacitor happens. But despite no differences in the currents being observed, short-circuit of S, which represents a difference for states 2 and 3, implies a voltage trade-off with other semiconductor, necessarily IGBT, to respect some KVLs. With this short-circuit the upper terminal of semiconductor S is connected to the highest voltage point in the converter while its lower terminal is still clamped by the second column of diodes. So it is expected that this semiconductor withstands the extra voltage in the semiconductors resultant from short-circuit. Re-writing (3.14) for each state, concerning the IGBTs turned on, appears in the correct sequence u + u + u + u + u = 0 (4.5) u + u + u + u + u = 0 (4.6) u + u + u + u + u + u + u = 0 (4.7) and substituting the ideal zero voltages in the respective diodes for each state results u + u = 0 (4.8) u + u + u = 0 (4.9) 49

72 u + u + u + u + u + u + u = 0 (4.10) Since the voltage in the rest of the diode network is not affected in any state, only D in states 2 and 3, (4.8) is equal for a normal operation and S withstands the symmetric voltage of D which corresponds to the voltage in C. For (4.9), the loop for state 2, where S is OFF, is noticed that the active semiconductor needs to withstand the same voltage as D and D which ideally corresponds to 250 kv existing between C and C. In this equation u is the odd factor who forces S to withstand a bigger voltage. The third state equation, (4.10), presents a bigger group of semiconductors to share the voltage but since the upper terminal of S is clamped through column 3, its voltage ideally reflects C, as S clamped between the second and the third column reflects C and necessarily S needs to reflect C and C with a total of 250 kv. Once again is the voltage across D who perturbs the loop. Simulation results for all semiconductors are presented in Figure 4.24, Figure 4.25 and Figure 4.26, respectively for the voltage in the diode network, their current and voltage across IGBTs. Figure Voltage in diode network in five-level converter with short-circuit fault in IGBT1. The first diode in the network, D, withstands along all period the voltage existing in C as expected, which is the only difference among the diodes when compared against the regular operation. Also for their currents, the second column is still the only to conduct load current while the other diodes only conduct leakage current. 50

73 Figure Current in diode network in five-level converter with short-circuit fault in IGBT1. The voltage across IGBTs demonstrates S withstanding the surplus voltage created in these semiconductors by short-circuit. Also, obviously S presents no voltage across its terminals and all the rest of IGBTs withstand the usual voltage, due to no discharge, for the usual states of operation. Figure Voltage sharing in IGBTs in five-level converter with short-circuit fault in IGBT1. 51

74 4.3.2 Short-circuit fault in IGBT 2 A short-circuit fault in the second active switch presents immediately a difference from first one because it creates a series connection of five IGBTs in state 2, the largest conduction duty, as demonstrated by Table 4.8. It was previously noticed that such arrangement of semiconductors is the cause of short-circuit current flowing in the converter and the same happens for this case. Table Command signals in five-level diode-clamped converter with short-circuit in IGBT2. State ID S S S S S S S S A simulation result in discharge with load voltage and the voltage in the capacitors is presented in Figure 4.27 where is noticed the discharge of C while the rest of them starts to assume the voltage difference. Instead of only two output levels as seen for the three-level converter (0 and ±500 kv according to which capacitor discharges), in this case three output levels exist. They exist due to the number of capacitors in this topology, C and C are used for the positive level while C and C are responsible for the negative one. Since only C is affected by a sudden discharge, in state 1 there still exists the contribution of C. State 2 with the series arrangement of the IGBTs connects the load directly to C, initially presents a non-zero value but when discharged is ideally zero, and state 3 presents the usual connection to load terminals throughout C and C. Figure Load and capacitors voltage in five-level converter with short-circuit fault in IGBT2. 52

75 It is also observed the evolution in the other capacitors initially raising their voltage but after a while they start to trend to specific values. Ideally the first capacitor evolves to 250 kv, corresponding to its usual voltage added with the usual voltage in C, and both C and C ideally trend to the usual 125 kv. This way the load suffers initially a perturbation in its behaviour and as the voltage in the capacitors evolves it regains the regular behaviour. Using a longer simulation time and after a common trend, becomes visible the slowly evolution towards the unbalance of voltages in capacitors C and C. The same phenomenon was already observed for the regular behaviour of five-level converters. The simulation results for the voltage applied to semiconductors are presented in Figure 4.28 and Figure 4.29 respectively for diode network and IGBTs. The period of simulation presented corresponds to a period where the voltage in the capacitors is still evolving towards the initial trend but anyway it is understood the influence of capacitor C in the diodes D and C in D as ideally desired in the topology set. As the rest of capacitors present a very similar result is not identifiable their influence in the respective diodes directly. Figure Voltage in diode network in five-level converter with short-circuit fault in IGBT2. The same described for the diode network is valid to IGBTs where S and S see the voltage in C and S sees the voltage in C. As S is the short-circuited such identification is not manageable but in fact short-circuit of S resulted in the discharge of C for this case. The discharge of C happens because with S short-circuited and in state 2, the capacitor sees a smaller impedance path to discharge through. Such path is described with KVL as u u _ + u + u + u + u + u + u + u + u = 0 (4.1) and the behaviour in the major discharge is represented in Figure

76 Figure Voltage sharing in IGBTs in five-level converter with short-circuit fault in IGBT2. Figure Discharging loop of C 2 in five-level converter. 54

77 To calculate the maximum short-circuit current peak the same ponderings are used disregarding the contribution from the DC bus and other capacitors because they are connected to the loop involved presenting large impedance. So assuming a balanced voltage in C with 125 kv and the same value for all conducting resistance in the semiconductors as also for the parasite resistance in the capacitor (r = 0,1 Ω), the short-circuit current is described by I = r 139 ka (4.2) Compared (4.2) against the resultant peak in the three-level converter, (4.2), the maximum peak for the five-level converter is 3,6 times smaller. This difference exists primarily due to the voltage in the capacitor which is reduced in half and also because in (4.2) the loop contains one diode and three IGBTs (4 r ) while in this converter the current sees three diodes and five IGBTs (8 r ), disregarding the parasite resistance in the capacitors. If the calculations are made without a parasite resistance, the currents in both converters present a higher value but they necessarily have a higher difference. I = 625 ka I 156 ka (4.3) The maximum short-circuit peak is presented in Figure 4.31 for C where it presents a value smaller than expected. This difference is greater than the ones in the three-level case and is explained by the less balanced voltage in the capacitors because in the instant causing the discharge the voltage in C rounds 119 kv instead of 125 kv. Figure Short-circuit current peak in five-level converter with short-circuit in IGBT2. The simulation results for currents circulating in the semiconductors are presented in Figure 4.32 and Figure 4.33 for the same period of time as presented for voltages. According to the discharging loop, the current in state 2 was supposed to travel through D, D and D only, but is visible, also only in 55

78 state 2, the existence of important values of current circulating also in D, D, D, D and D despite not being simultaneously. So initially the discharge is made through the loop described but as long as the capacitor discharges and consequently the rest of them charge new working conditions are offered to the semiconductors enabling their conduction. Figure Currents in diode network in five-level converter with short-circuit fault in IGBT2. All this currents, disregarding the ones in the third column, flow equally along some groups of diodes and within each column they flow in separated instants but always on state 2. Specifically, while D conducts, D, D and D are quietly waiting for their turn and when they conduct they all present the same current through them. This behaviour also happens for the second column where D and D conduct the same current while D and D are waiting and vice-versa. A major association with this current distribution is made with the orientation of load current where the upper diodes conduct for a positive value and the bottom ones conduct for a negative value. But this is not entirely valid for every instant in state 2 because the voltage felt by the load is not absolutely zero. This little differences influence which diodes conduct and those who don t conduct during some intervals. Another possible occurrence happens when the voltage in C is really small enhancing the possibility of conduction to D and D, inclusively creating a negative voltage through the terminals of the capacitor when they do. 56

79 Figure Currents in IGBTs in five-level converter with short-circuit fault in IGBT2. The current seen in IGBTs reflects the analysis made to the conduction in the diodes once it demonstrates the differences in the current between some adjacent semiconductors. For example S and S are different when D /D conduct because the diodes are connected to the IGBTs inner point. This is also noticed for the current circulating in S and S where the difference between them is created by the conduction on D, D and D. The current in the capacitors for the same period of time is represented in Figure 4.34 where is noticed the change in the current of C when the converter operates in state 2. Figure Currents in the capacitors in five-level converter with a short-circuit fault in IGBT2. 57

80 The load voltage and current is presented in Figure 4.35 for the same period of time as the simulations before where the trending of the voltage in the capacitors does not balance the voltage in the load yet. Figure Load voltage and current in five-level converter with a short-circuit fault in IGBT Short-circuit fault in IGBT 3 Following the same general representation idea, the semiconductors are arranged according to Table 4.9 and the same way the case of IGBT 1, it is not established any series connection between the short-circuited semiconductor and the rest of the regular operating semiconductors. This assumption implies a lack of change in the currents circulation through all the converter and necessarily also amends the voltage distribution in at least one semiconductor. Table Command signals in five-level diode-clamped converter with short-circuit in IGBT3. State ID S S S S S S S S Another observation can be made respecting the conduction duty where, since S is one of the inner IGBTs, the possible voltage unbalanced seen only happens in state 3 which is a smaller conducting duty state. This short-circuit involves directly the loop described by u u _ + u + u + u u u u = 0 (4.4) 58

81 and if for states 1 and 2 (IGBT 3 is usually ON) is u that always withstands the voltage in the capacitor, now in state 3 the voltage difference created by the short-circuit needs to be balanced through the diodes. Since the diodes cannot withstand direct voltages so high, they would conduct a large current supplied by C which is not feasible in this case, so D and D are discarded and the voltage is distributed by D, D and D but not necessarily balanced between them. The distribution is related not only with the blocking capability of each one, but also with the adjacent loops where they are inserted. Another influence in the converter exists, and according to (3.14), (3.15) and (3.16), is expected that the voltage trade-off among the IGBTs is made with S withstanding 250 kv. Just looking to (3.16) and already knowing that in state 3 D, D and D withstand extra voltage, is easily identified the voltage applied in S. These are the first direct observations that can be made, but while the fault in IGBT 1 only forces D, now, for example, with D affected other diodes, are automatically also affected due to the clamping between themselves where one case is described by u + u + u u = 0 (4.5) and consequently other diodes are also involved through other loops. So the simulation results for the voltage in all semiconductors, IGBTs and diodes along the network, are presented in Figure 4.36 and Figure Figure Voltage in diode network in five-level converter with short-circuit fault in IGBT3. In the third column is visible a reverse voltage applied to D and D in state 3 but not applied to D when in fact the equivalent resistance in the blocking state for this diode is bigger than for the other two. Also the one used for D is bigger than the one applied to D and its voltage is smaller. This proves the voltage distribution is dependent on all the loops along the network. In this case the 59

82 voltages across the diodes from the second column do not present any reasonable change but if the values of the equivalent resistances are different somehow alterations can be found. For example in a situation where D sees a reverse voltage in state 3, consequently D changes its reverse voltage, reducing it, due to (3.13) which consequently forces D to a higher reverse voltage because both D and D withstand the voltage from C and C. The same is visible for D and D where the first withstands a smaller voltage than usual necessarily compensated by D. The voltage reduction in D is a consequence from D. In this trade-off of voltage among the network the maximum reverse voltage in a semiconductor is never higher, in module, than approximately 250 kv because the usual reverse voltage is 125 kv and the unbalance is created through the short-circuit in a semiconductor previously withstanding 125 kv. Figure Voltage in IGBTs in five-level converter with short-circuit fault in IGBT3. As expected the active semiconductors maintain their behaviour exception made for S now withstanding the additional voltage resultant from the short-circuit in S. With all the changes seen in the diodes is presented Figure 4.38 as a verification that the currents circulating is still the same where only the second column of diodes conducts the load current and when on state 2. 60

83 Figure Currents in diode network in five-level converter with short-circuit fault in IGBT Short-circuit fault in IGBT 4 The fourth IGBT is also one of the inner active semiconductors in the converter as IGBT 3 and consequently is expected that short-circuit through its terminals creates the perturbations during a smaller conduction duty. In Table 4.10 is identified a series arrangement of the semiconductors in the third state specifically implying a discharge. Table Command signals in five-level diode-clamped converter with short-circuit in IGBT4. State ID S S S S S S S S Such discharge is presented in Figure 4.39 through the simulation result for the voltage applied to load and voltage in capacitors. So the fourth capacitor, C, presents descendent voltage in the negative half cycle, specifically due to state 3. The load sees three output levels, as in the case of IGBT 2 shortcircuited but now with a zero output always levelled. The evolution of the other capacitors is also similar to that case where now is C that trends to a 250 kv voltage while C and C after some amends trend to the usual 125 kv each. 61

84 Figure Load and capacitors voltage evolution in five-level converter with fault in IGBT4. Once again short-circuit creates a perturbation felt by load which is compensated after awhile through the increase of voltage in the adjacent capacitor that contributes to the same output level. The voltages applied to the diodes network and IGBTs are presented in Figure 4.40 and Figure 4.41 where, as for the short-circuit fault in IGBT 2, is possible to establish a direct link between some diodes and capacitors. In this situation is visible the relation between C, which is discharged, and D presenting no reverse voltage. Also for D exists a direct relation with the voltage in C. Figure Voltage in diode network with short-circuit fault in IGBT4. 62

85 With IGBTs the same happens, with S and S presenting a voltage value related with C. Also the short-circuit of S created, again, a discharge of C. Figure Voltage sharing in IGBTs in five-level converter with short-circuit fault in IGBT4. The reasons of discharge are always related to smaller impedance seen by the capacitor which in this case is described by u u _ + u + u + u + u + u + u + u + u = 0 (4.6) and represented in Figure

86 Figure Discharging loop of C 4 in five-level converter. Since the loop contains the same number of diodes and semiconductors, including the parasite resistance from the capacitor the maximum peak achieved by the short-circuit current is ideally the same that in (4.2). The result simulation is presented in Figure 4.43 where the first peak rounds 143 ka which implies about 4 ka of difference resultant mostly from the real voltage in C in that instant. The same reason as before explains these differences once the voltage in the capacitor is not exactly 125 kv in the precise instant of short-circuit. 64

87 Figure Capacitors current in major discharge in five-level converter with short-circuit fault in IGBT4. The circulation of currents in the semiconductors is presented in Figure 4.44 and Figure 4.45 where now the diodes from the second column conduct load current in state 2 as usual with no interference from any discharge because it happens in state 3. Figure Currents in the diode network in five-level converter with short-circuit fault in IGBT4. The third column diodes conduct the current according to the major discharging loop but not for every state 3 instant. It is noticed a gap in their conduction in the last quarter of the period in opposition to some small peaks seen in D indicating an attempt to conduct in this intervals. 65

88 Figure Currents in IGBTs in five-level converter with short-circuit fault in IGBT4. The current in IGBTs together with the currents in the capacitors presented in Figure 4.46 helps to notice that the current in the third column of the diode network, is not necessarily or only resultant from a discharge in C. For example in the first interval representing state 3 in this period, the first one after simulation time 0,99 s, the diodes present a high value of current through them while C is slightly charging. It also demonstrates that such current in the diodes do not necessarily travels entirely through the major discharging loop described as it also makes part of a loop containing the load and C. Figure Currents in the capacitors in five-level converter with short-circuit fault in IGBT4. 66

89 The load voltage and current is presented in Figure 4.47 for the same period of time as the simulations before. Figure Load Voltage and Current in five-level converter with short-circuit fault in IGBT Short-circuit faults in the lower IGBTs The fifth active semiconductor is part of the bottom switches and due to symmetry in the converter is expected that the behaviour for a short-circuit fault in IGBT 5 mirrors the short-circuit fault in IGBT 4 discharging C in state 1. In Table 4.11 is found the series connection causer of a discharge established for that state. Table Command signals in five-level diode-clamped converter with short-circuit in IGBT5. State ID S S S S S S S S

90 The load voltage evolution and the voltage existing in the capacitors is presented in Figure 4.48 where is easily identified the characteristics of a state with a smaller conduction duty and the discharge of C. This match with expected as it was already seen for the short-circuit faults in the bottom semiconductors of the three-level converter. Figure 4.48 Load and capacitors voltage evolution in five-level converter with fault in IGBT5. So the voltages and currents distributed along all semiconductors are expected to present some symmetry from the short-circuit fault in IGBT 4 case. In the IGBTs such symmetry is easy to predict since they are all connected in series from highest to lowest voltage point but the five-level converter presents not only two clamping diodes but instead a whole diode network. In any case symmetry between columns 1 and 3 exists since short-circuit now creates a discharging loop described by u u _ + u + u + u + u + u + u + u + u = 0 (4.7) where the first three diodes from the third column are replaced by the last three diodes from the first column, disregarding the IGBTs. This is a difference from the three-level case where only two loops served the four short-circuits of all IGBTs but a similitude is found once each capacitor has its only discharging loop. Until now were presented three loops in the five-level converter and the missing one which affects C and presents a symmetric behaviour from a short-circuit fault in IGBT 2 is described by u u _ + u + u + u + u + u + u + u + u = 0 (4.8) where D and D replace D and D. Also the loop ends through D while the other case uses D, precisely the first and last diodes of columns one and three respectively. This is caused with a shortcircuit in S. 68

91 Assuming all the voltages in the capacitors as ideally distributed and since only four IGBTs can create discharges allowing diodes from other columns than the second one to conduct, the currents circulation is symmetric between the upper and the lower IGBTs short-circuit fault cases. This assumption for the voltage distribution in all the semiconductors is also valid exception made for the symmetry between IGBT 3 and IGBT 6. A short-circuit fault in IGBT 6 is represented with the command signals of Table 4.12 where in state 1 the semiconductor is placed alone not establishing any possibility of conduction as the IGBT 3 case for state 3. In that point it was seen a voltage distribution through several diodes in the network which consequently affected some adjacent diodes. This same distribution is not possible to achieve symmetrically because it depends on each diode characteristics to divide the voltage. Table 4.12 Command signals in five-level diode-clamped converter with short-circuit in IGBT6. State ID S S S S S S S S The voltage distribution in the diode network for a short-circuit fault in IGBT 6 is presented in Figure 4.49 where the symmetry with Figure 4.36 is nonexistent. Figure Voltage in diode network in five-level converter with short-circuit fault in IGBT6. It is visible that S short-circuited forces D and D to withstand some high voltage in state 1 when previously withstand zero. Consequently due to the inner clamping of the diode network this affects the reverse voltage applied in other diodes as it can also be seen for D, D, D and D. 69

92 Simulation results for voltages and currents in diodes and IGBTs, for short-circuit faults in S and S creating a discharge, are presented in Annex B. 4.4 Seven-Level Diode-Clamped Converter The seven-level converter offers a more number of semiconductors to be tested but only the ones adjacent with a usual connection create a discharge. The number of semiconductors turned ON in the regular operation is six so short-circuit occurs with a series of seven IGBTs. In the previous converters four short-circuits happens in both, specifically for all the switches in the three-level converter and for switches S, S, S and S in the five-level converter. So is expected for the seven-level converter that its switches S, S, S and S create a discharge in one of the capacitors as demonstrated by Table Table Command signals with all possible short-circuits creating a discharge in seven-level converter. State ID S S S S S S S S S S S S Since the converter presents six capacitors and only four loops can be described, only four capacitors discharge, remaining two that will never discharge no matter which semiconductor presents a fault. The loops created by faults in this switches are u u _ + u + u + u + u + u + u + u + u + u + u + u + u = 0 (4.9) u u _ + u + u + u + u + u + u + u + u + u + u + u + u = 0 (4.10) u u _ + u + u + u + u + u + u + u + u + u + u + u + u = 0 (4.11) u u _ + u + u + u + u + u + u + u + u + u + u + u + u = 0 (4.12) respectively for S, S, S and S. Now the number of semiconductors composing the loop increases to twelve, specifically seven IGBTs and five diodes. So assuming an ideal voltage of 83,3 kv in the capacitor, the short-circuit current presents an approximate value of I = 83,3 13 r 64,08 ka (4.13) which is more than 2 times smaller than the five-level case and almost 8 times smaller than the threelevel case but yet is still a really huge value. With the already known unbalance of capacitors is 70

93 expected that simulation results present different values of current peak, some with higher and others with smaller values. Also with the increase of semiconductors in the path, the load impedance difference becomes smaller and attention is needed when disregarding its value in the short-circuit peak calculus. Looking to other IGBTs, there are now eight that force the clamping diodes to withstand extra voltage in their usual OFF states or even when it is supposed to withstand ideally zero. The simplest to analyze are S and S once they are on the upper and lower edges of the converter. These semiconductors short-circuited establish the direct connection of D and D in parallel with C and C respectively, being unable to conduct for all states. While in the five-level converter the short-circuit of edge IGBTs only provokes change in the specific diode, in this case some other small voltage tradeoffs exists initially in the adjacent D and D or D and D. Consequently with all inner loops in the diode network these small perturbations are spread by some of other diodes. Concerning IGBTs, since no discharge occurs, the voltage from S (S ) is now divided through the rest of the group where he is inserted, specifically S and S (S and S ). This is better than the previous case because not only the voltage is smaller as also the voltage difference is divided between more semiconductors. All the rest of the six IGBTs have an identical behaviour once they force the semiconductors in the group and also diodes in the network. But based on simulation results, only the first ones shortcircuited in each group, as S and S, assure a more balanced distribution in the rest of IGBTs from the same group. Some simulation results are then presented in Annex B. 4.5 n-level Diode-Clamped Converter The extensions of converter architectures to n levels do not interferes with the number of IGBTs that create a discharge in one of the capacitors and also reduces short-circuit current peak values. This reduction is related with the increasing number of semiconductors in the path, which represent higher impedance, and also with the smaller voltage in the capacitor. From previous analysis is noticed that semiconductors short-circuited must be adjacent to the usual series of a level of operation in order to create the new path with smaller impedance. With this condition in an n-level converter with an odd number of levels and operated as three, only four IGBTs cause discharges being easily identified from the start as also the capacitor they discharge. So in the upper IGBTs, from S until S, those adjacent switches are S ( ) and S discharging respectively C ( ) during state 2 and C during state 3, while for the lower IGBTs are S and S ( ) discharging C during state 1 and C ( ) during state 2. So the more external semiconductors cause the discharge of the middle capacitors and the inner semiconductors discharge the edge capacitors. 71

94 For a common DC bus with a voltage U and using only the conduction resistance of all semiconductors, assumed as equal, in the path, short-circuit current for an n-level converter is described as I = U (n 1) U = 2(n 1)r 2(n 1). (5.1) r So it decreases with the relation (n 1) for paths presenting much smaller impedance than load. When this assumption is no longer acceptable, short-circuit current needs to be calculated using load impedance in parallel with the respective half of the path and obviously creating differences between current flowing through the path and current effectively discharged by the capacitor. The current is then bigger and described as I = U (n 1) (n 1)r + (Z (n 1)r ) (Z + (n 1)r ) (5.2) where half of the path is in parallel with load and the other half is common to both in series. This expression is valid for discharges in state 2 because for other states needs to be added the contribution from other capacitors which now matter. In the seven-level case, with the characteristics used in simulation, this phenomenon is slightly noticed since a small part of the entire current discharged by the capacitor does not entirely flows through the new path created. But obviously if conduction impedances of semiconductors start to be higher than load impedance the greater amount of power transferred is lost on them and probably the converter is not sized properly. Short-circuit currents are extremely elevated for cases simulated but concerning just load voltage applied, the higher number of capacitors for each level allow a more steady output voltage in the converter. Even with one capacitor discharged, is seen the trend of the other capacitors in same level charging the voltage difference. This way load voltage is only slightly perturbed. Assuming one semiconductor can conduct 6 ka, as the load current used in simulations, with the same r for semiconductors, in a converter with an impedance much greater than a possible discharging path, the number of levels needed in such converter to stop semiconductors to be destroyed is 6 ka = 500 kv 2(n 1) r n > 21. (5.3) For standard value of current rating of IGBTs, 1kA, the number of levels needed is 1 ka = 500 kv 2(n 1) r n = 51. (5.4) Architecture like this needs 100 IGBTs with 100 anti-parallel diodes, 50 capacitors and 2450 clamping diodes with maximum voltage ratings rounding 10 kv. Despite the great reduction this voltage is still currently difficult to be applied to single semiconductors once the highest ratings available usually 72

95 round 6,5 kv. To respect this value using a single semiconductor in each specific position the number of levels in the converter is bigger than 77. Assuming a short-circuit current able to be eliminated by a fuse in the semiconductor short-circuited, opening the circuit, turns impossible positive load current circulation if the fuse acts in one of upper IGBTs or negative load current for a lower IGBT. So only the anti-parallel diode conducts current in the opposite direction. This solution is not effective to maintain acceptable converter output behaviour. A possible solution, concerning load, consists also in interrupting short-circuit current but instead of acting in the semiconductor, a circuit breaker is placed in the connection between specific capacitors and diode network, except in the connection to neutral point. This breaker offers the possibility to maintain load current behaviour without short-circuit currents flowing in the converter and without discharging all the voltage in the specific capacitor, but is not a solution for voltage unbalance in semiconductors. Also the breaker interrupts one important connection in topology that initially helps voltage sharing and induces new voltage sharing features in some diodes, not necessarily better. The other IGBTs do not provoke a discharge and only force other semiconductors to some extra voltage. In worst cases semiconductors are forced to withstand twice the ideal voltage. It is seen for five and seven-level sets that the IGBTs affected in these cases are the ones in the same group of the short-circuited one and they divide the voltage difference between them. So two benefits arise for higher number of levels sets because the voltage is smaller an also it is divided along more IGBTs. A converter with 81 levels, respecting previous 6,5 kv rate of semiconductors, has 6,25 kv in the capacitors and groups with 40 switches. Being this voltage ideally divided by the 39 corresponding switches, only 0,16 kv are added to voltage applied to IGBTs. Obviously ideal distribution does not occur and in the seven-level case, with three semiconductors in the group, is more evident the voltage being distributed by semiconductors beneath the short-circuited one, but if manageable the IGBTs still work without over-voltage problem. The voltage unbalance in diodes is difficult to predict for short-circuit faults in active semiconductors. If a short-circuit current takes place discharging all voltage in one capacitor, then the voltage in diodes D is approximately the same in capacitor C. If the IGBT short-circuited does not create any discharge, is expected some voltage trade-off with some diodes previously withstanding almost zero. With the existing connections linking columns to each other, this first trade-off consequently forces more diodes in other columns to withstand more voltage. The worst condition possible for a diode is to withstand twice the voltage it is expected. 73

96 74

97 Chapter 5 Conclusions 5.1 General Conclusions The current thesis intended to demonstrate the influence of short-circuit events, in a single active semiconductor, during the operation of diode-clamped converters with different number of levels sets and controlled as three-level converters in high voltage conditions. It is possible to conclude that with architectures designed for higher number of levels, the short-circuit currents created are smaller and always only 4 IGBTs can cause such anomalies no matter the number of levels. The other IGBTs when short-circuited force other semiconductors, diodes and IGBTs, to withstand some extra voltage in worst cases but never more than the double they ideally withstand. Also a trade-off exists when voltage in diode network is changed due to all inner connections between columns, so when some diodes withstand more voltage, others necessarily withstand less. Concerning the load, also with higher number of levels in the topology, it benefits from the higher number of capacitors used to perform each level when a discharge occurs once it never completely loses the three voltage levels. This way the load voltage difference created is smaller and load current is less perturbed. Inclusively the rest of the capacitors charge such voltage difference allowing the voltage applied to load to regain a regular behaviour after awhile but attention is required to the common voltage unbalance in capacitors. Load is not also affected at all when one of other IGBTs than the specific 4 presents a short-circuit fault despite the change of voltage sharing in some semiconductors. The voltage balancing in the semiconductors appears to be more complicated to control with the increase of levels. The clamping diodes network with high density of semiconductors does not create the ideal balanced voltage across them, and consequently also IGBTs present some voltage fluctuations through their terminals, but its use achieves much better results once, for cases tested, the maximum voltage in the semiconductors have mainly acceptable differences with few worse cases. To abridge conclusions, the converter with high number of levels architecture, operated as a threelevel converter, working with short-circuit faults in a single semiconductor, provides better and acceptable answers to load than a three-level converter, usual NPC. Short-circuit currents can be very high and destructive but are reduced increasing the number of levels. To eliminate short-circuit currents in adequate time and keeping load in acceptable working conditions, a circuit breaker in the connection between diode network and capacitors should be placed, except in neutral point. The major problems for every case arise from voltage distribution in semiconductors once in the worst 75

98 case is possible to one semiconductor to withstand twice the voltage ideally designed. This is a problem because is not expected to use semiconductors with twice the voltage rating than necessary to operate the converter. Also no more series connection of semiconductors then the ones in the architecture is desired once the study is focused on an n-level converter. 5.2 Future Works In the development of every work new approaches, new solutions and new possible studies appear and some are presented in order to complete this thesis. An extension of levels can be made using the same diode network to study voltage sharing for a higher number of levels, study open-circuit situations in semiconductors that do not create a short-circuit current to identify problems and solutions in the operation of the converter and study some approaches to face the voltage unbalance in capacitors. Also another PWM control can be used and short-circuit situations for three-phase cases can be study. At last interconnect two converters trough a DC cable and them to respective AC networks to simulate a more complete HVDC system. 76

99 References [1]. [Online] [Cited: 4 February 2009.] [2]. Angelidis, V. G., Demetriades, G. D. and Flourentzou, N. Recent Advances in High-Voltage Direct- Current Power Transmission Systems. IEEE International Conference on Industrial Technology [3]. Asplund, G., Carlsson, L. and Tollerz, O. 50 years HVDC. ABB Review [4]. Silva, José Fernando. Multilevel Conversion in Power Electronics (in Portuguese) [5]. Lai, J.-S. and Peng, F. Z. Multilevel Converters - A New Breed of Power Converters. IEEE Transactions on Industry Applications. May/June 1996, Vols. 32, no 3, pp [6]. Grünbam, R., Gustafsson, T. and Olsson, U. SVC Light: Evaluation of First Installation at Hagfors, Sweden. [7]. Choi, N. S., Cho, J. G. and Cho, G. H. A General Circuit Topology of Multilevel Inverter. IEEE 22nd Annual Power Electronics Specialists Conference June 1991, pp [8]. Rodríguez, J., Lai, J.-S. and Peng, F. Z. Multilevel Inverters: A Survey of Topologies, Controls, and Applications. IEEE Transactions on Industrial Electronics. August 2002, Vol. 49, pp [9]. Meynard, T. A. and Foch, H. Multilevel Converters And Derived Topologies for High Power Conversion. IEEE 21st International Industrial Electronics, Control, and Instrumentation November 1995, Vol. 1, pp [10]. Meynard, T. A. and Foch, H. Multi-Level Conversion: High Voltage Choppers and Voltage Source-Source Inverters. IEEE Power Electronics Specialists Conference. 1992, pp [11]. Marchesoni, M., Mazzucchelli, M. and Tenconi, S. A Non Conventional Power Converter for Plasma Stabilization. IEEE Transactions on Power Electronics. April 1990, Vol. 5, no 2. [12]. Peng, F.Z., et al. A Multilevel Voltage-Source Inverter with Separate DC Sources for Static Var Generation. IEEE Transactions on Industry Applications. September/October 1996, Vol. 32, no 5, pp [13]. Nabae, A., Takahashi, I. and Akagi, H. A New Neutral-Point-Clamped PWM Inverter. IEEE Transactions on Industry Applications. September/October 1981, Vols. IA-17, pp [14]. Carrara, G. et al. A New Multilevel PWM Method: A Theoretical Analysis. IEEE Transactions on Power Electronics. July 1992, Vol. 7, pp [15]. Manjrekar, M. and Venkataramanan, G. Advanced topologies and modulation strategies for multilevel inverters. 1996, pp [16]. Khomfoi, S. and Tolbert, Leon M. Multilevel Power Converters. Power Electronics Handbook [17]. Newton, C. and Summer, M. Novel technique for maintaining balanced internal DC link voltages in diode clamped five-level inverters. IEE Proceedings Electric Power Applications. May 1999, Vol. 146, pp

100 [18]. Silva, José Fernando. Industrial Electronics (in Portuguese). Lisbon : Calouste Gulbenkian Foundation, [19]. Marques, M. R. Interconnection Between Small Power Systems (in Portuguese). Technical University of Lisbon - Technical Superior Institute. Lisbon, Portugal MSc Thesis. [20]. Bartholomeus, P., Le Moigne, P. and Akoe Mba, J.B. Over-voltage problems of diode-clamped converters during switchings. 78

101 Annex A Simulation models In this annex are presented simulation models built and simulation parameters in order to perform the study. Due to several repeating series connection of semiconductors in subsystems, only the first ones are presented once the only difference presented in others is the number of semiconductors or the internal change of some input and output flags. Figure A.1 PWM command signals. 79

102 Figure A.2 Three-level converter model. Figure A.3 Subsystem IGBT with anti-parallel diode. 80

103 Figure A.4 Short-circuit fault and fuse. Figure A.5 Five level converter model. 81

104 Figure A.6 Series connection of upper IGBTs. 82

105 Figure A.7 Column of diode network. 83

106 Figure A.8 Seven-level converter model. 84

107 Annex B Simulation results In this annex are presented some extra simulation results for currents and voltages which exhibit symmetric and similar behaviours. B.1 Operation of Seven-Level Converter Figure B.1 - Voltage in diode network in seven-level converter. 85

108 Figure B.2 - Voltage in IGBTs in seven-level converter. B.2 Five-Level Converter Short-Circuit faults in lower IGBTs Figure B.3 - Currents in diode network in five-level converter with short-circuit fault in IGBT5. 86

109 Figure B.4 - Voltage in diode network in five-level converter with short-circuit fault in IGBT5. Figure B.5 - Currents in IGBTs in five-level converter with short-circuit fault in IGBT5. 87

110 Figure B.6 - Voltage in diode network in five-level converter with short-circuit fault in IGBT6 Figure B.7 - Voltage in IGBTs in five-level converter with short-circuit fault in IGBT6 88

111 Figure B.8 - Currents in diode network in five-level converter with short-circuit fault in IGBT7. Figure B.9 - Voltage in diode network in five-level converter with short-circuit fault in IGBT7. 89

112 Figure B.10 - Currents in IGBTs in five-level converter with short-circuit fault in IGBT7. Figure B.11 - Voltage in IGBTs in five-level converter with short-circuit fault in IGBT7. 90

113 Figure B.12 - Voltage in diode network in five-level convert with short-circuit fault in IGBT8 Figure B.13 - Voltage in IGBTs in five-level converter with short-circuit fault in IGBT8. 91

114 B.3 Seven-Level Converter Short-Circuit Faults Figure B.14 Load and capacitors voltage in seven-level converter with short-circuit fault in IGBT3. Figure B.15 - Voltage in diode network in seven-level convert with short-circuit fault in IGBT1. 92