Comparison of Hybrid Asymmetric and Conventional Multilevel Inverters for Medium Voltage Drive Applications

Transcription

1 Comparison of Hybrid Asymmetric and Conventional Multilevel Inverters for Medium Voltage Drive Applications Master of Science Thesis in the Master s programme Electric Power Engineering AMIR SAJJAD BAHMAN Department of Energy and Environment Division of Electric Power Engineering CHALMERS UNIVERSITY OF TECHNOLOGY Göteborg, Sweden 211

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3 MASTER S THESIS 211 Comparison of Hybrid Asymmetric and Conventional Multilevel Inverters for Medium Voltage Drive Applications Master s Thesis in the Master s Programme Electric Power Engineering AMIR SAJJAD BAHMAN Department of Energy and Environment Division of Electric Power Engineering CHALMERS UNIVERSITY OF TECHNOLOGY Göteborg, Sweden 211

4 Comparison of Hybrid Asymmetric and Conventional Multilevel Inverters for Medium Voltage Drive Applications Master s Thesis in the Master s Programme in Electric Power Engineering AMIR SAJJAD BAHMAN AMIR SAJJAD BAHMAN, 211 Department of Energy and Environment Division of Electric Power Engineering Chalmers University of Technology SE Göteborg Sweden Telephone: + 46 () Cover: A medium-voltage frequency converter, the ABB PCS 6 Wind, Reference: Göteborg, Sweden 211

5 Comparison of Hybrid Asymmetric and Conventional Multilevel Inverters for Medium Voltage Drive Applications Master s Thesis in Master s Programme in Electric Power Engineering AMIR SAJJAD BAHMAN Department of Energy and Environment Electric Power Engineering Chalmers University of Technology ABSTRACT Power electronic converters are becoming more and more popular for various industrial applications. To overcome the limitation of semiconductors current and voltage ratings in high power applications, series and parallel connection of switches is often considered an effective solution. In addition, stepped waveform in the output of inverter has better harmonic spectrum than 2-level waveform in low switching frequencies. So, in recent years multilevel inverters have gained great interest in industry. Among the different solutions available for multilevel converters, the asymmetric topologies allow to generate more voltage levels with less number of semiconductors and thus increase of output performance and system reliability. For these reasons, this kind of topology has attracted a lot of attention both from the customers and from the manufacturers. Application of appropriate semiconductor switches in the different cells of the inverter leads to increase of inverter efficiency. This inverter is typically known as hybrid inverter. In this work, different topologies of multilevel inverters consisting cascaded symmetric, diode-clamped, flying-capacitor, and hybrid asymmetric are investigated. It will be shown that hybrid asymmetric inverter has more reliable topology than others, due to less number of power semiconductor switches and higher voltage levels. Also different multilevel modulation techniques will be studied form voltage waveforms and harmonic spectra aspects. This study proves that Phase Disposition Pulse Width Modulation shows less harmonic distortion than other techniques. Comparison of hybrid asymmetric inverter with conventional multilevel inverters will be lead in two states of constant frequency and constant efficiency. The results indicate that, hybrid asymmetric topology has better performance in power losses, total harmonic distortion and first distortion factor than other topologies that leads to energy saving, better power quality and reduce in size, weight and volume of its LC filter. Key words: Hybrid asymmetric multilevel inverter, medium voltage drive, modulation techniques, power losses. I

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7 Acknowledgment This work has been carried out at the Division of Electric Power Engineering, Department of Energy and Environment at Chalmers University of Technology, Gothenburg, Sweden. I would like to thank first and foremost my examiner Dr. Massimo Bongiorno for his valuable and constructive suggestions during this work and advices in revising the thesis manuscript extensively to give it a better shape. I would also like to express my deep and sincere gratitude to my supervisor Dr. Ghasem Aghdam for his patience, encouraging, stimulating and critical comments regarding the work. I express my sincere appreciation to Mohammadreza Derakhshanfar, Mehdi Javdani Erfani, Shahab Shariat Torbaghan, Ali Mehdipour, and Saeid Haghbin my dear friends at division for their help, suggestions, and friendship throughout my time at Chalmers and for all the great memories away from the research. Finally, I d like to dedicate this work to the love of my life, Mona, for her deep love, patience, and encouragement from a long distance and my dear family, my parents, Manouchehr and Nafiseh, my sister and brother, Sara and Ali, for their encouragement, support, and love which always warms my heart in the darkest moment. Göteborg March 211 Amir Sajjad Bahman III

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9 Contents ABSTRACT ACKNOWLEDGMENT CONTENTS I III V 1 INTRODUCTION High-power medium-voltage drives classification Multilevel inverters, features, advantages and applications Hybrid and asymmetric multilevel inverters Thesis topics 7 2 MULTILEVEL INVERTER TOPOLOGIES level and 3-level voltage source inverters Multilevel inverters Symmetric multilevel inverters Asymmetric multilevel inverter Hybrid multilevel inverters Conclusions 19 3 MODULATION TECHNIQUES Carrier based PWM level PWM Multilevel PWM Conclusion 34 4 DRIVE SYSTEM AND PERFORMANCE INDEXES Inverter specification Dc-link voltage Power semiconductor selection Performance indexes THD DF Semiconductor power losses Efficiency Conclusion 44 5 COMPARISON OF DIFFERENT MULTILEVEL INVERTERS Simulation environment Simulation results 48 V

10 5.2.1 Comparison at constant carrier frequency Comparison at constant efficiency 51 6 CONCLUSION AND FUTURE WORK Results Future work 54 7 REFERENCES 56 VI

11 1 Introduction The increasing demand for electrical energy, depleting fossil energy reserves and the increase in energy prices have necessitated to use the current energy resources more efficiently. Power electronic converters as the essential equipments to convert and control of electrical power in the wide range of milliwatts to gigawatts with the help of semiconductor devices are finding increased attention. Hence, highly efficient power electronic technologies and reliable control strategies are needed to reduce the waste of energy and to improve power quality. One of the most significant potentials to improve the efficiency of electrical energy in industry is electric motor drive systems. Today, medium voltage drives have found extensive application in various industries, such as oil, gas and petrochemical industry, the cement industry, water pumping stations, metal industry, rolling mills, traction applications, wind power generation, marine drives, reactive power compensation, high voltage direct current (HVDC) transmission as well as many other applications [1]. On the other hand, several industries have increased their power-level needs, urged mostly by economy of scale (production levels and efficiency), causing the development of new power semiconductors, converter topologies, and control methods. Currently, medium voltage drives cover a power range of.2 MW to 4 MW at voltage level of 2.3 kv up to 13.8 kv [2]. However, at present 97% of the currently installed medium voltage motors operate at fixed speed; and only 3% of these are controlled by variable-speed drives [1]. One of the major markets for medium voltage drives is retrofit applications. For instance, when fans or pumps are driven by fixed speed motor, air or liquid flow are controlled normally by conventional mechanical methods, such as throttling control, inlet dampers, and flow-control valves, resulting in large amount of energy loss [3]. Therefore, there is a huge scope for developing adjustable speed drives for industrial applications. The installation of controlled medium voltage variable-speed drives reduces the energy loss and leads to a significant savings on energy cost and improving the power quality [2]. The power quality of medium voltage drives is affected by the applied converter topology, the load characteristics, the size and the type of the utilized filter, the level of switching frequency, and the control method [1]. Nevertheless, the design of these drives is faced with a number of challenges related to topologies and control of power line side converter (e.g. power quality, resonance, and power factor) and motor side converter (e.g. dv/dt, torque ripples, motor derating caused by generated harmonics and travelling wave reflections), as well as power semiconductor devices (semiconductor losses)[1]. Essential requirements for medium voltage drives are high efficiency, high reliability, low cost, small size and in some applications, high dynamic performance and regeneration capability [1]. CHALMERS, Electric Power Engineering, Master s Thesis 211 1

12 1.1 High-power medium-voltage drives classification Fig. 1.1 shows a simplified classification of converters used in high-power medium-voltage applications, which have a main division into direct and indirect connections of power supply and load. The former usually connects the load to the source directly through power semiconductorss and suitable control method. The latter transfers the power indirectly in two stages of rectification and inversion via an energy-storage component [3]. For direct conversion, cycloconverters are the most used topology in high power applications, which use a series of semiconductor switches to connect directly the high power supply to the load. Cycloconverters convert a threethree-phase ac phase ac voltage with a fixed magnitude and frequency to a voltage with variable magnitude and variable frequency. Matrix converters are included in this category but they are not listed in classification, since the technology is not available for high-power ranges, reaching only up to 15 kva [4]. In the other side of this classification, indirect converters are divided basically into current-source and voltage-source topologies, depending on the dc-link energy-storage component. Medium- Voltage Drives Direct conversion ac-ac Indirect conversion (DC-Link) ac-dc-ac Cycloconverter Current Source Voltage Source PWM Current Source Inverter Multilevel Inverters High Power 2-level VSI Load Commutated Inverter Single DC source Multiple Isolated DC sources NPC Cascaded H-Bridge Flying Capacitor Symmetric (Equal DC sources) Asymmetric (Unequal DC sources) Fig. 1.1 Classification of converters topologies for high-power drives 2 CHALMERS, Electric Power Engineering, Master s Thesis 211

13 Fig. 1.2 shows a typical view of an indirect medium-voltage drive. Depending on the system demands and the type of converters applied, the line and motor side filters are optional. A phase shifting transformer with multiple secondary windings is often utilized mainly for the line current distortions. The rectifier converts the power supply voltage to a dc voltage with a fixed or variable magnitude. The generally used rectifier topologies include multi-pulse diode or thyristor rectifiers and pulse width modulation (PWM) rectifiers. The dc link can simply be a capacitor that supplies a stiff dc voltage in voltage-source inverters or an inductor that smoothes the dc current in current-source inverters [3]. Fig. 1.2 Typical block diagram of medium voltage variable speed drives For current-source drives, two topologies have found industrial applications in high power ranges: the load-commutated inverter (LCI) and the PWM-CSI. The LCI has been utilized for many years presenting simple converter topology, low manufacturing cost, and reliable operation. Its main problems include low input power factor and distorted input current waveforms, which these problems are overcame by the newer technology of PWM-CSI [5]. On the other hand, high-power voltage-source inverters (VSI), have attracted more markets and developed significantly over the last decades, compared to current-source topologies. The voltage-source drives are divided in two groups of high-power two-level and multilevel inverters. The simplest topologies of VSIs are single-phase half-bridge inverter which generates a 2- level square-wave voltage and full-bridge inverter which generates 3-level waveform. These classical inverters were limited to low or medium power applications due to the limitations on the power semiconductor voltages and currents. The series connection of semiconductor switches enabled high twolevel VSIs for high-power applications. However, the addition of some other power components, like diodes or capacitors, and utilization of more complex switching methods permitted a more interesting use of these additional components to enhance the quality of input and output currents and voltages, originating the family of multilevel VSI technology. Although multilevel inverters were basically developed to reach higher voltage operation, before being restricted by semiconductor limitations, the extra switches and dc sources (supplied by dc-link capacitors) could be used to generate different voltage levels, enabling the generation of stepped CHALMERS, Electric Power Engineering, Master s Thesis 211 3

14 waveform with less harmonic distortion, reducing dv/dt and common-mode voltages. These characteristics have made them popular for high-power medium-voltage applications but the large number of semiconductor switches in these inverters, result in a reduction both of the reliability and efficiency of the drive [18]. Therefore, many power electronic researchers have made great effort in developing multilevel inverters with the same benefits and less number of semiconductor devices. 1.2 Multilevel inverters, features, advantages and applications In 8s, many power electronics researches were focused on increase of the current and voltage ratings of semiconductor devices. To obtain higher voltage levels, a group of researchers started to study new inverter topologies that were able to operate at high voltages. In 1981, A. Nabae, I. Takahashi and H. Akagi presented a new inverter topology, which was named neutralpoint-clamped PWM inverter (NPC-PWM). In fact, this topology was an improved circuit of the classical 2-level inverter [13]. Although the new topology was just 3-level inverter, it had the potential to be extended to N- levels. Today, this inverter is known as diode-clamped multilevel inverter [15]. Currently, in terms of topology, multilevel inverters can be mainly divided into three major groups: Cascaded multilevel inverters : These inverters include several H- bridge cells (Full-bridge inverters) connected in series. One leg of a cascaded multilevel inverter is shown in Fig In the same figure, it is possible to observe the structure of one individual cell. V dc 4 Cell4 V dc 4 Cell3 V a V dc 4 Cell2 V dc 4 Cell1 Fig. 1.3 Cascaded multilevel inverter 4 CHALMERS, Electric Power Engineering, Master s Thesis 211

15 Diode-clamped multilevel inverters : These inverters use clamped diodes and dc capacitors in order to generate ac voltage. This inverter is manufactured in 3, 4 and 5-level structures. The 3-level structure is known as neutral-point clamped (NPC) and is widely used in medium voltage, high power drives. One leg of an NPC inverter can be seen in Fig SW 1 V dc 2 SW 2 D 5 SW 3 V dc 2 D 6 SW 4 V a Fig. 1.4 NPC inverter Flying-capacitor multilevel inverter : In this topology, semiconductor devices are in series and their connecting points are clamped by extra capacitors, as it can be seen in Fig SW 1 V dc 2 SW 2 C 5 SW 3 V dc 2 SW 4 V a Fig. 1.5 Flying-capacitor inverter CHALMERS, Electric Power Engineering, Master s Thesis 211 5

16 Together with the converter topology, great effort has been addressed from the research community in investigating different switching methods for these inverters. This is mainly due to the fact that the adopted switching strategy impacts the harmonic spectrum of output waveforms as well as the switching and the conduction power losses. In case of multilevel converters, three switching methods are usually used [14]: Selective Harmonic Elimination. In this method, each switch is turned on and turned off once in a switching cycle and switching angles are usually chosen based on specific harmonics elimination or minimization of output voltage Total Harmonic Distortion (THD). Carrier-Based PWM. In this method, drive signals of switches are derived from comparison of reference signal with carrier signals. Space-Vector PWM. The space vector modulation technique is based on reconstruction of sampled reference voltage with help of switching space vectors of a voltage source inverter in a sampling period. 1.3 Hybrid and asymmetric multilevel inverters The topologies mentioned before are typically called symmetric multilevel inverters, because the dc link capacitors have the same voltages. Asymmetric multilevel inverters have the same topology as symmetric ones; the only difference is in the dc link voltages. However, the asymmetric multilevel inverters can generate higher number of output voltage levels with the same number of semiconductor switchers in symmetric ones. Therefore, in these inverters the efficiency is improved by using less semiconductor devices and more complicated switching algorithms; while, output filters are very small or even removed [14, 15]. One leg of an asymmetric multilevel inverter is shown in Fig Vdc 4 Cell2 V a V dc 4 Cell1 Fig. 1.6 Asymmetric multilevel inverter Since the different cells of asymmetric inverter work with different dc link voltages and different switching frequencies, it is more efficient to use appropriate semiconductor devices in different cells. For example, using IGCT (Integrated Gate-Commutated Thyristor) switches which are suitable for high voltage low frequency applications, in higher voltage cells decreases the 6 CHALMERS, Electric Power Engineering, Master s Thesis 211

17 power losses. These inverters are called hybrid multilevel inverters. A hybrid inverter which uses several types of semiconductors has many advantages [17, 18]. Active power is transferred by semiconductors with low losses and high reliability and the output harmonic spectrum is improved by other semiconductors. 1.4 Thesis topics This thesis investigates hybrid asymmetric multilevel inverters for medium voltage drive applications. In addition, it presents some comparisons of this type of inverters with conventional multilevel inverters in terms of harmonic distortion, power losses and efficiency. The inverter consists of a main cell with IGCT switches and a sub cell with IGBT (Insulated-Gate Bipolar Transistor) switches. Main and sub cells are connected in series in each phase [19]. IGCT is a device with high reverse voltage, high reliability and low losses which is used in the main cell [2-22], while IGBT is a device with high switching frequency which is used in the sub cell to obtain low harmonic spectrum in the output of inverter. In the second chapter of this thesis, a brief overview of different multilevel inverter topologies and new research topics in this field are presented and their advantages and disadvantages are discussed briefly. In addition, these topologies are compared in different aspects. At the end, the hybrid asymmetric multilevel inverter topology is derived. In Chapter 3, different modulation techniques in voltage source inverters are explained. Also, the carrier-based multilevel PWM, which is applied in hybrid asymmetric multilevel inverters extensively, is analyzed briefly and different multilevel PWM techniques are compared from voltage waveforms and harmonic spectra aspects and the most appropriate modulation technique is derived. In Chapter 4, the inverter specifications, semiconductor devices, and the performance indexes consisting power losses, harmonic distortions, and efficiency that will be compared in different topologies will be studied. In Chapter 5, the simulation environment and results of comparison between hybrid asymmetric and conventional multilevel inverters in two methods of constant carrier frequency and constant efficiency will be presented. In the last chapter, a summary of works which have been done on multilevel inverters in this work are presented; finally, future works that can be followed in continue of this thesis, are mentioned. CHALMERS, Electric Power Engineering, Master s Thesis 211 7

18 2 Multilevel Inverter Topologies In recent years, industry has demanded for high power equipments, which today reaches to megawatts. Adjustable ac drives which operate in high power range are usually connected to the medium voltage network. Hence, medium and high voltage ac drive systems have been considered widely. Today, due to limitation of semiconductor devices to operate in high current and voltage ratings, it is difficult to connect a semiconductor switch directly to medium voltage networks ( kv). To achieve this problem, a family of multilevel inverters has been emerged for working in medium and high voltage levels [23]. Multilevel inverters consist of a series of power semiconductor devices and capacitors, which generate voltages with stepped waveforms in the output. Fig. 2.1 shows one phase leg of multilevel inverters. In this schematic diagram, operations of semiconductors are shown by an ideal switch with several states. The switching algorithms of switches and commutation of them allow the addition of the capacitor voltages as temporary dc voltage sources, whereas the semiconductors should withstand limited voltages of capacitors. V C a V C V a V C Fig. 2.1 One phase leg of a multilevel inverter The large number of semiconductors in the multilevel inverters has a negative impact on the reliability and on the overall efficiency of these types of converters. On the other hand, using inverters with the low number of semiconductors needs large and expensive LC filters to limit insulation stress of motor windings or can be applied for motors that can withstand this stress [6-12]. In this chapter, first the structure of inverter is briefly explained and then different topologies of multilevel inverters, their advantages, disadvantages and comparison in different aspects are discussed. In this case, first the topologies of symmetric multilevel inverters are investigated and then asymmetric multilevel inverters are discussed. Finally, based on these inverters, the topology of hybrid asymmetric multilevel inverter is derived. 8 CHALMERS, Electric Power Engineering, Master s Thesis 211

19 2.1 2-level and 3-level voltage source inverters Generally inverters can be divided in two major groups: single-phase inverters and three-phase inverters. The simplest inverter structure is halfbridge single-phase inverter which generates 2-level square waveform, whereas output waveform of a full-bridge single-phase inverter is 3-level square waveform. Full-bridge inverters are known as H-bridge inverter due to their structure shape. These two structures are shown in Fig. 2.2 and Fig In half-bridge single-phase inverter, two switches are needed which should not be turned on simultaneously to prevent short-circuit of the dc source. In first half-cycle, is on and is off, so load voltage is equal to /2. In second half-cycle, is off and is on so load voltage is equal to /2. In full-bridge inverter when (, ) are on and (, ) are off, load voltage is equal to whereas, in the case of (, ) are off and (, ) are on, is seen on load. To apply zero voltage on load, (, should be on and (, ) should be off or vice versa. Similar to the half-bridge case, in full-bridge inverter the pairs of (, ) and (, ) should not be on simultaneously. The output voltage waveforms of half-bridge and full-bridge inverter are shown in Fig. 2.4 and Fig / 2 V dc S 1 v o i o / 2 V dc S 2 Fig. 2.2 Half-bridge inverter power circuit S 1 S 4 V dc i o v o S 3 S 2 Fig. 2.3 Full-bridge inverter power circuit (H-bridge) CHALMERS, Electric Power Engineering, Master s Thesis 211 9

20 v o /2 V dc V dc / 2 Fig. 2.4 Half-bridge inverter output voltage waveform v o V dc V dc 2.2 Multilevel inverters Fig. 2.5 Full-bridge inverter output voltage Multilevel inverters are being used widely in static VAr compensators, active power filters and adjustable speed drives (ASDs) for medium voltage induction motors [23]. Usually the inverters which generate more than two phase potentials are known as multilevel inverters. By increase of the voltage levels to infinite value, THD of voltage waveform decreases to zero, since the waveform will be more sinusoidal; but, in practice the accessible voltage level is limited because of voltage unbalancing problems and power losses [23]. In this part, the most important topologies of multilevel inverters and their characteristics will be discussed Symmetric multilevel inverters There are three decades that multilevel inverters are being used in the world of power electronics [8]. They are named by the number of voltage levels that generate and different topologies they have. Usually the number of output voltage levels is odd instead of even. It means that the definition of a zero voltage level in the output of inverter like in 3-level or 5-level inverters makes it more sinusoidal and less harmonics are made. This issue will be discussed later in this chapter. As discussed in the introductory part of this 1 CHALMERS, Electric Power Engineering, Master s Thesis 211

21 thesis, the most conventional topologies of multilevel inverters are listed below [23]: Cascaded H-Bridge multilevel inverter Diode-clamped multilevel inverter Flying-capacitor multilevel inverter These inverters are known as symmetric multilevel inverters, since their DC link capacitors have the same voltages and all the semiconductor devices should be able to block these voltages in the off state Cascaded H-bridge multilevel inverter i Fig. 2.6 shows the power circuit of a 5-level cascaded H-bridge inverter [6, 1, 24]. For clarity of the figure, only one phase is shown in the figure. In this topology power cells are in series and the number of phase voltage levels that can be obtained at the converter terminals is proportional to the number of cells. In other words, in this topology the number of phase voltage levels at the converter terminals is 2 1, where is the number of cells or dc link voltages. In this topology, each cell has separate dc link capacitor and the voltage across the capacitor might differ among the cells. So, each power circuit needs just one dc voltage source. The number of dc link capacitors is proportional to the number of phase voltage levels. The ground point shown in Fig. 2.6 is a common reference point and all phases are connected in this point. Each H-bridge cell may have positive, negative or zero voltage. Final output voltage is the sum of all H-bridge cell voltages and is symmetric with respect to neutral point, so the number of voltage levels is odd. Cascaded H-bridge multilevel inverters typically use IGBT switches. These switches have low block voltage and high switching frequency. Cascaded H- bridge inverters have excellent input current and output voltage waveforms. Output voltage has smooth steps, so the output filter is usually not needed or in the case of necessity it can be very small [12]. The most important problems with the drives using this inverter are the high number of devices to rectify ac to dc voltage, complex switching patterns to command all the switches and need of multi-pulse input transformer that affect the efficiency, reliability and system costs [16]. V dc 4 V dc 4 V a Fig. 2.6 Cascaded H-bridge 5-level power circuit CHALMERS, Electric Power Engineering, Master s Thesis

22 Diode-clamped multilevel inverter Fig. 2.7 shows the power circuit of a 5-level diode-clamped inverter [9, 13]. For clarity of the figure, only one phase is shown. In this topology, semiconductor devices are connected in series and dc link is divided to smaller capacitors and connects to switches by clamp diodes. The clamp diode connections are necessary to block the current and their numbers in each leg are selected in such a way to have the same block voltages like the switches. DC link capacitors are the same for all phases, so one dc voltage source is needed for the dc link. The number of capacitors in each phase is proportional to the number of phase voltage levels. The ground point shown in the figure is the common reference point and is connected to the middle of dc link. To generate N voltage levels by the aim of the diode-clamped inverter, N-1 capacitors are needed on the dc bus [25]. For example, in a 5-level inverter shown in fig 2.7, dc bus voltage consists of four capacitors:,, and. If they are being fed by a dc link voltage of, the capacitors voltages will be /4. Table 2.1 presents switching pattern of a 5-level diode-clamped inverter. 1 indicates that the switch is ON and indicates that the switch is OFF. It is obvious from this table that in each cycle just four switches should be ON. S 1 V dc 4 C 1 S 2 V dc 4 C 2 S 3 S 4 V a V dc 4 C 3 S 5 S 6 V dc 4 C 4 S 7 S 8 Fig. 2.7 Diode-clamped 5-level inverter power circuit 12 CHALMERS, Electric Power Engineering, Master s Thesis 211

23 Table 2.1 Diode-clamped 5-level inverter switch states Output Switch state S S S S S S S S V / V / V / V / Since in Diode-clamped multilevel inverter topology switches should withstand the dc link voltage, this topology uses HV-IGBT (High Voltage IGBT) switches, but IGCT switches seem to be more suitable for this application. Diode-clamped multilevel inverter has a simple circuit but generates high and steep voltage steps which may impact the life time of the motor windings; therefore, an additional filtering stage is needed to reduce the ripple in the inverter output voltage. Theses filters are usually heavy and expensive in comparison with the filters used in cascaded H-bridge inverters [25] Flying-capacitor multilevel inverter Fig. 2.8 shows one phase leg of the power circuit for a flying-capacitor 5- level inverter [23]. In this topology semiconductor devices are connected in series and their connecting points are clamped by extra capacitors. In this topology series connections of clamped capacitors are necessary to block the current and their numbers in each leg are selected in such a way that all the capacitors store the same energy. In this way large and heavy capacitors will not be needed. The ground point shown in the figure is the common reference point and, similarly to the diode-clamped topology described in the previous section, is connected to the middle point of the dc link. The output voltage is symmetric with respect to the neutral point. When using this kind of inverter topology, if the system generates even voltage levels, the number of dc link capacitors will be odd. In other words, to generate N-level output voltage, N-1 dc link capacitors are needed [25]. It is clear in Fig. 2.8 that there is not any connections in the three interior loops between balancing capacitors (,, ) to the dc link sources for each phase, like the diode clamped topology. Table 2.2 presents switching pattern of a 5-level flying-capacitor inverter. Large number of clamped capacitors makes this inverter bulky and expensive. Also, to balance the capacitors voltages, specific controls and accurate measurements should be considered. CHALMERS, Electric Power Engineering, Master s Thesis

24 V dc 4 C 1 S 1 S 2 C c V dc 4 C 2 C b S 3 S 4 C c C a V a V dc 4 C 3 C b S 5 S 6 C c S 7 V dc 4 C 4 S 8 Fig. 2.8 Flying-capacitor 5-level inverter power circuit Table 2.2 Flying-capacitor 5-level inverter switch states Output Switch state S S S S S S S S V / V / V / V / Required components for different topologies Totally, considering the cost of semiconductors and passive components, converter losses and simplicity of modulation schemes, cascaded H-bridge and diode-clamped inverters are more used in large motor drive applications. Flying capacitor inverters can be used in DC/DC converters since their phase voltage looks like that of a full-bridge phase shift modulated DC/DC converters [23]. In Table 2.3, required components of different N-level topologies discussed till now are brought together [23]. 14 CHALMERS, Electric Power Engineering, Master s Thesis 211

25 Table 2.3 Required components of multilevel inverters (N-level) form different aspects Topology A B C D E F g Cascaded H-bridge 6(N-1) Even: (3N/2)- 1.5 Odd: Even: (3N/2)-1.5 Odd: /(N-1) 2N-1 (3N/2)-2 (3N/2)-2 Diodeclamped 6(N-1) 6(N-2) 3 (N-1) (N-2) N-1 N-1 /(N-1) 2N-1 Flyingcapacitor 6(N-1) 3N /(N-1) 2N-1 A: switches (including free-wheeling diodes) B: required diodes (with different reverse voltages) C: required diodes (if the same reverse voltage distribution on them is targeted) D: required capacitors E: required capacitors (if the same voltage distribution across the capacitors is targeted) F: maximum voltage applied for each cell/dc link capacitor G: line-to-line output voltage levels Asymmetric multilevel inverter As mentioned earlier, symmetric multilevel inverters are characterized by the fact that the voltages across the different dc link capacitors are equal. One interesting alternative is to have different capacitor voltages. This topology of inverters is known as asymmetric multilevel inverter. Although the focus for this kind of inverters has been mainly addressed in the direction of cascaded H-bridge asymmetric multilevel [14-18], asymmetric inverters can also be derived from diode-clamped and flying-capacitor inverters or a combination of them either [16, 18]. Asymmetric multilevel inverters have the same circuit configuration as symmetric ones. The only difference is the dc link capacitor voltages. Using different dc link voltages in different power cells and application the appropriate switching methods, the number of output voltage levels increases. Therefore, with less number of H-bridge cells, more output voltage levels can be obtained. In Fig. 2.9 and Fig. 2.1 two types of 9-level symmetric and asymmetric inverters are shown. According to these figures, in the symmetric inverter, CHALMERS, Electric Power Engineering, Master s Thesis

26 four cells are needed to generate 9-level voltage, whereas in the asymmetric inverter two cells are enough to generate the same number of voltage levels. The operation method of asymmetric inverters will be explained in Section The number of phase voltage levels in asymmetric multilevel inverter is calculated by equation 2.1: 2. V where N is the number of inverter cells and is the normalized dc voltage of each cell with respect to the dc link capacitor voltage. This equation can easily be obtained by considering the derivation of asymmetric topology from cascaded symmetric inverter. For example, for the asymmetric inverter shown in Fig. 2.1 the number of output voltage levels is 2.(1+3)+1=9. It of importance to mention that the switches applied in the symmetric inverter have the same off-state voltage, but in the asymmetric inverter, due to different voltage levels of dc link sources, the size of switches can be different. Vdc V dc V dc V dc Va Fig level symmetric inverter power circuit 3V dc V dc a V Inverter states and voltages v Fig level asymmetric inverter power circuit In a cascaded H-bridge asymmetric multilevel inverter, each cell has four switching states. Output voltages are:, and (two times). So, there are three different states with different voltages. If the voltage of cell is named, this voltage is defined as the following:, 1,, 1 where is the switching state and is the cells capacitor voltages CHALMERS, Electric Power Engineering, Master s Thesis 211

27 If multilevel inverter is constituted by N cells, then the output voltage with respect to the neutral point is give by, 2.3 From (2.3) it can be seen that the final output voltage is the sum of each cell voltage. According to the discussion above, a graph is formed and inverter states and output voltages are specified, Fig It is obvious that the starting point of this graph is the neutral point and the voltage is zero in this point. The nodes in this graph indicate the possible voltages for each cell. It is clear from this figure that each cell can generate three voltage levels. Therefore, by applying different dc link voltage levels to different cells and combination of them, more voltage levels can be obtained in the output of inverter terminals. This combination can be done up to the cell. Each branch of this graph indicates a switching state of each cell, therefore each route of these graph shows a switching state of the inverter. It should be mentioned that it is possible for different routes to arrive in a same output voltage. (a) (b) Fig Inverter states and output voltages for each phase (a) 9-level symmetric inverter, (b) 9-level asymmetric inverter Cell voltages, switching power and frequency f In the symmetric multilevel inverters, all cells have the same voltages, whereas in asymmetric multilevel inverters different cells may have different voltages. In chapter 4, it will be shown that how the different dc link voltages affects the switching power losses and frequency. 2.3 Hybrid multilevel inverters In previous sections, symmetric inverters, asymmetric inverters and their characteristics were discussed. In this section these topologies are synthesized and another topology that is called hybrid multilevel inverter is derived. CHALMERS, Electric Power Engineering, Master s Thesis

28 This topology has a simple circuit with high reliability, power quality and efficiency. According to Section 2.1, in multilevel inverters two topologies are more applied in medium voltage industrial applications especially in electric drives: cascaded H-bridge inverter and diode-clamped inverter. In addition, both topologies have some advantages and disadvantages. In fact, the important matters are compromise in power quality of converter in both line and motor sides, circuit complexity that affects efficiency, reliability and cost of inverter. H-bridge cascaded inverter has excellent input current and output voltage waveforms but it requires many devices to rectify the ac voltage to the dc voltage, many control equipments and complexity multi-pulse transformer design. Diode-clamped multilevel inverter has a simple circuit but needs LC filter to drive the motor. This compromise can be done by using asymmetric multilevel inverter. Using asymmetric method in cascaded H-bridge inverter increases the number of output voltage levels. As a result, by using an asymmetric multilevel inverter, power semiconductors should withstand high reverse voltage in the off-state. So, if the voltage ratio of cell supplying voltages is selected 3 to 1 or more, the semiconductor switches should not be the same in all cells. In this case, depending on the voltage level, it is suggested that an appropriate switch used. In other words, larger cells which work in higher voltages, transfer high active power and operate in low switching frequencies [16-19]. HV-IGBT or IGCT switches with reverse voltages more than 4.5 kv are used in these cells. IGCT switches works with high reliability; high reverse voltage and low off-state power losses [2-22]; whereas smaller cells which have lower voltages operate in higher switching frequencies. LV-IGBT switches are used in these cells; because this switch operates in high switching frequency and shows good performance in lower voltages. By combination of IGBT and IGCT in a hybrid asymmetric multilevel inverter, all the advantages of multilevel inverters can be achieved [17, 18]. This inverter is named hybrid since it uses two different types of semiconductor devices. Since, this inverter uses different voltage levels in the dc link capacitors, it can generate more voltage levels in the output and since, it uses two types of semiconductors in each cell, the power losses decreases either. This inverter is shown in Fig S 7 S 5 S 3 S 1 3V dc V dc V a S 8 S 6 S 4 S 2 Fig level hybrid asymmetric cascaded H-bridge inverter power circuit 18 CHALMERS, Electric Power Engineering, Master s Thesis 211

29 Fig shows the drive power circuit of a 3-phase hybrid asymmetric inverter. The inverter is composed of two parts: IGCT inverter or main inverter and IGBT inverter or sub inverter and they are connected in series in each phase. Usually in hybrid asymmetric multilevel inverters, the ratio of 3 to 1 is used between main and sub inverter capacitors in order to achieve maximum output voltage level; so finally the output phase voltage is 9-level [25]. Fig phase 9-level hybrid asymmetric inverter power circuit for drive applications 2.4 Conclusions In this chapter, conventional topologies of multilevel inverters have been investigated. First, different topologies of multilevel inverters, their advantages and disadvantages have been discussed. Then, based on symmetric multilevel inverter, asymmetric and hybrid multilevel inverter have been derived. Finally, the structure of the hybrid asymmetric multilevel inverter that is appropriate for high power, medium voltage drive applications has been described. CHALMERS, Electric Power Engineering, Master s Thesis

30 3 Modulation Techniques In many industrial applications, the output voltage of inverters should be controlled to overcome input voltage changes and meets the need of voltage/frequency control. It is obvious that output voltage harmonics are depended on the selected modulation technique. A high number of semiconductor devices and switching redundancies bring a higher level of complexity in multilevel topologies compared with a two-level inverter. However, this complexity can be used to improve the modulation technique, such as, reducing the switching frequency, minimizing the common-mode voltage or balancing the dc link voltages. Today, there are many modulation techniques for multilevel applications and they can be classified in two main groups, depending on their switching frequency: 1) fundamental switching frequency, where each inverter has only one commutation per cycle, and 2) high switching frequency, where each inverter has several commutations per cycle. These techniques are shown in Fig. 3.1[14-16] and can be defined as the following: Multi-Level Inverter Modulation Techniques Fundamental Switching Frequency High Switching Frequency Selective Harmonic Elimination (SHE) Space Vector PWM (SVM) Carrier-Based PWM Fig. 3.1 Conventional modulation techniques in multilevel inverters Selective Harmonic Elimination (SHE): In this technique, the switching angles are computed offline and are calculated in such a way that arbitrary harmonics, usually low order, up to m-1 harmonics are eliminated, where m is the number of switching angles. This modulation operates at a very low switching frequency to reduce the semiconductor losses. To minimize harmonic distortion and to achieve adjustable amplitude of the fundamental component, the most significant low-frequency harmonics are chosen for elimination by properly selecting angles among different level inverters. Space-Vector PWM (SVM): Each multilevel inverter has several switching states which generate different voltage vectors and can be used to modulate the reference. In SVM, the reference signal is generated from its closest signals. Some vectors have redundant switching states, meaning that they can be generated by more than one 2 CHALMERS, Electric Power Engineering, Master s Thesis 211

31 switching state. This feature is used for balance of capacitor voltages. Multilevel SVM must manage this behavior to optimize the search of the modulating vectors and apply an appropriate switching sequence. Carrier-Based PWM: This highly conventional technique is based on the comparison of a sinusoidal reference with carrier signals which are usually selected triangular and modified in phase or vertical positions to reduce the output voltage harmonic content. Due to simplicity and popularity of this technique, it will be analyzed in this chapter in details and will be used as the modulator of the multilevel topologies. 3.1 Carrier based PWM In this part, first fundamentals of PWM for 2-level converters and its characteristics will be explained. Then, this modulation will be investigated for multilevel inverter applications. For all of inverters (2-level or multilevel) minimum and maximum values of output voltages will be normalized to -1 and +1 with respect to the input dc voltage. For 2-level inverter which has two states, this is simply understandable, but for multilevel inverters depending on the number of output voltage levels, other states which are equally between the minimum and maximum, will be added level PWM Inverter gain can be defined as the ratio between the output ac voltage and the input dc voltage. There are different methods to change the inverter gain. The most effective method to control the gain and the output voltage of inverter is using PWM method in inverters. Fig. 3.2 shows 2-level PWM fundamentals. In this figure a reference signal which is usually a sinusoidal waveform, is compared with a carrier signal which is usually a triangular waveform. Based on this figure, if we assume that the average output voltage in switching cycle is, we have:, (3.1) where is the switching time where the reference signal is lower than the carrier. is the minimum voltage and is generated by subtraction of reference and carrier signals when the reference is lower than carrier. is the switching time where the reference signal is higher than the carrier and is the maximum voltage and is generated by subtraction of reference and carrier signals when the reference is higher than carrier. If we solve the above equation for two switching times, and, we have:, (3.2) The equation (3.2) shows a linear relation between switching times and average of output voltage. CHALMERS, Electric Power Engineering, Master s Thesis

32 The previous equations can be rewritten based on duty cycles ( ), i.e. the ratio of conduction times ( ) and total switching period ( ):, 1,2 (3.3), 1 (3.4), (3.5) v 2 d1 d2 1 v reference carrier v 1 t1 t2 t s Fig. 3.2 PWM modulation fundamentals From equation 3.5, it can be concluded that duty cycles can be stated as normalized form of average voltages. For example, duty cycle corresponds to average voltage for mapping,,1. Also, according to equation 3.2 switching times can be calculated and detected by using a timer. In addition, desired output voltage can be compared with a linear ramp wave in the switching period. Thus, if desired voltage is higher than ramp, higher level of output voltage is selected; otherwise lower level is selected. There are different methods to generate modulation signals [27]. All these methods can be presented by similar graphic diagrams: a reference signal is compared to a carrier signal and output state is selected based on which signal is higher at any moment. In selection of carrier and reference signals there are some points which are mentioned below: Carrier signal is usually a symmetric triangular wave, but a saw tooth wave can be used either. Important fact is that the symmetric signal generates fewer harmonic [27]. The reference signal can be continuous or sampled synchronous with carrier signal. The second method usually generates fewer harmonics. Since today digital controllers are used, this method is preferred [28]. Fig. 3.3 shows an example of 2-level PWM. 22 CHALMERS, Electric Power Engineering, Master s Thesis 211

33 (a) (b) Fig. 3.3 (a) Reference signal ( ) and carrier signal ( ), (b) output voltage of 2-level PWM Multilevel PWM Multilevel PWM is a generalized form of the 2-level PWM, described in the previous section, applied to multilevel inverters. In this part, multilevel PWM, its characteristics and advantages are presented. Considering 2-level PWM, the average output voltage ( ) is generated by switching of voltages in the switching cycle ( ). In addition, considering this modulation, to determine switching times, carrier signals are used. According to Fig. 3.2, for each modulation band one carrier signal is needed. Therefore, for an inverter with N output levels, N-1 modulation bands and therefore N-1 carrier signals are needed [28]. Considering 2-level PWM, there are several methods to generate modulation signals. Carrier signals in multilevel applications can be in the form of level-shifted to each other or phase-shifted [23, 27, 3, 31]. In levelshifted PWM, the carrier signals have the same phase and pick-to-pick amplitude and they are in vertical positions to each other. In phase-shifted PWM the phase of each carrier shifts in a proper angle to reduce the harmonic content of the output voltage. The arrangement that is used generally is triangular waveforms which are level-shifted to each other. Some examples of 5-level and 9-level PWM are shown in Fig. 3.4 and Fig In this figures, all the carrier signals have the same frequency, amplitude and phase. CHALMERS, Electric Power Engineering, Master s Thesis

34 (a) (b) Fig level inverter: a) reference and carrier signals, b) output voltage (a) (b) Fig level inverter: a) reference and carrier signals, b) output voltage 24 CHALMERS, Electric Power Engineering, Master s Thesis 211