High-performance Regulator IC Series for PCs 100mA Linear Regulators for Note PC BD35602F/HFN/HFV, BD35603F/HFN/HFV, BD35605F/HFN/HFV

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1 TECHNICAL NOTE High-performance Regulator IC Series for PCs 00mA Linear Regulators for Note PC BD0F/HFN/HFV, BD0F/HFN/HFV, BD0F/HFN/HFV Description BD0 series is a LDO regulator with output current 00mA. The output accuracy is±% of output voltage. BD0 series have some kinds of output voltage line-up and package line-up. Thus, it is used for the wide applications of digital appliances. Over current protection (for protecting the IC destruction by output short circuit), shutdown ON/OFF switch (for setting the circuit current 0μA at shutdown mode), and thermal shutdown circuit (for protecting ICs from heat destruction by over load condition) are all built in. Features ) Output current 00mA ) Output voltage accuracy : ±% ) Built-in Over Current Protection circuit (OCP) ) Built-in Thermal Shut Down circuit (TSD) ) With shut down switch ) Rich package line-up : HVSOF, HSON, SOP Line-up Product name.v.0v.v Package BD0 HFV HVSOF BD0 HFN HSON BD0 F SOP Product name : BD0 a b Symbol a b 0 Output ltage (V) Package 0.V typ. HFV HVSOF 0.0V typ. F SOP 0.V typ. HFN HSON Oct. 00

2 Absolute maximum ratings (Ta= ) Parameter Symbol Limits Unit Power Supply ltage Vcc 0.0 * V ltage V 0.0 V HVSOF 0.0 * Power Dissipation HSON Pd 0 * mw SOP 90 * Operating Temperature Range Topr -0~+00 Storage Temperature Range Tstg -~+0 Junction Temperature Tjmax +0 * Not to exceed Pd * Reduced by.mw for each increase in Ta of over. (when mounted on a board 70.0mm 70mm.mm Glass-epoxy PCB.(copper foil area:00mm )) * Reduced by 0.mW for each increase in Ta of over. (when mounted on a board 70.0mm 70mm.mm Glass-epoxy PCB, layer(copper foil density : 7%)) * Reduced by.mw for each increase in Ta of over.(when mounted on a board 70.0mm 70mm.mm Glass-epoxy PCB.) Operating Conditions (Ta= ) Parameter Symbol Min. Max. Unit Input Power Supply ltage VCC +. V ltage V - V Output Current Io - 00 ma This product should not be used in a radioactive environment. ELECTRICAL CHARACTERISTICS BD0 HFV/HFN/F (Unless otherwise noted, Ta=, =V, Vcc=V) Parameter Symbol Min. Typ. Max. Unit Conditions Output ltage Output ltage (T) 0.99 (T) 0.9 (T) (T) (T).0 (T).0 V V Io=0mA 00mA Tj=0 to 00 Io=0mA 00mA Circuit Current at shutdown mode Isd - 0 μa mode Bias Current Icc μa Output Current Ability Io ma Line Regulation Reg.I - 0 MV Vcc=( +.V ) V, Io=00mA Low ltage V (Low) 0-0. V High ltage V (High). - V Bias Current I μa /

3 Reference Data BD0HFN (Unless otherwise specified, Ta=, =V, Vcc=V) 00mV/div 00mV/div Io 0mA/div Io 0mA/div Fig. Transient Response (0 0mA) Co=μF (0m sec/div) (0μsec/div) Fig. Transient Response (0 0mA) Co=μF (0.msec/div) Fig. Waveform at output start Co=μF VCC 0V/div VCC 0V/div VCC 0V/div (sec/div) Fig. Waveform at output OFF Co=μF Fig. Input sequence Co=μF (msec/div) (msec/div) Fig. Input sequence Co=μF VOUT [V].0.9 Icc [μa] 0 90 Icc [ua] Ta [ ] Fig.7 Ta- (Io=0mA) Ta [ ] Fig. Ta-Icc (V=V) Ta [ ] Fig.9 Ta-Icc (Vcc=V, V=0V) Ien [μa]. 0. [V].00 ISTB [μa] Ta [ ] Io [ma] Vcc [V] Fig.0 Ta-I (Vcc=V, V=V) Fig. Io- (V=V) Fig. Vcc-ISTB /

4 Reference Data BD0HFN (Unless otherwise specified, Ta=, =V, Vcc=V) [V] Vcc [V] Fig. Vcc- /

5 Block Diagram (HSON SOP) Vcc (+.)~V _S OCP SOFT Ceramic Capacitor uf TSD V FB Pin Function Table (HSON SOP) Pin No. Pin Name Pin Function VCC Input ltage Pin N.C. Open Output ltage Pin N.C. Open Pin _S Sense Pin 7 N.C. Open Enable Pin Pin Layout (HSON SOP) VCC N.C 7 N.C _S N.C /

6 Evaluation Board Circuit (=.V) _S C7 Vcc SW C C N.C N.C 7 C V o _S _S C R C C N.C U R V 0 U C R R Gate Vcc Evaluation Board Parts List Designation Value Part No. Company R R R R C C uf CM0B0K0A KYOCERA C C C C uf CMXR0KA KYOCERA C C - - U - BD0XHFN ROHM U /

7 Heat Dissipation Characteristics HVSOF [W] HSON [W].0.0 ().7W Power Dissipation [Pd] ().70W ().0W () 0.W Power Dissipation [Pd] ().W () 0.W Ambient Temperature [Ta] [ ] Ambient Temperature [Ta] [ ] PCB size : 70mm 70mm.mm () layer (Copper foil area : 00mm ) θj-a=7. /W () layer (Copper foil area : 90 mm ) θj-a=9. /W () layer (Copper foil area : 00mm ) θj-a=7. /W () layer (copper foil area : less than 0.%) θj-a=9. /W () layer (copper foil area : less than 7%) θj-a=9. /W () layer (copper foil area : less than %) θj-a=7. /W SOP [mw] 700 () 90mW 00 Power Dissipation [Pd] () 0mW Ambient Temperature [Ta] 0 () 70mm 70mm.mm Glass-epoxy PCB θj-c= /W () With no heat sink θj-a= /W 7/

8 Reference landing pattern MIE E b D e L (Unit : mm) Lead pitch landing pitch landing length landing pitch e MIE l b central pad length central pad pitch D E *It is recommended to design suitable for the actual application. Dimension HSON ±0..0±0. 0.Max..90±0. 7 D 0 X PIN MARK 0. Lot No. (0.) (.) (0.) 0.±0.0 (.) 7 (0.0) (0.0) (0.) (0.) (Unit : mm) /

9 Operation Notes. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added.. Power supply lines Design PCB layout pattern to provide low impedance and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures.. voltage The potential of pin must be minimum potential in all operating conditions.. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 9. Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. TSD on temperature [ C] (typ.) Hysteresis temperature [ C] (typ.) BD0XHFV/HFN/F 7 0. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 9/

10 . Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When > Pin A and > Pin B, the P-N junction operates as a parasitic diode. When > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the (P substrate) voltage to an input pin, should not be used. Resistor Pin A Pin A N N P+ P P + N P substrate Parasitic element Parasitic element Pin B N C Transistor (NPN) P + N P P + N P substrate Parasitic element B E Pin B B C E Parasitic element Other adjacent elements. Ground Wiring Pattern. When using both small signal and large current patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the wiring pattern of any external components, either. 0/

11 Type Designations (Ordering Information) B D 0 X H F V - T R Product Name Package Type E Emboss tape reel opposite draw-out side: pin BD0 BD0 BD0 HFV : HVSOF HFN : HSON F : SOP TR Emboss tape reel opposite draw-out side: pin HVSOF <Dimension>.0±0. (MAX. include BURR).±0..±0. (MAX. include BURR) 0.7Max. S (.) (.) (.) 0. S 0.± (0.) (0.) 0.±0.0 <Tape and Reel information> Tape Embossed carrier tape Quantity 000pcs Direction of feed TR (The direction is the pin of product is at the upper light when you hold reel on the left hand and you pull out the tape on the right hand) (Unit:mm) Reel Pin Direction of feed When you order, please order in times the amount of package quantity. HSON <Dimension>.90± ±0..0±0. 0.Max (0.) (.) (0.) 0.±0.0 (.) (0.0) 7 (0.0) (0.) (0.) <Tape and Reel information> Tape Embossed carrier tape Quantity 000pcs Direction of feed TR (The direction is the pin of product is at the upper light when you hold reel on the left hand and you pull out the tape on the right hand) (Unit:mm) Reel Pin Direction of feed When you order, please order in times the amount of package quantity. SOP <Dimension> <Tape and Reel information> Tape Embossed carrier tape Quantity 00pcs.±0..±0..0±0. 0.Min. Direction of feed E (The direction is the pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 0.±0..± ±0. 0. (Unit:mm) Pin Direction of feed Reel When you order, please order in times the amount of package quantity. /

12 / Catalog No.0TA '0.0 ROHM