VX-1700 Series. HF Multi Mode Mobile Radio Service Manual. Introduction. Contents. For USA Version

Transcription

1 VX-700 Series HF Multi Mode Mobile Radio Service Manual For USA Version 005 VERTEX STANDARD CO., LTD. EC05H5A VERTEX STANDARD CO., LTD Nakameguro, Meguro-Ku, Tokyo 53-86, Japan VERTEX STANDARD US Headquarters 000 Walker Street, Cypress, CA 0630, U.S.A. YAESU EUROPE B.V. P.O. Box 7555, 8 ZN Schiphol, The Netherlands YAESU UK LTD. Unit, Sun Valley Business Park, Winnall Close Winchester, Hampshire, SO3 0LB, U.K. VERTEX STANDARD HK LTD. Unit 5, 0/F., Seaview Centre, - Hoi Bun Road, Kwun Tong, Kowloon, Hong Kong Introduction This manual provides the technical information necessary for servicing the VX-700 HF Transceiver. Servicing this equipment requires expertise in handing surface-mount chip components. Attempts by nonqualified persons to service this equipment may result in permanent damage not covered by the warranty, and may be illegal in some countries. Two PCB layout diagrams are provided for each double-sided board in this transceiver. Each side of the board is referred to by the type of the majority of components installed on that side ( Side A or Side B ). In most cases one side has only chip components (surface-mount devices), and the other has either a mixture of both chip and leaded components (trimmers, coils, electrolytic capacitors, ICs, etc.), or leaded components only. As described in the pages to follow, the advanced microprocessor design of the VX-700 Transceiver allows a complete alignment of this transceiver to be performed without opening the case of the radio; all adjustments can be performed from the front panel, using the Alignment Mode menu. While we believe the information in this manual to be correct, VERTEX STANDARD assumes no liability for damage that may occur as a result of typographical or other errors that may be present. Your cooperation in pointing out any inconsistencies in the technical information would be appreciated. Contents Specifications... Exploded View & Miscellaneous Parts... 3 Block Diagram... 5 Connection Diagram... 6 Circuit Description... 7 Connector Pinout Diagrams... 0 Alignment... ALE- Automatic Link Establishment Unit Installation... CE77 PC Programming Software... Board Units (Schematics, Layouts & Parts) MAIN Unit... PA Unit... 7 PANEL Unit... 8 GPS-INTERFACE Unit MIC Unit... ENC Unit... ALE Unit (Option)... 3

2 Specifications General Receiver Frequency Range: Transmitter Frequency: Emission Modes: Frequency Synthesizer Step: Frequency Stability: Operating Temperature Range: Antenna Impedance: Supply Voltage: Power Consumption: Dimensions (WxHxD): Weight (approx.): Transmitter Power Output: Modulation Types: Spurious Radiation: J3E Carrier Suppression: Undesired Sideband Suppression: J3E Audio Response: Occupied Bandwidth: Microphone Impedance: Receiver 30 khz ~ MHz.600 ~ MHz AA (CW), J3E (LSB/USB), A3E (AM), JB (USB/LSB), 0 Hz, 00 Hz, khz ± ppm (Typical) F ~ F ( 0 ~ +55 Cycle TX:RX = min.: min. 50 Ohms.8 Volts DC ±5%, negative ground 5 ma (Standby).0 A (Receive, no signal).5 A (Receive) A (Transmit, 5 Watts output).5 x 3. x. ( x x 85 mm).5 lbs (.3 kg) 5 Watts (AA, JB, ~ 3. MHz) 00 Watts (AA, JB, ~ MHz) 3 Watts AM Carrier ~ 3. MHz) 5 Watts AM Carrier ~ MHz) J3E: PSN type modulator, A3E: Low-level (early stage) Better than 56 db Better than 50 db below peak output Better than 60 db below peak output Not more than 6 db from 00 Hz ~ 500 Hz AA: less than 0.5 khz J3E: less than 3.0 khz A3E: less than 6.0 khz 00 ~ 0 k Ohms (600 Ohms Nominal) Circuit Type: Double-conversion Superheterodyne Intermediate Frequencies: st: 5.7 MHz, nd: khz Sensitivity: AA/JB/J3E A3E 0. ~ 0.5 MHz 0.5 ~.6 MHz:. µv 8 µv.6 ~ 30 MHz: 0.6 µv µv (AA/JB/J3E/A3E: S/N 0 db) Squelch Sensitivity (AA/JB/J3E): 0. ~ 0.5 MHz 0.5 ~.6 MHz:.5 µv.6 ~ 30 MHz: µv IF Rejection: Better than 80 db Image Rejection: Better than 80 db Selectivity: 6 db 60 db AA(W), JB(W), J3E >. khz <.5 khz AA(N), JB(N) > 500 Hz <.0 khz A3E > 6 khz < 0 khz Audio Output: At least. Watts into 8 0% THD Audio Output Impedance: ~ 6 Ohms (8 Ohms Nominal) Conducted Radiation: Less than 000 µµw Specifications are subject to change without notice or obligation.

3 Exploded View & Miscellaneous Parts RA06500 COVER (TOP) PA UNIT 6 P0035 CONNECTOR (FM-MDR-MI) RA CHASSIS RA HOLDER PLATE (CW) T070A WIRE ASSY RA06600 REFLECTOR SHEET RA07700 DIFFUSER SHEET (BLIND) (pcs) RA INTER CONNECTOR (pcs) G6006 LCD PANEL UNIT MAIN UNIT RA HOLDER PLATE (D-SUB) 0 RA0650A RUBBER KNOB (PW) RA PACKING PAD (CHASSIS) RA07500 FRONT PANEL ASSY RA06600 PACKING PAD (SP) MIC UNIT RA FRONT PLATE (A) M006 SPEAKER RA FRONT PLATE (B) ENC UNIT RA07700 DIFFUSER SHEET (LCD) RA LCD HOLDER RA06600 SPONGE RUBBER (LCD) RA06500 LIGHT GUIDE (LCD) RA COVER (BOTTOM) 8 M0000 FAN GPS INTERFACE UNIT VXSTD P/N A T0375 Q REF. P000 P000 P000 P0005 P0006 P0007 P0008 VXSTD P/N T3550 T3505 T0703 T070 T07 T070 T077A SUPPLIED ACCESSORIES DESCRIPTION MH-3A8J Hand Microphone DC Power Cord Spare Fuse (5 A Blade Type) CONNECTION CABLES QTY. DESCRIPTION Coaxial Cable (J00 J006) Coaxial Cable (J00 J00) 30-pin Flat Cable (J003 J00) -pin Molex (J008 J00) 8-pin Molex (J005 J600) 8-pin Molex (J300 J60) 30-pin Flat Cable (J00 J300) RA06800 KNOB (L) RA0600 KNOB (S) RA060A RUBBER KNOB (KEY) RA0630A RUBBER KNOB (KEY) RA060A RUBBER KNOB (UP/DOWN) R300700A FOOT 7 R300700A FOOT 7 S00003 CASE LEG (FF-003) R05630 STAND S00003 CASE LEG (FF-003) REF VXSTD P/N U U U0000 U U00500 U U U03000 U0600 U0800 U0600 U0800 U30800 U U70000 DESCRIPTION SEMS SCREW SEMS SCREW SEMS SCREW TRUSS HEAD SCREW BINDING HEAD SCREW BINDING HEAD SCREW BINDING HEAD SCREW BINDING HEAD SCREW TAPTITE SCREW TAPTITE SCREW TAPTITE SCREW TAPTITE SCREW TAPTITE SCREW OVAL HEAD SCREW PLAIN WASHER SM3X8NI ASM3X8NI HSMX0NI M3X6 M.6X5NI M3X6NI MX6B MX30(Ni) MX6NI MX8NI M.6X6 M.6X8NI M3X8NI M3X6B FWBSNI Non-designated parts are available only as part of a designated assembly. QTY

4 Exploded View & Miscellaneous Parts Note

5 Block Diagram 5

6 Connection Diagram 6

7 Circuit Description Receive Signal Path Incoming RF signal from the ANT jack is delivered to the PA Unit, and passes through the TX/RX relay RL00 to J006. The RF signal is then applied to J00 on the MAIN Unit, and passed through the limiter circuit consisting of D006, D007, D008, and D00 (all RLS5) to prevent distortion from high RF signal input, and is fed to one of eight band-pass filters which strip away unwanted signals prior to delivery of the incoming signal to the RF amplifiers, Q0 and Q0 (both SK50-K). The amplified RF signal passes through a low-pass filter to the doubly-balanced mixer D03 (HSB88WS), where the RF signal is mixed with the st local signal delivered from buffer amplifier Q0 (SC5), resulting in a 5.7 MHz st IF signal. The 5.7 MHz st IF signal is fed through monolithic crystal filter XF00, which strips away unwanted mixer products, and is amplified by st IF amplifier Q050 (3SK5GR); the st IF signal is then applied to the nd mixer Q05 (RF7), where it is mixed with the 5.5 MHz nd local signal which is divided from 0.5 MHz reference signal delivered from buffer amplifier Q075 (SC7Y), resulting in a khz nd IF signal. The khz nd IF signal is fed through buffer amplifiers Q030 and Q0 (both UPC57G) to the A/D converter Q07 (AK58A), then delivered to the DSP IC Q035 (UPD775), where the khz nd IF signal is demodulated in accordance with the mode selection data from the main CPU Q08 (HD6F). The demodulated signal is delivered to the D/A converter Q08 (AK550VT) which converts the demodulated signal to audio. The audio signal from the D/A converter Q08 (AK550VT) is fed through a low-pass filter at Q036 (UPC57G), which eliminates high-pitched noise on the audio signal, and is fed to the AF mute gate Q0 (SJ5D), then applied to the audio amplifier Q055 (TDA003H). The amplified audio signal is delivered to J300 on the PANEL Unit, then passes through the speaker switch RL300/Q3006 (DTC3ZE) to the internal or external speaker. The DSP IC Q035 (UPD775) outputs AGC data which is proportionate to the received signal strength to the main CPU Q08 (HD6F). The main CPU Q08 (HD6F), in turn, outputs a DC voltage in accordance with the received signal strength. This DC voltage is fed through buffer amplifier Q03 (LM0PW) to RF amplifiers Q0 & Q0 (both SK50) and gate of IF amplifier Q050 (3SK5GR), to reduce their gains when strong signals are present in the receiver passband. Transmit Signal Path The speech audio from the microphone is delivered to J600 on the MIC Unit, then applied to J005 on the MAIN Unit. The speech audio is amplified by Q03- (UPC57G), then passed though the clipper, D0 (MC850), and further amplified by Q03- (UPC57G). The amplified speech audio is fed through the A/D converter Q08 (AK550VT), then delivered to the DSP IC Q035 (UPD775), where the speech audio is modulated in the khz TX st IF signal in accordance with the mode selection data from the main CPU, Q08 (HD6F). The modulated signal is fed through the D/A converter Q07 (AK58A) and buffer amplifier Q03 (UPC57G) to the mixer Q05 (RF7) where the khz TX st IF signal is mixed with st local signal delivered from buffer amplifier Q075 (SC7Y), resulting in a 5.7 MHz IF signal. The resulting 5.7 MHz IF signal is buffered by Q0 (3SK5GR), then delivered to the monolithic crystal filter XF00, which strips away unwanted mixer products, and then is amplified by Q03 (3SK5GR). The amplified IF signal is delivered to doubly-balanced mixer D03 (HSB88WS), where it is mixed with the PLL local signal from the buffer amplifier, Q0 (SC5). The resulting the RF signal at the transmit frequency is fed through a low-pass filter circuit, and then is amplified by Q06 (SC7Y) and buffer amplifier Q05 (SC3357), and then filtered by one of eight band-pass filters to suppress out-of-band responses. The RF signal is then amplified by Q00 (SC5) and delivered to the PA Unit. 7

8 Circuit Description On the PA Unit, the low-level RF signal from the MAIN Unit is amplified by pre-driver Q00 (RD06HHF), push-pull driver Q008/Q00 (both RD6HHF), and push-pull final amplifier Q0/ Q0 (both SD05), which provides up to 0 watts of RF output power. The RF output from the final amplifier is fed through the one of seven low-pass filters, sampling directional coupler T005, and TX/RX relay RL00 before delivery to the antenna jack. The sampling directional coupler senses forward and reverse power output, which is rectified by D07 and D08 (both MA7), respectively, and the DC voltage is then amplified by Q05 (LM0PW) on the PA Unit. The DC voltages derived from forward and reverse power are applied to J003 on the MAIN Unit, and then amplified by Q00 (LM0PW) and Q0 (SC8). The amplified DC voltage is fed back to the nd gate of the 5.75 MHz IF amplifier Q03 (3SK5GR), so that the transmitter s IF gain can be regulated by this sensing of the power output, preventing overdrive or damage caused by transmission into an excessive impedance mismatch at the antenna. PLL Circuit The PLL local signal for the receiver st local and the transmitter final local is generated by one of two VCOs: Q07 or Q073 (both SK0GR) in conjunction with varactor diodes D07, D08, D0, D050, D05, D05, D053, and D05 (all HVU35) on the MAIN Unit. The oscillating frequency is determined primarily by the level of DC voltage applied to the varactor diodes. The VCO output is buffered by Q066 (SK30Y), amplified by Q07 (SC7Y), and band-pass filtered by capacitors C8, C, C7, C00, C0, and C0 and coils L070, L07, L07, and L076. The filtered PLL local signal is fed through buffer amplifiers Q07 (SC7Y), Q08 (SC3356), and Q0 (SC5) to the TX final mixer or RX st mixer D03 (HSB88WS). A portion of the output of buffer amplifier Q066 (SK30Y) is further amplified by Q06 (SC7Y), then delivered to the PLL subsystem IC Q056 (ADF00BRU), which contains a reference divider, serial-to-parallel data latch, programmable divider, phase comparator and a swallow counter. The sample VCO signal is divided by the programmable divider section of the Q056 (ADF00BRU). Meanwhile, the output from the.65 MHz TCXO reference oscillator, X003, is amplified by Q06 (TC7S0FU) and divided by the DDS IC Q060 (AD833BRM) in accordance with the PLL dividing data from the main CPU, Q08 (HD6F), then fed through the buffer amplifiers Q063 (SC7Y) to ceramic filter CF00. The divided and filtered reference signal is applied to the reference divider section of the PLL subsystem IC Q056 (ADF00BRU), where it is divided by 5/ 6 to produce the loop reference. The divided signal from the programmable divider (derived from the VCO), and that derived from the reference oscillator, are applied to the phase detector section of the PLL subsystem IC Q056 (ADF00BRU), which produces a pulsed output with pulse duration depending on the phase difference between the input signals. This pulse train is fed through the loop filter, consisting of resistors R, R3, & R7 and capacitors C78, C8, C8, C08, & C8, then fed back to the VCO varactor diodes D07, D08, D0, D050, D05, D05, D053, and D05 (all HVU35). Changes in the DC voltage applied to these varactor diodes affect the reactance in the tank circuit of VCOs Q07 and Q073 (both SK0GR), changing the oscillating frequency according to the phase difference between the signals derived from the VCO and the TCXO reference oscillator. The VCO is thus phase-locked to the reference frequency standard. A portion of the output of reference signal from TCXO X003 is multiplied by four at Q070 (SC7Y). The resulting 0.5 MHz signal is buffered by Q075 (SC7Y), then applied to a lowpass filter, consisting of capacitors C0, C05, C0, C, and C and coils L075 and L077. The filtered reference signal is applied to the TX st mixer Q05 and RX nd mixer Q05 (both RF7). 8

9 Circuit Description Control Circuit Major frequency control functions such as channel selection, display, and PLL divider control are performed by main CPU Q08 (HD6F) on the MAIN Unit, at the command of the user via the tuning knob and function switches on the front panel. The programmable divider data for the PLL from the main CPU is applied directly to DDS IC Q06 (AD833BRM) and PLL subsystem IC Q056 (ADF00BRU). The Mode selection data from the main CPU is also delivered to DSP IC Q035 (UPD775) to control the various circuits required for the selected mode. The Band selection binary data from the main CPU is decoded (BCD to Decimal) by Q0 (TC08BF). The resulting decimal outputs are level-shifted by Q003 (TD6783AF) to select the active band-pass filter on the MAIN Unit required for the operating frequency. Also, the decimal outputs from Q003 (TD6783AF) are delivered to PA Unit, where they are used to select the active low-pass filter required for the operating frequency. TX/RX Control When the PTT switch is pressed, pin of the main CPU Q08 (HD6F) goes low, which causes pin 60 of the main CPU Q08 (HD6F) to go low. This signal disables the receiver V bus at Q06 (SA60A). At the same time, pin 5 of the main CPU Q08 (HD6F) goes low to activate the transmit V bus at Q08 (SA65). Power Supply & Regulation The +5 V bus for the main CPU Q08 (HD6F) is derived from the.5 V bus via regulator Q0 (BA05FP) on the MAIN Unit. The +8 V bus is derived from the.5 V bus via regulator Q007 (KIA7808API) on the MAIN Unit. A portion of the +8 V bus is regulated by Q008 (L78M05T) for the +5 V bus, and is regulated by Q006 (UPC6) for the +.6 V bus required by the DSP IC Q035 (UPD775GK).

10 Connector Pinout Diagrams MIC Jack GPS Jack (As Viewed From Front Panel) (As Viewed From Rear Panel) P ENB CNTL GND PTT MIC MIC GND + 5V UP DOWN Connected with,,, and. GPS Data Input (+) N/C Connected with,,, and. GPS Data Input (--) Connected with,,, and. Connected with,,, and. Connected with,,, and. NC Pin 3 PTT Open Circuit Voltage: 5 V, Closed Circuit Current: ma ACC Jack TUNE Jack DATA Jack (As Viewed From Rear Panel) (As Viewed From Rear Panel) (As Viewed From Rear Panel) +.8 V OUT TX GND GND BAND DATA A BAND DATA B BAND DATA C BAND DATA D TX-INH EXT ALC Input TX REQ +.8 V OUT TX GND GND RX D TX D TUNER SENSE RESET TX-INH DATA IN GND DATA PTT DCD DATA OUT SQL OUT Pin Pin +.8 V TX GND Max. A This terminal is connected in parallel with the pin of TUNE Jack. Open Collector (Max. 60 V, A) This terminal is connected in parallel with the pin of TUNE Jack. Pin Pin +.8 V TX GND Max. A This terminal is connected in parallel with the pin of ACC Jack. Open Collector (Max. 60 V, A) This terminal is connected in parallel with the pin of ACC Jack. Pin Pin 5 Pin 6 DATA IN DATA OUT SQL OUT 60 kω. 500 kω SQL OPEN: 5 V SQL CLOSE: 0 V Accessory Port (Located on the MAIN Unit) ENCR_TXIN ENCR_RXIN INDICATOR CODE (8) CODE () CODE () CODE () ENCR_RXOUT CLEAR/SCRAMBLE PTT VCC GND ENCR_TXOUT 0