LV8415XA. H bridge 2-channel driver. Blurring correction driver. Overview LV8415XA is dual channel H-bridge driver IC for digital still camera.

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1 Ordering number : ENA2245 LV845XA BiCMOS IC Blurring correction driver H bridge 2channel driver Overview LV845XA is dual channel Hbridge driver IC for digital still camera. Function Actuator driver (saturation drive H bridge) 2channel Hall Amplifier 2channel Constant current hall bias circuit 2channel Generalpurpose amplifier 2channel With builtin for PWM signal generation logic circuit 2channel 8bit DAC for hall bias 2channel 8bit DAC for hall amplifier offset adjustment 2channel Three line serial input Two systems in power supply (VM: for actuator, VCC) With builtin thermal protection circuit With builtin low voltage malfunction prevention circuit WLP32L Specifications Absolute Maximum Ratings at Ta = 25 C Parameter Symbol Conditions Ratings Unit Supply voltage V M max 6 V Supply voltage 2 max 6 V Output peak current I O peak OUT to 2 (t msec, duty 2%) 6 ma Output current I O max OUT to 2 35 ma Hall bias current I HB max 5 ma Allowable power dissipation Pd max On a specified board W Operating temperature Topr 2 to 85 C Storage temperature Tstg 55 to 5 C Specified board: 4.mm 5.mm.8mm, Four layers fiberglass epoxy circuit board. 2 Tjmax=5 C Please design PCB so that internal chip temperature does not exceed 5 C. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ratings at Ta = 25 C Parameter Symbol Conditions Ratings Unit Supply voltage range V M 2.7 to 5.5 V Supply voltage range to 5.5 V Logic input voltage to.3 V ORDERING INFORMATION See detailed ordering and shipping information on page 3 of this data sheet. Semiconductor Components Industries, LLC, 24 January, 24 84NK 234S2 No.A2245/3

2 LV845XA Electrical Characteristics at Ta = 25 C, VCC = 3.3V, VM = 5.V Ratings Parameter Symbol Conditions Unit min typ max Current consumption when I CCO ST = L. μa standing by VM current consumption I M V M = 5.V, ST = H, no load μa current consumption I CC ST = H, no load ma low voltage cutting voltage VTHVCC V Low voltage hysteresis voltage VTHHYS 5 2 mv Thermal shutdown temperature TSD Design guarantee C Thermal hysteresis width ΔTSD Design guarantee C H bridge output (OUT2) Output on resistance Ronu I O = ma, Upperside on resistance.7.98 Ω Rond I O = ma, Underside on resistance.5.7 Ω Output leakage current I O leak μa Diode forward voltage VD ID = ma.7 V Operational amplifier (OPAMP4) Input offset voltage OP_VIO ± ±5 mv Input offset current OP_IIO ±5 ±5 na Input bias current OP_IB 3 25 na Equal phase input voltage range VICM V Equal phase signal removal CMR R L = 2kΩ, VIN = mv(open loop gain) 6 8 db ratio Large amplitude voltage range VG R L = 2kΩ V/mV Output voltage range V O H R L = 2kΩ.2 V V O L.2 V Power supply change removal SVR db ratio Output current (sink/source) OP_IO 2 ma Hall bias (HB2) Output current IHB RHG = kω, VHBIN =.V ma Output saturation voltage VSATHB I HB = ma.2 V Reference voltage Reference voltage VREF V Reference voltage load characteristic VRref I REF = μa V Internal CLK frequency for PWM drive CLK frequency Fclk MHz Control pin (ST, SCLK, DATA, STB) Builtin pulldown resistance Rin 5 2 kω Input current I IN L = V. μa I IN H = 3.3V μa Input L level voltage L. V Input H level voltage H 2.5 V No.A22452/3

3 LV845XA Block Diagram VM.μF low voltage cutting circuit Overheating protection circuit Oscillation circuit bit PWM generation logic Logic circuit H bridge circuit OUTA OUTB OUT2A SCLK DATA Sirial /pararel bit PWM generation logic Logic circuit H bridge circuit OUT2B STB P Standard voltage 8bit DAC 8bit DAC 8bit DAC 8bit DAC ST VOUT4 4 4 VOUT3 3 3 VOUT2 2B 2A 2 HB2 H2 VOUT B A HB H VREF P H H Setpoint signal (3 line sirial) Hall Out (Yaw) LogicChip Hall Out (Pitch) No.A22453/3

4 Package Dimensions unit : mm LV845XA Pin Assignment F E OUT A VM OUT B ST P SCLK OUT 2A DATA OUT 2B STB (NC_ TEST) VREF (NC_TEST) is pin only for the test. Please NC_TESTpin connect line. D 3 4 S C HB 3 4 HB2 Power supply pin pin B H VOUT 3 VOUT VOUT 2 VOUT 4 H2 Output pin Logic control pin A A B 2B 2A 2 Analog control pin Ball side view No.A22454/3

5 LV845XA Pin function Pin No. Pin name Pin function Equivalent Circuit E2 E3 E4 E5 ST SCLK DATA STB Input pin. High level 2V to ( = 3.3V) Low level to.5v ( = 3.3V) IN F F2 F4 F5 E F3 OUTA OUTB OUT2A OUT2B VM P Output pin. (PWM output) VM : POWER Power supply pin. P : POWER pin. VM OT OT PG D D6 C B C6 B6 S HB H HB2 H2 Signal system power supply pin Signal system pin HB, 2 pin Hall bias source pin H, 2 pin Hall bias current setting pin VCC IN H HB A A2 A3 A6 A5 A4 A B 2 2A 2B Hall amplifier input pin Hall amplifier input pin A Hall amplifier input pin B LPF formation pin (The filter is formed for the noise removal.) VCC INB IN INA B3 B4 VOUT VOUT2 Hall amplifier output pin. VOUT : Hall amplifier ch output pin. VOUT2 : Hall amplifier 2ch output pin. OT Continued on next page. No.A22455/3

6 LV845XA Continued from preceding page. Pin No. Pin name Pin function Equivalent Circuit D2 C2 D5 C General purpose amplifier input pin. 3 : 3ch general purpose amplifier input pin 3 : 3ch general purpose amplifier input pin 4 : 4ch general purpose amplifier input pin 4 : 4ch general purpose amplifier input pin IN IN B2 B5 VOUT3 VOUT4 General purpose amplifier output pin. VOUT3 : 3ch general purpose amplifier output pin VOUT4 : 4ch general purpose amplifier output pin OT E6 VREF Internal standard voltage pin /2 output VREF F6 NCTEST N.C. pin TEST pin Please NC_TEST pin connect line. VCC NC No.A22456/3

7 LV845XA 3 line serial communication electrical Characteristics at Ta = 25 C, VCC = 3.3V, VM = 5.V Ratings Parameter Symbol Conditions Unit min typ max Serial data forwarding pin Logic pin input current I IN L =V(SCLK, DATA, STB). μa I IN H =3.3V(SCLK, DATA, STB) 33 5 μa Input H level voltage H SCLK, DATA, STB 2.5 V Input L level voltage L SCLK, DATA, STB. V Minimum SCLK H pulse width T SC H. μs Minimum SCLK L pulse width T SC L. μs STB regulation time Tlat. μs Minimum STB pulse width Tlatw. μs Data setup time Tds. μs Data hold time Tdh. μs maximum CLK frequency Fclk 4 MHz T SC H Fclk T SC L SCLK Tds Tdh DATA A A A2 D D Tlat STB Tlatw Serial data timing condition Serial data input timing chart ST DATA A A A2 A3 D D D2 D3 D4 D5 D6 D7 D8 D9 D D SCLK STB The latch does the state setting data It inputs it from A in order of D. The data transfer is done by the rising edge, and after all data transfers, the latch does all data to SCLK by the STB signal standing up. The STB signal accepts and the internal logic of IC doesn't accept the SCLK signal during "H". No.A22457/3

8 Serial logic map PWMh bridge relation serial map Input LV845XA A A A2 A3 D D D2 D3 D4 D5 D6 D7 D8 D9 D D Setting mode Set content Remarks 5/52 % 5/52 % 2/52 % /52 % ch PWM Duty set % /52 % 2/52 % 59/52 % 5/52 % 5/52 % 5/52 % 5/52 % 2/52 % /52 % 2ch PWM Duty set % /52 % 2/52 % 59/52 % 5/52 % 5/52 % V /255 VREF 2/255 VREF ch hall bias set (8bit DAC) 253/255 VREF 254/255 VREF VREF V /255 VREF 2/255 VREF 2ch hall bias set (8bit DAC) 253/255 VREF 254/255 VREF VREF V /255 ch hall amplifier offset adjustment (8bit DAC) 2/ / /255 V /255 2ch hall amplifier offset adjustment (8bit DAC) 2/ / /255 The PWMhbridge driver's ON/OFF operation is done with the ST pin. % % Reverse Middle point Normal rotation Reverse Middle point Normal rotation No.A22458/3

9 Hall amplifier gain setting range Hall amplifier relation serial map Input A A A2 A3 D D D2 D3 LV845XA Setting mode Hall amplifier magnification ()Inside: Resistance ch hall amplifier gain setting (36k//3.6k) ( 3 Resistance 2 2 (72k//3.6k) Resistance) 4 (44k//3.6k) 5 (8k//3.6k) 6 (26k//3.6k) 7 (252k//3.6k) 9 (324k//3.6k) (36k//3.6k) (396k//3.6k) 2 (432k//3.6K) 4 (54k//3.6k) 5 (54k//3.6k) 6 (57k//3.6k) 7 (62k//3.6k) 9 (684k//3.6k) 2 (72k//3.6k) 2ch hall amplifier gain setting (36k//3.6k) ( 3 Resistance 2 2 (72k//3.6k) Resistance) 4 (44k//3.6k) 5 (8k//3.6k) 6 (26k//3.6k) 7 (252k//3.6k) 9 (324k//3.6k) (36k//3.6k) (396k//3.6k) 2 (432k//3.6K) 4 (54k//3.6k) 5 (54k//3.6k) 6 (57k//3.6k) 7 (62k//3.6k) 9 (684k//3.6k) 2 (72k//3.6k) ch hall amplifier offset (36k//3.6k) resistance / input resistance 2 (72k//3.6k) ( Resistance 2 4 (44k//3.6k) Resistance) 5 (8k//3.6k) 6 (26k//3.6k) 7 (252k//3.6k) 9 (324k//3.6k) (36k//3.6k) (396k//3.6k) 2 (432k//3.6K) 4 (54k//3.6k) 5 (54k//3.6k) 6 (57k//3.6k) 7 (62k//3.6k) 9 (684k//3.6k) 2 (72k//3.6k) 2ch hall amplifier offset (36k//3.6k) resistance / input resistance 2 (72k//3.6k) ( Resistance 2 4 (44k//3.6k) Resistance) 5 (8k//3.6k) 6 (26k//3.6k) 7 (252k//3.6k) 9 (324k//3.6k) (36k//3.6k) (396k//3.6k) 2 (432k//3.6K) 4 (54k//3.6k) 5 (54k//3.6k) 6 (57k//3.6k) 7 (62k//3.6k) 9 (684k//3.6k) 2 (72k//3.6k) No.A22459/3

10 Generalpurpose amplifier ON/OFF setting Input A A A2 A3 D D LV845XA Setting mode Set content Remarks Generalpurpose Standby amplifier Operate PWM circuit accuracy setting Generalpurpose Standby amplifier 2 Operate Input Setting mode Set content Remarks A A A2 A3 D D bit resolution Initial value bit resolution PWM accuracy setting 2bit resolution PWM pulse width of moving ch (X axis side) Input [3:] Moving pulse Setting mode A A A2 A3 D D D2 D3 number ch (X axis) side width of (Initialization) moving Note : pulse = CLK 2ch (Y axis side) Input [7:4] Moving pulse Setting mode A A A2 A3 D4 D5 D6 D7 number 2ch (Y axis) side width of (Initialization) moving Note : pulse = CLK The ON/OFF operation of the hall amplifier and the hall bias is done with the ST pin. Note : An initial value of A to A3 = is a static test mode. Use it specifying data D for one. TEST mode setting Input A A A2 A3 D Setting mode Content Remarks External CLK It uses it by the shipment inspection. NC pin _ TEST mode Internal CLK Internal CLK operation Note : External CLK mode is for the shipment inspection. Use it with internal CLK. Use it after it internal CLK switches because default is external CLK mode. No.A2245/3

11 Hall bias, Offset adjustment circuit configuration Bias adjustment 8bit DAC LV845XA Offset adjustment 8bit DAC H Hall amplifier, Hall bias equivalent circuit About the gain adjustment The resistance ratio of 2 and 3 is adjusted in figure and the gain is set. Refer to the setting to the cereal map. The magnification can be set from ten by 2. About the Offset adjustment The resistance ratio of and 2 is adjusted in figure and the Offset is set. Refer to the setting to the cereal map. The magnification can be set from ten by 2. No.A2245/3

12 LV845XA Note in design Standby function IC becomes a standby state at ST = L, and IC enters the state of operation at ST = H. Moreover, the register in IC is reset as for ST = L at times. Hall bias The constant current output is built into for the hall element drive. The constant current value is set from detection resistance (RHG) connected from the HBIN pin impression voltage and the H pin between. Constant current value (IO) = HBIN voltage Detection resistance HBIN HB I O VCC H H Constant current value (IO) becomes about ma when assuming HBIN pin impressed voltage =.V and detection resistance = kω from the abovementioned calculation type. Moreover, the H pin must connect with the HB pin, and connect the detection resistance of a large value as much as possible when you do not use the hall bias circuit. Operation amplifier Impress the bias to the VIN pin, and compose the buffer by the connection to the VOUT pin in the VIN pin in the operational amplifier not used. V OUT No.A22452/3

13 LV845XA ORDERING INFORMATION Device Package Shipping (Qty / Packing) LV845XAMH WLP32L (2.47mm 2.47mm) (PbFree / Halogen Free) 5 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A22453/3