Revision 01, April PCIe -Over-Fiber. Gen 3 x8 Data Sheet

Transcription

1 Revision 01, April 2018 PCIe -Over-Fiber Gen 3 x8 Data Sheet

2 COPYRIGHTS, TRADEMARKS AND PATENTS Product names used herein are trademarks of their respective owners. All information and material in this publication are property of Samtec, Inc. All related rights are reserved. Samtec, Inc. does not authorize customers to make copies of the content for any use. PCI-SIG, PCI Express and the PCIe design marks are registered trademarks and/or service marks of PCI-SIG. Terms of Use Use of this publication is limited to viewing the pages for evaluation or purchase. No permission is granted to the user to copy, print, distribute, transmit, display in public, or modify the contents of this document in any way. Disclaimer The information in this publication may change without notice. All materials published here are As Is and without implied or express warranties. Samtec, Inc. does not warrant that this publication will be without error, or that defects will be corrected. Samtec, Inc. makes every effort to present our customers an excellent and useful publication, but we do not warrant or represent the use of the materials here in terms of their accuracy, reliability or otherwise. Therefore, you agree that all access and use of this publication s content is at your own risk. NEITHER SAMTEC, INC. NOR ANY PARTY INVOLVED IN CREATING, PRODUCING, OR DELIVERING THIS PUBLICATION SHALL BE LIABLE FOR ANY DIRECT, INCIDENTAL, CONSEQUENTIAL, INDIRECT, OR PUNITIVE DAMAGES ARISING OUT OF YOUR ACCESS, USE OR INABILITY TO ACCESS OR USE THIS PUBLICATION, OR ANY ERRORS OR OMISSIONS IN ITS CONTENT.

3 1 Table of Contents 2 INTRODUCTION Product Features SYSTEM REQUIREMENTS Naming Convention Clock Power Pre-Emphasis Active Equalization Extended Sync Lane Delays and Latency Quiet and Idle Time Detect Adaptor Boards Auxiliary (Sideband) Signals Equivalent Sideband IO Circuit Low Power Sub-states Product Variants INSTALLATION AND OPERATION Connecting the AOC Power Sequence TECHNICAL SPECIFICATIONS REGULATORY AND COMPLIANCE CABLE OPTIONS AND PINOUT G G3 Cable Pinout G G3 Cable Pinout H8G H8G3 Cable Pinout AG AG3 Cable Pinout AG AG3 Cable Pinout Cables with MTP option Ordering Information Mechanical Dimensions PCIEO ADAPTOR BOARDS APPENDIX IDT Switch Compatibility References

4 2 Introduction Samtec Gen 3 Active Optical Cables (AOCs) are designed for PCIe -Over-Fiber extension and expansions systems that need either electrical isolation or to extend the conventional 3 m length offered by copper cables. These pin compatible optical assemblies use the same connector set as traditional PCIe copper cables yet allow the extension of the PCIe bus to beyond 100 m. These cables are optimized for operation at Gen 3 transfer rates when using PLX chipsets. Issues have been identified with Gen 2 switches that do not explicitly follow the requirements of the PCIe Gen 2 specification. Architectures based off these switches may not fully function with these cables and result in links that operate at reduced width and/or rate. Although the form factor was intended for Gen 1 and Gen 2 applications, the delay in the ratification of a Gen 3 external cabling spec led to the industry extending the use of the original solution to Gen 3 applications. As the optical engines used within the AOCs are designed for data rates up to 10G, links more than 100 m are possible based on the signal integrity of the link. Links are limited to 100 m due to protocol limitations that result in reduced bandwidth for long links. 2.1 Product Features Fully Active Optical Cable with Host and Target Cables with MTP option Supports PCIe auxiliary signaling Clock forwarding Up to 100 meters cable length Bit error rate better than Compatible with Dolphin and One Stop Systems (OSS) cards

5 3 System Requirements 3.1 Naming convention The nomenclature for transmitter and receiver pins of the optical cables is discussed in this section. In the electrical domain, TX is an output and RX is an input to the cable. In the Optical domain, TX is an input to the Optical Block and RX is an output of the optical block. The electrical transmitters in Samtec PCIe Active Optical Cables should be connected to the PCIe electrical receivers. The electrical receivers in Samtec PCIe Active Optical Cables should be connected to the PCIe electrical transmitters ELECTRICAL OPTICAL ELECTRICAL PCIe Block PETp PETn CPWRON CPERST# PERp PERn Optical Tx CPWRON CPERST# TX Optical Fiber RX Optical Rx PETp PETn CPWRON CPERST# PCIe Block PERp PERn CPWRON CPERST# CREFCLKp CREFCLKn Termination Resistor CLK OSC CREFCLKp CREFCLKn Optical Rx Optical Fiber Optical Tx PERp PERn CPRSNT# CWAKE# PETp PETn CPRSNT# CWAKE# RX TX PERp PERn CPRSNT# CWAKE# PETp PETn CPRSNT# CWAKE# HOST Sideband Signals High Frequency Signals Figure 1: Interconnect Cable Diagram ENDPOINT

6 3.2 Clock PCIe protocol supports three different clock architectures as shown in Table 3-1. Architecture Description Spread Spectrum Modulation Common Same 100 MHz±300ppm Refclk to transmitter Yes Refclk Rx Data Clocked Rx Separate Refclk and receiver. 100 MHz ±300ppm Refclk to transmitter only. Receiver recovers clock from incoming serial data. This architecture has much tighter jitter requirements than Common Clock Rx architecture. Separate 100 MHz ±300ppm Refclk to Tx and Rx. Also requires much tighter jitter requirements. Yes Supported by Samtec Table 3-1: PCIe Clock Architectures. Constant Frequency Clock (CFC): Active Optical Cables require the use of a constant clocking scheme. The PCIe AOC provides 100 MHz constant clock to the target end of the link as specified in the standard 1. Spread-spectrum Clock (SSC) is used in many systems running PCIe. However, due to signaling technology limitations, the PCIe standard cannot support SSC beyond 7 m of link length. To use a PCIe Active Optical Cable assembly (of any length) in a system that uses SSC clocking, the SSC must be completely disabled 2 at the host. If disabling the SSC is not possible, then a clock isolation. A host adaptor Board will be required to isolate the spread-spectrum clock. Note 1: The clock is not carried across the AOC, hence the Common Refclk architecture cannot be used. Clock from the host is terminated in the Optical transmitter. An option to generate a local clock in target end of the cable is available for use in Endpoint. Note 2: Some motherboard BIOS still allow SSC to be disabled; however, in cases, the disable function does not take effect until after enumeration. In other cases, disabling the SSC will only reduce its amplitude and will not force a change to constant clock operation. If SSC cannot be fully disabled, a host adaptor Boards providing clock isolation must be used. No No Yes Yes

7 PCIEO 3.3 Power Samtec PCIEO cables require 3.3 V ± 5% supplied to both ends of the cable. See chapter 7 for details of the pin assignment in the cabling specification. The PCIe cabling specification specifies power as an option, and therefore, not all PCIe systems may provide power to the connector ports. PWR PWR_RTN PWR PWR_RTN 3.4 Pre-emphasis Figure 2: Filtering capacitors on Power Transmitter pre-emphasis is a SERDES setting used to pre-distort a signal to enable it to run longer distances over traditional copper cables. Optical cables do not have the same loss/degradation mechanisms as copper cables and will accurately represent the electrical signal input at the output. As a result, for best results, the pre-emphasis must be reduced to the minimum required to provide good signal quality at the connector. 3.5 Active equalization Transmitter backchannel tuning has proven to give unreliable results which may require bypass of training phase. It may be necessary to use fixed pre-sets or fixed coefficients. On the receiver side, the optical module is trace length dependent. CTLE values of certain vendors will need to be modified to have a specific start value or locked to a fixed value. Auto equalization needs to be disabled in Gen3 for the above-mentioned reasons. 3.6 Extended Sync Longer optical cables add delay as optics adds latency. Speed of light along with the PCIe architecture currently limiting cable length to 100 m which is significantly greater than electrical cables capability. This has the following effects: Affects ACK/NAK and update-fc for PCIE Reduces throughput These affects are also seen when adding re-timers. 3.7 Lane Delays and Latency The extended sync bit in the link control register must be enabled to allow a minimum of 1,024 TS1 ordered sets to be sent during training. This is partially to compensate for the longer cable lengths used, as well as the methods used, to allow electrical idle over optical links.

8 3.8 Quiet and Idle Time The consequence of ignoring the quick electrical idles results in oscillation in the Optical transmitter because of no incoming modulation of the laser. This causes the need to squelch the receiver output. 3.9 Detect The PCI Express Base Specification defines a Detect circuit as part of the transmit that uses a common mode pulse to determine whether a receiver is connected. As part of the link training process, the PCIe protocol needs to determine the required link width (x1, x4, x8, x16). Each TX end sends a common mode pulse down its 100 ohms differential signal line, and it then measures the response of the decayed signal. Since there is no electrical continuity over the optical fiber, a resistor network on the TX data channel is used to simulate the response of a connected receiver. As a result, care should be taken to ensure that Detect is not used as a mechanism to determine whether a downstream port is connected. RXnP R2 R1 R3 R4 R5 RXnN R6 Figure 3: PCIe Detect Spoofing Circuit Resistors used in the reference circuit are typically size 0201 and 5% tolerance. In certain applications, the common mode pulse AC characteristics may need to be adjusted. Please contact optics@samtec.com for more information. Certain PCIe chipsets have the ability to disable RX detect function, which would eliminate the need for the spoofing circuit. Please contact pcie@samtec.com for more information Adaptor Boards A host adaptor board and a target adaptor Board that are compatible with Active Optical Cables should be installed at each end of the link. Samtec has successfully tested adaptor boards from OSS and Dolphin to support PCIe -Over-Fiber applications enabling links up to 100 m in length. See section 8 on PCIEO Adaptor Boards for more details.

9 3.11 Auxiliary (Sideband) Signals Table 3-2 lists all the sideband signals on the PCIe along with their description. Sidebands don t have dedicated fiber as it is too expensive, so they are multiplexed with traffic. During link training, the sideband signals are in the end state as specified in Table 3-2. Unused sideband signals should be tied to the end state at the source end of the cable. Please contact optics@samtec.com if other sidebands are required. Sideband Signal 1 Function End state Signal Type CREFCLKp, CREFCLKn CPERST# CPWRON CPRSNT# CWAKE# Low voltage differential cable reference clock Cable Reset logically equivalent to system PERST# (platform reset), driven by the upstream subsystem Cable Power On, used to notify slave-type downstream subsystems to turn their main power on or off Cable Present detect to indicated that it s both present and its power is good Cable Wake, driven by a downstream subsystem to reactivate the upstream subsystem - HCSL, LVPECL, etc High High Low High Table 3-2: Sideband Signals LVTTL Pull-up Resistor or LVTTL LVTTL LVTTL Note 1: A no sidebands cable is available as an option for applications where sidebands are not required

10 3.12 Equivalent Sideband IO Circuit The sideband input signals are pulled high using an internal pull-up resistor of kω. Refer to Table 3-3 to determine which sideband signals are inputs to the host end of the cable and which signals are inputs to the target end of the link. The outputs are totem pole outputs and sink about 20 ma of current. Sideband Signal Upstream Pull-up Downstream Pull-up CPWRON Input Yes Output N/A CPERST# Input No Output N/A CPRSNT# Output N/A Input Yes CWAKE# Output N/A Input Yes Table 3-3: Sideband Signal Input - Output Reference Upstream Side Cable Downstream Side CPWRON CPWRON Upstream Side 3.3 V Cable Downstream Side CPERST# CPERST# Figure 4: CPWRNON and CPERST# Sidebands Upstream Side Cable Downstream Side 3.3 V CPRSNT# CPRSNT# Upstream Side Cable Downstream Side 3.3 V CWAKE# CWAKE#

11 3.13 Low Power Sub-states Hot-swapping is not supported with PCIEO products. Please contact for further details. Only L0, L0s and L1 power states are supported as shown in Table 3-4. Link State Description Supported L0 Fully working state Yes Power is on Clocks running L0s Low Power Standby; low resume latency Yes TLP and DLLP transmission is disabled for a Link in L0s L1 Lower power than L0s; longer resume time Yes L2/L3 Ready Staging state in preparation for power removal No (Pseudo-state) L2 Low power sleep state (all clocks, main power off) No L3 Auxiliary power is not available, No wakeup possible No Table 3-4: Link States Figure 5 highlights the legitimate L-state transitions that may occur during link operation. Figure 5: Link Power Management State Flow Diagram

12 3.14 Product Variants Table 3-5 lists the sideband options available with the standard product. Please contact for other options. Variant Clock Present Clock Speed (MHz) Sideband Description -11 Yes 100 MHz Reset and Present Only -12 Yes 100 MHz No sidebands Table 3-5: PCIEO Product Variants

13 4 Installation and Operation 4.1 Connecting the AOC Power to either the adaptor board or motherboard should be in the off state prior to installing the cable assembly (This is to ensure that the link is enumerated and prevent damage to the cable). Refer to the label on the connector shell to identify the host end and the target end. Insert the host end of the assembly into the host card and the target end into the target card ensuring the connector is fully seated and the latching mechanism is fully engaged with the host connector. Incorrectly inserting the host into the target port and vice versa will prevent the cable from operating but should not cause electrical damage to the cable. 4.2 Power Sequence PCIEO Active Optical Cables do not require a special powering sequence. But whether using an Active Optical Cable or a passive copper cable, it is critical that the target be powered prior to the PCIe root complex on the motherboard enumerating (searches and detects) all PCIe devices. There is a short delay between when the host is powered on and enumeration. The target end requires power prior to the host initiating enumeration process, therefore it is a good practice to apply power to the target side of the cable prior to applying power to the host side of the cable.

14 5 Technical Specifications Specifications Symbol Unit Min Max Operating Case TCASE C 0 70 Operating Humidity %RH 5 90* Storage Temperature Range TSTO C Link Distance m 5 100** *Some motherboards may fail to link at distances above 100 m. Contact optics@samtec.com. ** Noncondensing Table 5-1: General Characteristics Specifications Symbol Unit Min Typ. Max Notes Data Rate (channel) GT/s 1 2.5/5.0/ Gen 1 / Gen 2 / Gen 3 Differential Input Amplitude VDI mv Peak-to-peak differential Differential Output VDO mv 719 Peak-to-peak differential Power Supply Voltage VCC1 V Supplied through pins B14, B15 and B16 Power Supply Current ICC1 ma 230 Per connector end Power Consumption PDISS W 0.75* 1.0** Per connector end Bit Error Rate BER For AOC * Nominal supply voltage, room temperature ** Maximum supply voltage Table 5-2: Electrical Characteristics

15 6 Regulatory and Compliance The PCIEO cable was designed to meet the following specifications. Feature Test Method Performance Electrostatic Discharge (ESD) to the electrical contact Electrostatic Discharge (ESD) to module case when installed JEDEC Human Body Model (HBM) (JESD22-A114-B) Variation of IEC kv 15 kv Electromagnetic Interface (EMI) FCC part 15 Class B 1 System dependent EMI Immunity Variation of IEC V/m, MHz Laser eye safety IEC amendment 2 CFR 21 section RoHS compliance RoHS2 2011/65/EU EU Phthalate Directive 2015/863/EU Table 6-1: PCIEO Compliance Class 1 3 EU RoHS2 Annex 4 Note 1: Complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice No. 50, dated June 24, Manufacturing Location: Samtec, 520 Park East Blvd., New Albany, IN Note 2: Caution - Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure. Note 3: Class 1 LASER PRODUCT per IEC Ed. 2 (2007) Note 4: PCIEO products are in compliance with the MCV (Maximum Concentration Value) limits of: all six named RoHS2 substances (Cadmium, Hexavalent Chromium, Lead, Mercury, PBBs, and PBDEs) in accordance with Directive 2011/65/EU (Lead-Compliant by virtue of Annex Exemption 7c) deca-bde in accordance with EU Directive 2005/618/EC. phthalates (DEHPBBP, DBP, and DIBP) in accordance with EU Directive 2015/863/EU.

16 7 Cable Options and Pinout PCIEO x4 transmits data on four independent, full-duplex optical channels and mates to a standard PCIe External Cabling V2.0 x4 port. PCIEO H8 combines a bidirectional x4 channel device in a x8 form factor housing, mates to a standard PCIe x8 port and links as an optical x4 link enabling longer run lengths with existing PCIe Expansion and Extension systems. Each lane is capable of transmitting PCIe signaling at Gen 1 (2.5 GT/s), Gen 2 (5 GT/s) and Gen 3 (8 GT/s). Pre-standard external cabling support for Gen 3 has been successfully demonstrated with third party cards, please contact optics@samtec.com for further details. The electrical to optical conversion circuitry is fully integrated into the connector housing at each end of the assembly, and the optical signal is transmitted over a small diameter optical fiber. The cable auxiliary signals (CPERST# and CPRSNT#) are also transmitted over the optical link. Fiber cable used in the PCIEO AOC is a nonconductive, plenum rated cable with a 3 mm cable diameter and 30 mm minimum bend radius. OM2 fiber is used for cables of length <50 m. OM3 fiber is used for cables of length 50 m or for pigtailed cables. Cable connector attached at each end of the fiber cable has a metal housing that contains the electrical to optical components. The following solutions are available for x8 and x4 configurations of host and target. This would depend on the type of PCIe host and target adaptor boards. x8 Host to x8 Target with an 8G3 cable as a x8 x8 Host to x8 Target with a H8G3 cable as a x4 x8 Host to x4 Target with a 8AG3 cable as a x4 x4 Host to x8 Target with a 4AG3 cable as a x4 x4 Host to x4 Target with a 4G3 cable as a x4 Note: Unlike traditional copper cable, active optical PCIe cables are directional. One end must be connected to the host system (upstream direction), and the other to the target system (downstream direction). The ends of the cable are labeled as host and target and are not interchangeable. The outside surface of the end connector on the cables are conductive for connection to chassis ground. When electrical or clock isolation is used, a separate return path must be provided for the power and sideband signals on the Active Optical Cable. Sideband Signal 3.3 V POWER PWR_RTN SB_RTN Function Power provisioning to allow for active signal conditioning components within the cable assembly Return path optional for 3.3 V power provisioning The sideband return provides a return current path for sideband signals, allowing for power domain isolation between subsystems. Table 7-1: Power and Sideband Returns

17 7.1 4G3 Figure 6 shows the Gen 3 optics cable with a x4 form-factor connector on both ends G3 Cable Pinout Figure 6: Gen 3 x4 Cable Pin Logic Description Pin Logic Description A1 GND Ground B1 GND Ground A2 PETp0 Transmitter Electrical B2 PERp0 Receiver Electrical A3 PETn0 Input Lane 0 B3 PERn0 Output Lane 0 A4 GND Ground B4 GND Ground A5 PETp1 Transmitter Electrical B5 PERp1 Receiver Electrical A6 PETn1 Input Lane 1 B6 PERn1 Output Lane 1 A7 GND Ground B7 GND Ground A8 PETp2 Transmitter Electrical B8 PERp2 Receiver Electrical A9 PETn2 Input Lane 2 B9 PERn2 Output Lane 2 A10 GND Ground B10 GND Ground A11 PETp3 Transmitter Electrical B11 PERp3 Receiver Electrical A12 PETn3 Input Lane 3 B12 PERn3 Output Lane 3 A13 GND Ground B13 GND Ground A14 CREFCLKp Reference Clock B14 PWR 3.3 V Power Supply A15 CREFCLKn B15 PWR A16 GND Ground B16 PWR_RTN Power Supply GND A17 SB_RTN Ground B17 PWR_RTN A18 CPRSNT# Cable Present Sideband B18 CWAKE# Cable Wake Sideband A19 CPWRON Power On Sideband B19 CPERST# Reset Sideband Table 7-2: PCIEO-4G3 Electrical Pinout

18 7.2 8G3 Figure 7 shows the Gen 3 optics cable with a x8 form-factor connector on both ends. Figure 7: Gen 3 x8 Cable

19 G3 Cable Pinout Pin Logic Description Pin Logic Description A1 GND Ground B1 GND Ground A2 PETp0 Transmitter Electrical B2 PERp0 Receiver Electrical A3 PETn0 Input Lane 0 B3 PERn0 Output Lane 0 A4 GND Ground B4 GND Ground A5 PETp1 Transmitter Electrical B5 PERp1 Receiver Electrical A6 PETn1 Input Lane 1 B6 PERn1 Output Lane 1 A7 GND Ground B7 GND Ground A8 PETp2 Transmitter Electrical B8 PERp2 Receiver Electrical A9 PETn2 Input Lane 2 B9 PERn2 Output Lane 2 A10 GND Ground B10 GND Ground A11 PETp3 Transmitter Electrical B11 PERp3 Receiver Electrical A12 PETn3 Input Lane 3 B12 PERn3 Output Lane 3 A13 GND Ground B13 GND Ground A14 CREFCLKp B14 PWR Reference Clock A15 CREFCLKn B15 PWR A16 GND Ground B16 PWR A17 RSVD Not Connected B17 PWR_RTN A18 RSVD Not Connected B18 PWR_RTN A19 SB_RTN Ground B19 PWR_RTN 3.3 V Power Supply Power Supply GND A20 CPRSNT# Cable Present Sideband B20 CWAKE# Cable Wake Sideband A21 CPWRON Power-On Sideband B21 CPERST# Reset Sideband A22 GND Ground B22 GND Ground A23 PETp4 Transmitter Electrical B23 PERp4 Receiver Electrical A24 PETn4 Input Lane 4 B24 PERn4 Output Lane 4 A25 GND Ground B25 GND Ground A26 PETp5 Transmitter Electrical B26 PERp5 Receiver Electrical A27 PETn5 Input Lane5 B27 PERn5 Output Lane 5 A28 GND Ground B28 GND Ground A29 PETp6 Transmitter Electrical B29 PERp6 Receiver Electrical A30 PETn6 Input Lane 6 B30 PERn6 Output Lane 6 A31 GND Ground B31 GND Ground A32 PETp7 Transmitter Electrical B32 PERp0 Receiver Electrical A33 PETn7 Input Lane 7 B33 PERn0 Output Lane 6 A34 GND Ground B34 GND Ground Table 7-3: PCIEO 8G3 Electrical Pin Out

20 7.3 H8G3 Figure 8 shows the Gen 3 optics cable with a x8 form-factor connector on both ends but with only one x4 link activated. Figure 8: Gen 3 x4 Cable with x8 Form Factor

21 7.3.1 H8G3 Cable Pinout Pin Logic Description Pin Logic Description A1 GND Ground B1 GND Ground A2 PETp0 Transmitter Electrical B2 PERp0 Receiver Electrical A3 PETn0 Input Lane 0 B3 PERn0 Output Lane 0 A4 GND Ground B4 GND Ground A5 PETp1 Transmitter Electrical B5 PERp1 Receiver Electrical A6 PETn1 Input Lane 1 B6 PERn1 Output Lane 1 A7 GND Ground B7 GND Ground A8 PETp2 Transmitter Electrical B8 PERp2 Receiver Electrical A9 PETn2 Input Lane 2 B9 PERn2 Output Lane 2 A10 GND Ground B10 GND Ground A11 PETp3 Transmitter Electrical B11 PERp3 Receiver Electrical A12 PETn3 Input Lane 3 B12 PERn3 Output Lane 3 A13 GND Ground B13 GND Ground A14 CREFCLKp B14 PWR Reference Clock A15 CREFCLKn B15 PWR 3.3 V Power Supply A16 GND Ground B16 PWR A17 RSVD Not Connected B17 PWR_RTN A18 RSVD Not Connected B18 PWR_RTN Power Supply GND A19 SB_RTN Ground B19 PWR_RTN A20 CPRSNT# Cable Present Sideband B20 CWAKE# Cable Wake Sideband A21 CPWRON Power-On Sideband B21 CPERST# Reset Sideband A22 GND Ground B22 GND Ground A23 - Not Connected B23 - Not Connected A24 - Not Connected B24 - Not Connected A25 GND Ground B25 GND Ground A26 - Not Connected B26 - Not Connected A27 - Not Connected B27 - Not Connected A28 GND Ground B28 GND Ground A29 - Not Connected B29 - Not Connected A30 - Not Connected B30 - Not Connected A31 GND Ground B31 GND Ground A32 - Not Connected B32 - Not Connected A33 - Not Connected B33 - Not Connected A34 GND Ground B34 GND Ground Table 7-4: PCIEO-H8G3 Electrical Pinout

22 7.4 4AG3 Figure 9 shows the Gen 3 optics cable with a x4 form-factor connector on the host end and a x8 formfactor connector on target end. Figure 9: Gen 3 x4 PCIe Host to x8 PCIe Target

23 AG3 Cable Pinout Pin Logic Description Pin Logic Description A1 GND Ground B1 GND Ground A2 PETp0 Transmitter Electrical B2 PERp0 Receiver Electrical Output A3 PETn0 Input Lane 0 B3 PERn0 Lane 0 A4 GND Ground B4 GND Ground A5 PETp1 Transmitter Electrical B5 PERp1 Receiver Electrical Output A6 PETn1 Input Lane 1 B6 PERn1 Lane 1 A7 GND Ground B7 GND Ground A8 PETp2 Transmitter Electrical B8 PERp2 Receiver Electrical Output A9 PETn2 Input Lane 2 B9 PERn2 Lane 2 A10 GND Ground B10 GND Ground A11 PETp3 Transmitter Electrical B11 PERp3 Receiver Electrical Output A12 PETn3 Input Lane 3 B12 PERn3 Lane 3 A13 GND Ground B13 GND Ground A14 CREFCLKp Reference Clock B14 PWR 3.3 V Power Supply A15 CREFCLKn B15 PWR A16 GND Ground B16 PWR_RTN Power Supply GND A17 SB_RTN Ground B17 PWR_RTN A18 CPRSNT# Cable Present Sideband B18 CWAKE# Cable Wake Sideband A19 CPWRON Power on Sideband B19 CPERST# Reset Sideband B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 Table 7-6: PCIEO-4AG3 Electrical Pinout NO CONNECT

24 7.5 8AG3 Figure 10 shows the Gen 3 optics cable with a x8 form-factor connector on the host end and a x4 formfactor connector on target end. Figure 10: Gen 3 x8 PCIe Host to x4 PCIe Target

25 AG3 Cable Pinout Pin Logic Description Pin Logic Description A1 GND Ground B1 GND Ground A2 PETp0 Transmitter Electrical B2 PERp0 Receiver Electrical A3 PETn0 Input Lane 0 B3 PERn0 Output Lane 0 A4 GND Ground B4 GND Ground A5 PETp1 Transmitter Electrical B5 PERp1 Receiver Electrical A6 PETn1 Input Lane 1 B6 PERn1 Output Lane 1 A7 GND Ground B7 GND Ground A8 PETp2 Transmitter Electrical B8 PERp2 Receiver Electrical A9 PETn2 Input Lane 2 B9 PERn2 Output Lane 2 A10 GND Ground B10 GND Ground A11 PETp3 Transmitter Electrical B11 PERp3 Receiver Electrical A12 PETn3 Input Lane 3 B12 PERn3 Output Lane 3 A13 GND Ground B13 GND Ground A14 CREFCLKp B14 PWR Reference Clock A15 CREFCLKn B15 PWR A16 GND Ground B16 PWR_RTN A17 SB_RTN Ground B17 PWR_RTN A18 CPRSNT# Cable Present Sideband B18 CWAKE# A19 CPWRON Power on Sideband B19 CPERST# 3.3 V Power Supply Power Supply GND Power Supply GND Cable Wake Sideband Reset Sideband A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 NO CONNECT Table 7-7: PCIEO-8AG3 Electrical Pinout

26 7.6 Cables with MTP option All the cables also provide an MTP option. Figure 11 shows MTP option with 4G3 and 8G3 cables. Figure 11: 4G3 and 8G3 Cables with MTP option 7.7 Ordering Information Figure 12: MTP Pin position PCIEO-XXX-XXX.X-XX-X-XX-X SPEED -4G3: X4 GEN 3 -H8G3: X4 GEN 3-8G3: X8 GEN 3-4AG3: X4 TO X8 GEN 3-8AG3: X8 TO X4 GEN 3 ASSEMBLY LENGTH (METERS) 000.5m 100.0m (Longer lengths available as custom parts 0.5m, 1m, 3m STANDARD STOCKED LENGTHS FOR -MTP OPTION (-MTP OPTION ONLY) -M: MALE -F: FEMALE (LEAVE BLANK FOR FULL AOC) END OPTION -01: MTP KEY DOWN (LEAVE BLANK FOR FULL AOC) PRODUCT VARIANT -11: 100 CLOCK FREQUENCY (RESET AND PRESENT SIDEBANDS ONLY) -12: 100 CLOCK FREQUENCY (NO SIDEBANDS) 7.8 Mechanical Dimensions Figure 13: Ordering Information The mechanical dimensions for the x8 and x4 form factor connectors can be obtained from this link: TYPE -H: HOST -T: TARGET (LEAVE BLANK FOR FULL AOC)

27 8 PCIEO Adaptor Boards Samtec has tested PCIe Gen 3 Compliant adaptor boards from OSS and Dolphin to support PCIe -Over- Fiber applications enabling links up to 100 m in length. In addition to supporting optical links, PCIe over copper cable is also supported allowing the use of copper cables for links up to 7 m in length. User manuals and details of the adaptor boards can be obtained from: OSS adaptor boards: Dolphin adaptor boards: Vendor Part Number Description OSS OSS-PCIe-HIB38-x4 1 Gen 3 x4 Host/Target Adaptor board with PCIe switch OSS OSS OSS-PCIe-HIB38-8- DUAL OSS-PCIe-HIB38-8- QUAD Gen 3 x8 adaptor board with two x8 connectors with PLX 8749 Gen 3 x8 adaptor board with four x8 connectors with PLX 8749 Dolphin PXH810 Gen 3 x8 NTB Host Adaptor with Broadcom PLX Switch Dolphin PXH812 Gen 3 Host and Target Adaptor with Broadcom/PLX Switch Note 1: This board has not been tested by Samtec Table 8-1: Compatible adaptor boards OSS Gen3 PCIE Switch-based Cable Adaptor Board Dolphin Gen3 PCIE NTB Host Adaptor Board OSS Gen3 x8 Dual Port Cable Adaptor Board Dolphin Gen3 Host/Target Adaptor Board with PLX Switch Figure 14: Adaptor Boards OSS Gen3 x8 Quard Port Cable Adaptor Board

28 9 Appendix 9.1 IDT Switch Compatibility A. Move to Gen 3 mode by using a H8G3 cable. The H8G3 cable is mechanically compatible with x8 ipass connectors and shells, but it only has 4 active optical links installed. When plugged into a x8 capable system, the system will operate at x4 width. See Section 7.3 for more details about the H8G3 cable. B. Use a Dolphin Interconnect Solutions PXH812 target board with a PLX 1 switch. For more details about compatibility with IDT switch, please contact pcie@samtec.com. Note 1: PLX is a registered trademark of PLX Technology, Inc. 9.2 References PCI Express External Cabling Rev 2.0 PCI Express Base Specification Revision 3.0