TOPSwitch for Telecom and

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1 DC to DC Converters Using TOPSwitch for Telecom and Cablecom pplications Design Note DN-6 Description The TOPSwitch product family provides a cost effective and reliable solution for DC to DC converter applications. The TOP00-TOP0 series of products can be used for input voltages as low as 6VDC and as high as 00VDC in a flyback topology. The 50V breakdown voltage minimizes primary clamping requirements in low voltage applications, reducing cost and simplifying the design. The high level of system integration reduces component count and board space while boosting power density. Because TOPSwitch is very easy to use, design time to production is greatly reduced. Compared to discrete PWM and converter modules, the TOPSwitch solution reduces total cost, component count, size, and weight while also increasing system reliability. Output power ranges for each TOPSwitch as a function of DC input voltage are shown in the table below. For each minimum input voltage value shown, an output power range is given for each TOPSwitch for an expected converter efficiency of approximately 80% with losses split evenly between TOPSwitch and the rest of the circuitry. The transformer should be designed for the indicated reflected voltage V OR and will have maximum duty cycle D MX approaching 6%. Refer to pplication Note N-7 for more information on reflected voltage and transformer design. + DC IN - DRIN SOURCE CONTROL TOPSwitch Figure. Typical pplication. Typical pplication Circuits PI Circuits for three different DC to DC applications are shown using the TOP0. The flyback converter shown in Figure operates directly from the -8 VDC telecom input voltage and delivers up to 5 Watts at a highly accurate +. VDC output voltage. multiple output flyback converter suitable for Cablecom applications is shown in Figure 6. This converter also delivers a total power of 5 Watts while operating from MINIMUM INPUT VOLTGE 8 VDC VDC 6 VDC 8 VDC 60 VDC 7 VDC 90 VDC REFLECTED VOLTGE V OR 0 V 0 V 60 V 80 V *00 V *0 V *50 V TOPSwitch OUTPUT POWER RNGE vs. INPUT VOLTGE FLYBCK CONVERTER OUTPUT POWER RNGE (80% EFFICIENCY) TOP00 TOP0 TOP0 TOP0 TOP W W.-. W.5-.9 W.7-. W 0-.6 W.-.7 W.9-.8 W W W 0-.7 W.-6.5 W.6-9. W 6.0- W 7.0- W W 6.0- W W - W -5 W 0-0 W W -5 W 6- W 9-8 W 0- W -5 W 7-5 W -6 W 6-5 W 0- W 8-7 W 6-5 W -67 W 9-78 W *Some Cablecom pplications require derating of output power due to input withstand voltage requirement. Refer to Cablecom example circuit section. July 996

2 T -8V DC INPUT C 7 µf 00 V U TOP0YI DRIN SOURCE CONTROL C 680 pf 00 V C5 7 µf 0 V R 6. D N8 C 0. µf 6, 8 5, 7 C7 nf 00 V U CNY7- D MBR05 R 5 C9 0. µf C 5600 µf 0 V C µf 0 V D U L. µh 5.5 C S S LMN-. +. V C 000 µf 6. V RTN PI Figure. Simple, Low Cost.V, 5W DC to DC Converter Using the TOP0. rectified quasi-square wave input voltage ranging from 6 VC to 90 VC, typical of a ferro-resonant transformer. The 5V output is tightly regulated and the ±5 VDC outputs are regulated via the transformer secondary turns ratios. Figure 0 shows a ring generator bias flyback converter that operates from the -8 VDC telecom input voltage. This is a primary regulated converter that delivers up to 6 Watts of power at - 55 VDC output voltage. -8V Telecom Converter Figure shows an isolated flyback DC to DC converter using the TOP0 that operates from -6VDC to -70VDC and delivers 5W of power. Output voltage is accurately regulated from the secondary by using an LM-. (U) which is a precision regulator/driver. DC voltage is applied to the primary winding of T as shown in Figure. The other side of the transformer primary is driven by the integrated high voltage MOSFET within the TOP0. The switching frequency of the TOP0 is 00KHz, set by the internal oscillator. With a breakdown voltage of 50V, the clamp circuit to limit the TOPSwitch Drain voltage becomes very simple. C limits the leading-edge voltage spike caused by the transformer leakage inductance. Note that the effectiveness of C to limit the Drain voltage spike is directly related to the value of the transformer leakage inductance. If the leakage inductance is greater than the values specified in Table, a clamp circuit consisting of a Zener diode and ultrafast diode must be used (refer to N-). The.V secondary winding is rectified and filtered by D, C, C, C0 and L to create the. V output voltage. The LM directly senses the output voltage V O and regulates the output voltage by controlling the optocoupler U LED current. C9 rolls off the high frequency gain of the LM for stable operation. R limits the optocoupler LED current and determines the loop gain. The bias winding voltage is rectified and filtered by D and C to generate an approximate V bias voltage to supply the transistor-side of the optocoupler. Optocoupler transistor current is driven into TOPSwitch Control pin to determine the duty cycle. U together with U adjusts the current into the control pin to vary the duty cycle and maintain the output voltage of.v. R and C5 tailor the frequency response of the power supply. Table (at the end of this Design Note) shows electrical specifications and construction details for flyback Transformer T.

3 Performance Data Load regulation is the amount of change in DC output voltage for a given change in output current. Data is taken at nominal input voltage of -8VDC. Output voltage is measured at the power supply output connector. Figure shows that the.v output voltage stays within ± 0.% from 0% load to 00% load. VO (% of Nominal) 0 00 PI Efficiency (%) W Load Maximum Load Input Voltage (VDC) Figure 5. Efficiency vs. Input Voltage. PI Figure. Load Regulation. Load Current () Line regulation is the amount of change in the DC output voltage for a given change in the DC input voltage. Data for line regulation, shown in Figure, is taken at the maximum load condition. Figure shows that the.v output stays within 0.6% from -6VDC input to -70VDC input. VO (% of Nominal) 0 00 Figure. Line Regulation. Maximum Load Load Input Voltage (VDC) PI Efficiency is the ratio of output power to input power. Figure 5 shows curves for efficiencies at two load conditions as a function of input voltage. Worst case efficiency occurs at -6VDC input and maximum load current. t this condition, the output diode average current is approximately.6. Most of the power dissipation loss is due to D (W to W). To improve the overall efficiency, a lower V F (0.V) Schottky diode may be used for D (Motorola, MBR55L or equivalent). Multiple Output Cablecom Power Supply Figure 6 shows a multiple output flyback DC to DC converter using the TOP0. This isolated power supply operates from rectified quasi-square wave input voltage of 6 VC to 90 VC and delivers a total power of 5W. 5VDC output voltage V O is accurately regulated from the secondary by using a TL (U) which is a precision shunt regulator. ±5VDC output voltages are derived from the turns ratio of transformer T (between the 5V windings and the +5V winding) which take into account the voltage drops of rectifiers D, D, and D5. The 5V secondary winding is rectified and filtered by D, C, C, and L to create the 5 V output voltage. The TL directly senses the output voltage, via resistor divider R and R5, and regulates the 5V output voltage by controlling the optocoupler U LED current. C9 rolls off the high frequency gain of the TL for stable operation. R limits the optocoupler LED current and determines the loop gain. The +5V output winding is rectified and filtered by D, C, C, and L, and the -5V output winding is rectified and filtered by D5, C, C5, and L5. The bias winding voltage is rectified and filtered by D and C to generate an approximate V bias voltage to supply the

4 DN-6 transistor side of the optocoupler. Optocoupler transistor current is driven into the TOPSwitch Control pin to determine the duty cycle. U together with U adjusts the current into the control pin to vary the duty cycle and maintain an output voltage of 5V. R and C5 tailor the frequency response of the power supply. In cable distribution, the power supply may have to withstand input voltage as high as 87 VC (quasi-square wave) which will require a Zener diode drain clamp circuit consisting of VR and D. This clamp circuit will limit the leading-edge voltage spike caused by transformer leakage inductance to a safe value below TOPSwitch breakdown rating. Transformer reflected voltage V OR will also have to be reduced to approximately 60V which limits maximum duty cycle D MX to a lower value and decreases converter output power capability by 0% to 5% compared to the values shown in the table at the beginning of this Design Note. Refer to pplication Note N-7 for more information on reflected voltage and transformer design. Table (at the end of this Design Note) shows electrical specifications and construction details for flyback Transformer T. BR C INPUT C µf 00 V U TOP0YI DRIN SOURCE CONTROL VR P6KE0 D UF00 C5 7 µf 0 V D T N8 C 0. µf 5 6 R 6. C7 nf 00 V D UF00 U CNY7- D5 UF00 D MBR75 R 5 C5 0. µf C 8 µf 5 V U C 8 µf 5 V C 00 µf 0 V L µh 50 m L5 µh 50 m L 0 µh C9 0. µf R 0K C 56 µf 5 V C5 56 µf 5 V +5 V -5 V +5 V C 000 µf 0 V RTN TLCLP R5 0K Figure 6. Multiple Output 5V, ±5V, 5 Watt DC to DC Converter Using the TOP0 Operating from Rectified 6 VC to 90 VC Quasi -Square Wave Input Voltage. PI

5 Performance Data Data for load regulation is taken at nominal input voltage of 8VDC. Load for the 5V output is varied from 0.5 to while the load for the 5V is maintained at 0.7. Figure 7 shows that the 5V output voltage stays within 0.% from 0.5 to load. Load cross regulation is the amount of change in the ±5V output voltages for a given change in 5V output current. Figure 7 also show that the cross regulation is 8.% for the +5V output and 7.9% for the -5V output. Data for line regulation, shown in Figure 8, is taken at maximum load condition. Figure 8 shows that the 5V output stays within 0.%, the +5V is within 8.%, and the -5V is within 8.% from 6 VC to 90 VC quasi-square wave input voltage. Figure 9 shows curves for efficiencies at three load conditions as a function of input voltage. Worst case efficiency of 7% occurs at 6 VC quasi-square wave input voltage and maximum load current. VO (% of Nominal) V -5V 5V Input Voltage (VC, Quasi-Square Wave) Figure 8. Line Regulation at 5W Load PI VO (% of Nominal) V V Output Load () PI Efficiency (%) W Load 0W Load 6W Load Input Voltage (VC, Quasi-Square Wave) PI Figure 7. Load Regulation at 8 VDC Input as 5 V Load Varies. Figure 9. Efficiency Curves vs. Input Voltage 5

6 -8V DC INPUT C 7 µf T VR N6000C 0 V D N8 C 0. µf 8 7 D UF00 C 00 µf RTN -55 V U TOP0YI DRIN SOURCE C 680 pf 00 V C5 7 µf 0 V R 0 C7 nf 00 V CONTROL PI Figure 0. Ring Generator Bias Voltage DC to DC Converter Using the TOP0. Telecom Ring Generator Bias Circuit Figure 0 shows the TOP0 used for a ring generator bias application. This is also an isolated flyback DC to DC converter that operates from -6VDC to -60VDC and delivers up to 6W of power at an output voltage of -55 VDC. With a breakdown voltage of 50V, the clamp circuit to limit the TOPSwitch Drain voltage becomes very simple. C limits the leading-edge voltage spike caused by the transformer leakage inductance. Note that the effectiveness of C to limit the Drain voltage spike is directly related to the value of the transformer leakage inductance. If the leakage inductance is greater than the values specified in Table, a clamp circuit consisting of a Zener diode and ultrafast diode must be used (refer to N-). Primary side regulation is used to control the output voltage. Output voltage is indirectly regulated via the primary bias winding. The output voltage is determined by the TOPSwitch Control pin voltage V C (typically 5.8V), Zener voltage V VR, the voltage drops of rectifiers D and D, and the turns ratio between the output winding and bias winding of T. The output winding is rectified and filtered by D and C to create -55 VDC. The bias winding voltage is rectified and filtered by D and C to create a bias winding voltage of 5.8V (the sum of V VR and V C ). C5 is the filter for the Control pin. C5 and R compensate the control loop of the power supply. Table (at the end of this Design Note) shows electrical specifications and construction details for flyback Transformer T. Performance Data Load regulation data is taken at nominal input voltage of -8VDC. Output voltage is measured at the power supply output connector. Figure shows that the output voltage stays within ±.5% of the nominal value from 0% load to 00% load. VO (% of Nominal) Load () Figure. Load Regulation at -8 VDC Input. PI

7 Data for line regulation, shown in Figure, is taken at maximum load. Figure shows that the output voltage stays within % of the nominal value from -6VDC input to -60VDC input. Figure shows curves for efficiencies for three load conditions as a function of input voltage. Worst case efficiency occurs at -6VDC input and maximum load current. Data shows that efficiency measurements are greater than 8%. VO (% of Nominal) 0 00 PI PI Input Voltage (VDC) Efficiency (%) Figure. Line Regulation at Maximum Load 0 Maximum Load 0 W Load 5.5W Load Input Voltage (VDC) Figure. Efficiency vs. Input Voltage 7

8 V+ 8 node 50 T of #9 Drain node T of #9 Pri Rtn T of # Sec Rtn node T of # Sec Rtn MTERIL Item 5 6 Description Core: EE9, PC0EE9-Z,TDK Gapped for L of 7 nh/t Bobbin: BE-9-8CPH TDK Magnet Wire: #9 WG Heavy Nyleze Magnet Wire: # WG Heavy Nyleze Tape: M 98 Polyester Film (white) 0.8 inches wide by. mils thick Varnish ELECTRICL SPECIFICTIONS Electrical Strength Creepage Primary Inductance Resonant Frequency Primary Leakage Inductance 60 Hz, minute, from pins - to pins 7-8 Between pins - and pins 5-8 ll windings open ll windings open Pins 5-8 shorted 500 VC.5 mm (min) 80µH MHz (min) 5 µh PI Table. Telecom. V Output Transformer 8

9 SECONDRY 5,7 6,8 TPE TPE BIS PRIMRY WINDING INSTRUCTIONS Two-Layer Primary Basic Insulation Bias Winding Basic Insulation Secondary Winding Outer Insulation Final ssembly Start at pin. Wind 5 turns of #9 (item ) from left to right. Wind in a single layer. pply layer of tape, item 5, for basic insulation. Wind remaining 5 turns in the next layer from right to left. Finish on pin. layer of tape (item 5) for basic insulation. Start at pin. Wind turns #9 (item ) from left to right. Wind uniformly, in a single layer, across entire width of bobbin. Finish on pin. layers of tape (item 5) for basic insulation. Start at pins 6 and 8. Bifilar wind turns of # (item ) from left to right. Wind uniformly, in a single layer, across entire width of bobbin. Finish on pins 5 and 7, respectively. layer of tape (item 5) for insulation. ssemble and secure core halves. Impregnate uniformly with varnish (item 6). PI Table. Telecom. V Output Transformer (Continued) 9

10 V+ 7 T of # node T of #8 Rtn T of #8 Cathode Drain node 9 T of #8 Pri Rtn node T x of # Rtn MTERIL Item 5 6 Description Core: EE9, PC0EE9/7/5-Z,TDK Gapped for L of 89 nh/t Bobbin: YW8, EL9, 0 Pin (YIH HW Enterprises) Magnet Wire: #8 WG Heavy Nyleze Magnet Wire: # WG Heavy Nyleze Tape: M 98 Polyester Film (white) 0.85 inches wide by. mils thick Varnish ELECTRICL SPECIFICTIONS Electrical Strength Creepage Primary Inductance Resonant Frequency Primary Leakage Inductance 60 Hz, minute, from pins -5 to pins 6-0 Between pins -5 and pins 6-0 ll windings open ll windings open Pins 6-0 shorted 500 VC.5 mm (min) 5 µh MHz (min) 5 µh PI Table. Multi Output Transformer 0

11 SECONDRY TPE TPE 5 BIS PRIMRY WINDING INSTRUCTIONS Two-Layer Primary Basic Insulation Bias Winding Basic Insulation Bifilar 5V Winding Bifilar ±5V Winding Outer Insulation Final ssembly Start at pin. Wind 9 turns of #8 (item ) from left to right. Wind in a single layer. pply layer of tape, item 5, for basic insulation. Wind remaining 8 turns in the next layer from right to left. Finish on pin. layer of tape (item 5) for basic insulation. Start at pin. Wind 9 turns #8 (item ) from left to right. Wind uniformly, in a single layer, across entire width of bobbin. Finish on pin 5. layers of tape (item 5) for basic insulation. Start at pin 7. Wind bifilar T (item ) from left to right. Wind uniformly, in a single layer, across entire width of bobbin. Finish on pin 6. Start at pins 0 and 9. Wind bifilar T (item ) from left to right. Wind uniformly, in a single layer, across entire width of bobbin. Finish on pins 9 and 8, respectively. layers of tape (item 5) for insulation. ssemble and secure core halves. Impregnate uniformly with varnish (item 6). PI Table. Multi Output Transformer (Continued)

12 V+ 8 node T of #6 8 T of #7 Drain node T of #6 7-55V DC Pri Rtn MTERIL Item 5 6 Description Core: EE, PC0EE-Z,TDK Gapped for L of 70 nh/t Bobbin: BE--8CP TDK Magnet Wire: #6 WG Heavy Nyleze Magnet Wire: #7 WG Heavy Nyleze Tape: M 98 Polyester Film (white) 0.8 inches wide by. mils thick Varnish ELECTRICL SPECIFICTIONS Electrical Strength Creepage Primary Inductance Resonant Frequency Primary Leakage Inductance 60 Hz, minute, from pins - to pins 7-8 Between pins - and pins 7-8 ll windings open ll windings open Pins 7-8 shorted 500 VC.5 mm (min) 80 µh MHz (min) 5 µh PI Table. Ring Generator Bias Transformer

13 7 SECONDRY 8 BIS TPE TPE PRIMRY WINDING INSTRUCTIONS Double Primary Layer Basic Insulation Double Secondary Layer Basic Insulation Bias Winding Outer Insulation Final ssembly Start at pin. Wind 7 turns of #6 (item ) from left to right. Wind in a single layer. pply layer of tape, item 5, for basic insulation. Wind remaining 6 turns in the next layer from right to left. Finish on pin. layers of tape (item 5) for basic insulation. Start at pin 8. Wind 9 turns #7 (item ) from left to right. Wind in a single layer. pply layer of tape (item 5) for basic insulation. Wind remaining 9 turns in the next layer from right to left. Finish on pin 7. layers of tape (item 5) for basic insulation. Start at pin. Wind turns of #6 (item ) from left to right. Wind uniformly, in a single layer, across entire width of bobbin. Finish on pin. layers of tape (item 5) for insulation. ssemble and secure core halves. Impregnate uniformly with varnish (item 6). Table. Ring Generator Bias Transformer (Continued) PI

14 NOTES

15 NOTES 5

16 Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc. Copyright 99, Power Integrations, Inc. 77 N. Mathilda venue, Sunnyvale, C 9086 WORLD HEDQURTERS Power Integrations, Inc. 77 N. Mathilda venue Sunnyvale, C 9086 US Main: Customer Service: Phone: Fax: JPN Power Integrations, Inc. Keihin-Tatemono st Bldg. -0 Shin-Yokohama -Chome.Kohoku-ku Yokohama-shi, Kanagawa Japan Phone: 8 (0) Fax: 8 (0) MERICS For Your Nearest Sales/Rep Office Please Contact Customer Service Phone: Fax: SI & OCENI For Your Nearest Sales/Rep Office Please Contact Customer Service Phone: Fax: EUROPE & FRIC Power Integrations (Europe) Ltd. Mountbatten House Fairacres Windsor SL LE United Kingdom Phone: (0) Fax: (0) PPLICTIONS HOTLINE World Wide PPLICTIONS FX mericas Europe/frica (0) Japan 8 (0) sia/oceania

Design Example Report

Design Example Report Title Specification Application Author Document Number 2.2W Charger using LNK501P Input: 198 253 VAC Output: 3.6V / 0.6 A Cell Phone Charger Applications Department DER-15 Date February