QinetiQ Q20 High Sensitivity GPS Receiver. Specification. QinetiQ Proprietary QINETIQ/FST/I&C/SPEC044447/ th October 2005

Transcription

1 QinetiQ Q20 High Sensitivity GPS Receiver Specification QINETIQ/FST/I&C/SPEC044447/ th October 2005 Any person finding this document should hand it or post it to the Group Security Manager, QinetiQ Limited, Cody Technology Park, Farnborough, Hampshire GU14 0LX, with particulars of how and where found. Requests for wider use or release must be sought from: Intellectual Property Division QinetiQ Ltd Cody Technology Park Farnborough Hampshire GU14 0LX Copyright QinetiQ ltd 2005

2 Administration page Record of changes Issue Date Detail of Changes th November 2004 First Formal Release th May 2005 Updated pin-out descriptions Updated minimum application circuit diagram th May 2005 Updated for Version 2 software performance improvements 'This document is supplied in confidence to the recipient for information purposes only and is not to be released outside the recipient's organisation without the prior written permission of QinetiQ. Requests for permission for wider use or release should be made to Intellectual Property Department, QinetiQ. QinetiQ accepts no responsibility for any claims or damages arising out of the use of this document, or from the use of modules based on this document, including but not limited to claims in respect of loss or damage based on infringement of patents, copyright or other intellectual property rights. QinetiQ makes no warranties, either expressed or implied, with respect to the information and specifications contained in this document and the recipient accepts full responsibility for the use to which such information is put'. Although every effort has been made to ensure the details are correct at the time of issue, QinetiQ reserves the right to change this specification without notice. QINETIQ/FST/I&C/SPEC044447/2.0 Page 2

3 List of contents 1 Introduction Technical Assistance Your Comments 5 2 Q20 Module Functional Description General Description Features Block Schematic Front End Filter and Low Noise Amplifier Radio Frequency Front End Baseband Processor Signal Processing Navigation Solution Real Time Clock & EEPROM Input / Output Reset Logic Operating Modes Operation on power up Operation on power interrupt Power Consumption Protocols 11 3 Performance Specification 12 4 Mechanical Specification Dimensions Specification PCB Outline Recommended Layout Footprint Electrical Connections 15 5 Electrical Specification Absolute Maximum Ratings Operating Conditions Q20 Module Pin I/O Details RF Input Parameters 17 6 Interfaces Outline Description Serial Interface Reserved Detailed Pin Description Pin 1 ntrst Pin 2 nreset Pin 3 COM 1 RX 19 QINETIQ/FST/I&C/SPEC044447/2.0 Page 3

4 6.2.4 Pin 4 COM 1 TX Pin 5 COM 2 RX Pin 6 COM 2 TX Pin 7 COM 3 RX Pin 8 COM 3 TX Pin 9 MODE Pin 10 EXT CLOCK Pin 11 Reserved Pin 12 Reserved Pin 13 VBATT Pin 14 1V8_Test Pin 15 DIG_GND Pin 16 VCC Pin 17 FREQ OUT Pin 18 TIMEMARK Pin 19 Reserved Pin 20 LED Pin 21 LED Pin 22 LED Pin 23 TDI Pin 24 TCK Pin 25 JTAGSEL Pin 26 TDO Pin 27 TMS Pin 28 2V8_Test Pin 29 RF_GND Pin 30 RF_GND Pin 31 RF_IN Pin 32 RF_GND 21 7 References 22 8 Abbreviations 22 9 Glossary 23 A Q20 Module Minimum Application Circuit 24 A.1 Passive Antenna 24 A.2 Active Antenna 25 QINETIQ/FST/I&C/SPEC044447/2.0 Page 4

5 1 Introduction Thank you for your interest in the QinetiQ Q20 High Sensitivity GPS Receiver. The Q20 represents the state of the art in GPS receiver technology. The Q20 s high sensitivity enables GPS positioning in locations where other receivers fail to operate and therefore brings the benefits of GPS to a host of new applications. This document describes the features and specifications of the QinetiQ Q20 GPS module, a high-sensitivity, low power, GPS receiver macro-component. Figure 1: Q20 High Sensitivity GPS Receiver Module The document details the mechanical and electrical characteristics of the Q20 module, and is intended to aid the integration of the module into higher-level systems and products. 1.1 Technical Assistance If you are experiencing difficulties integrating the Q20 module which cannot be resolved using the documentation supplied, please us at the following address and we will do our best to assist you as quickly as possible. Send an to: GPSSupport@qinetiq.com 1.2 Your Comments We are continually trying to improve our products and services and we value your feedback. If you have any suggestions or comments please forward them to the following address and we will endeavour to take account of them in our future products and updates. Send an to: GPSSales@qinetiq.com QINETIQ/FST/I&C/SPEC044447/2.0 Page 5

6 2 Q20 Module Functional Description 2.1 General Description The QinetiQ Q20 GPS Module is a high sensitivity, ultra-compact GPS receiver offering state of the art indoor and outdoor positioning capability. The high sensitivity of the Q20 module enables operation in environments where conventional GPS receiver technology cannot function, e.g. urban canyons, under wet foliage and indoors. The Q20 s novel architecture also enables extremely rapid Time-To-First-Fix (TTFF) in a conventional signal environment. The module is based on a state of the art QinetiQ GPS baseband processor, which provides rapid signal acquisition and very low signal strength tracking capability. The QinetiQ baseband processor provides digital interfaces for access to the positioning output and control of the module functions. Embedded in the processor are highly reliable software and navigation library functions. These have been optimised for execution on the baseband s high performance ARM966 microprocessor. The baseband processor is integrated with a low noise RF front end to give unprecedented sensitivity in such a small receiver module. The RF front end and associated filtering provide effective protection from out of band interference. The module also contains a real time clock that can be battery backed and a low drift temperature compensated crystal oscillator, optionally an external reference oscillator can be used instead 1. There is onboard memory for storing all the necessary receiver software plus data that can assist acquisition: time, date, frequency bias, last known position, ephemeris and almanac. 2.2 Features The Q20 offers the following features: 12 channels to provide an All Satellites in View tracking capability Fast Time-To-First-Fix (TTFF) High sensitivity with or without Network Assistance Almanac and Ephemeris data demodulation at extremely low signal levels 1 Hz position and velocity updates 3 Serial Ports 1 Pulse Per Second (1 PPS) timing output Operating Voltage 3.0 to 3.6 V Embedded ARM966 processor Wide operating temperature range: -30 C to +80 C Small size: 22.0 mm x 26.5 mm x 3.3 mm (including RF shield) Weight 2.5 g 1 Build-time option QINETIQ/FST/I&C/SPEC044447/2.0 Page 6

7 2.3 Block Schematic The Q20 module is a complete GPS receiver requiring a minimum of external components and connections to operate. The user can be up and running simply by connecting power, an antenna and a device to the serial port capable of interpreting standard NMEA data messages. A demonstration kit is available to make the process even easier. This includes a boxed Q20 with rechargeable battery and mains power supply together with all the cables and software required to start exploring the benefits of high sensitivity GPS. The main functional components within the Q20 are shown in figure 2 and described in detail below. IF Filter TCXO Digital Power I 2 C RTC, Reset Logic E 2 PROM VCC VBATT External Antenna RF Front End LNA Front End Filter RF PSU Crystal Baseband Processor 3 3 External Reset Mode External Clock 1 PPS Freq Out Serial I/O GPS Status Figure 2: Q20 Block Schematic 2.4 Front End Filter and Low Noise Amplifier GPS signals from the antenna first encounter a high performance ceramic front-end filter which effectively removes any unwanted signals (i.e. signals outside the L1, C/A-code GPS bandwidth). After filtering the signals are amplified by an onboard Low Noise Amplifier (LNA) prior to input into the RF-front end. 2.5 Radio Frequency Front End The RF Front End used in the Q20 is a single Silicon-Germanium BiCMOS device. It amplifies the very weak GPS signals to a magnitude useable by the digital circuits. To do this it requires a power gain in excess 140 db. Such a high gain, applied to all the signals incident at the antenna, would result in very large signals in the RF/IF system, so it is also necessary to incorporate filters to exclude unwanted signals outside the GPS bandwidth. The RF section of the receiver down-converts the GPS signals to an Intermediate Frequency (IF) which the baseband processor s digital circuits can process. The RF section of the receiver is driven by the reference oscillator. Control of the RF device is via a digital 4-wire Serial Peripheral Interface (SPI). This interface provides control of power to the RF circuits, Automatic Gain Control (AGC), QINETIQ/FST/I&C/SPEC044447/2.0 Page 7

8 synthesiser dividers, and Analogue to Digital (A-to-D) thresholds. Adjustable A-to-D thresholds are helpful in improving signal-to-noise ratios when operating in interference environments. 2.6 Baseband Processor Signal Processing The IF signal, received at the RF/baseband interface, is a digitised composite of the signal from all received GPS satellites. It retains the full bandwidth of the GPS signal. The baseband process separates out the individual satellite signals, by correlation with their individual Pseudo Random Noise (PRN) codes, removes any residual IF and Doppler frequency components and then provides further filtering to a rate at which software techniques become more appropriate. Signal acquisition is implemented using a parallel search strategy in both code and frequency. In code space the baseband processor provides many more parallel correlators than conventional GPS receivers. Further parallel processing is provided for a search in the frequency domain, by using a powerful dedicated Fast Fourier Transform (FFT) engine implemented in hardware. The reference oscillator provides the digital clock signal to the baseband processor Navigation Solution The baseband processor contains an embedded on-board ARM966 processor, which uses the raw measurements provided by the dedicated signal processing to calculate an accurate navigation solution (position, velocity and time) using an advanced Kalman filter. The processor also executes proprietary algorithms to reject interference and reduce the effects of multipath Real Time Clock & EEPROM The Q20 module contains a Real Time Clock (RTC), reset controller and 32K x 8 Bits of EEPROM connected to the baseband processor on a 2-wire I 2 C bus. The RTC can be battery backed by the user, thus remaining active when primary power is removed from the Q20 module. This will enable the module to quickly establish which satellites are in view upon switch on for faster starts from power on. On power down, the EEPROM is used to store useful information including an Almanac, Ephemeris, last known position and frequency bias. This information, in conjunction with date and time information from the RTC, enables the Q20 module to rapidly acquire GPS satellite signals from switch-on. The Q20 module software provides EEPROM management. For example Write cycles are managed to provide an EEPROM lifetime of more than 10 years. QINETIQ/FST/I&C/SPEC044447/2.0 Page 8

9 2.6.4 Input / Output The module hardware provides various Input / Output (I/O) options for transferring information and data to / from the module. Three serial I/O ports at CMOS level (3V0-3V3), Baud rate configurable in software. Default settings are as follows: COM 1: 4800 Baud, no parity, 1 stop bit NMEA (GGA, GLL, GSA, GSV, RMC) output QinetiQ proprietary ASCII commands in and out QinetiQ proprietary network assist COM 2: Baud, no parity, 1 stop bit NMEA (GGA, GLL, GSA, GSV, RMC) output QinetiQ proprietary ASCII commands in and out QinetiQ proprietary network assist COM 3: 4800 Baud, no parity, 1 stop bit NMEA (GGA, GLL, GSA, GSV, RMC) output QinetiQ proprietary ASCII commands in and out QinetiQ proprietary network assist Please note that full network assistance data may take a long time to download if used at low Baud rates. One Pulse Per Second (1 PPS) precision timing output Frequency out - reserved for timing application software. Mode reserved for High Dynamic software Three GPS status outputs (to drive LEDs) as follows LED 1: On when there is no fix and the Q20 is searching for satellites LED 2: Pulses high for each satellite tracked without ephemeris data LED 3: Pulses high for each satellite tracked with ephemeris data External reset input External clock input. This option (specified at build time) enables the use of an external reference oscillator in place of the on-board TCXO Reset Logic An onboard reset control is provided to perform a controlled reset of the device under brown-out conditions. Reset occurs at 2.85 V ±100 mv. QINETIQ/FST/I&C/SPEC044447/2.0 Page 9

10 2.7 Operating Modes Operating Mode Description Normal Sleep Auto Software Update In normal mode selected peripherals are enabled and the system runs at its designated operating frequency. The Q20 acquires and tracks satellites and generates a navigation solution. In this mode, the Q20 offers high performance, but consumes the most power. In sleep mode, the Phase Lock Loop (PLL) output is dropped to a very low level. GPS functionality is not available. UART functionality is significantly decreased, but it is still be possible for serial activity to cause a UART to generate an Interrupt Request (IRQ). Sleep mode is entered from normal mode under software control, and is exited under external command on COM 1 (any activity on COM1). The PLL will also return to its previous mode on the assertion of the IRQ by external stimulus (i.e. by asserting the nreset discrete). Place-holder In software update mode no navigation solution is generated. The Q20 module supports software upgrade from any serial port.! Note: Software update will only operate at 38,400 BAUD. Software Upgrade Mode is entered on software command or at start-up by holding the COM 1 RX pin low. Software Upgrade Mode is exited on receipt of the appropriate software command or by resetting the module. Software commands and protocols are detailed in the Q20 GPS Receiver Module Interface Control Document.[1] Table 1 - Q20 Module Operating Modes Time to switch between sleep and normal modes is less than 5 seconds. 2.8 Operation on power up On application of power the Q20 module will perform a power-on reset and transition to the normal mode of operation. 2.9 Operation on power interrupt The Q20 module contains a reset controller. In the condition of power interrupt or power brown-out it will perform a reset and transition to the normal mode of operation. Reset occurs at 2.85V ±100 mv. QINETIQ/FST/I&C/SPEC044447/2.0 Page 10

11 2.10 Power Consumption The Q20 power consumption can be minimised by intelligently switching between operating modes. The Q20 is able to obtain a fix much faster than conventional GPS receivers and so is ideally suited to intermittent operation. Mode Current Consumption (ma) Fix 145 Sleep 10 Software Update 200 Max consumption during sequence Table 2 - Q20 Module Power Consumption 2.11 Protocols The Q20 supports several different serial protocols; these are described in the Q20 GPS Receiver Module Interface Control Document.[1] Protocol Type Runs On NMEA QinetiQ ASCII command set Output, ASCII, 0183, V2.1 and V2.2 Input / output, ASCII, QinetiQ proprietary COM 1, COM 2, COM 3 COM 1, COM 2, COM 3 Network Assist Input, QinetiQ proprietary COM 1, COM 2, COM 3 Table 3 - Q20 Module Serial Data Protocols! Note Individual messages may be switched on / off under software control. This is on a per-module basis, i.e. a message disabled on one COM port will be disabled on both other COM ports. QINETIQ/FST/I&C/SPEC044447/2.0 Page 11

12 3 Performance Specification Receiver Type 12 parallel channel C/A L 1 ( MHz) Performance RF Reception Sensitivity -185 dbw acquisition Signal Acquisition Hot Warm Cold Reacquisition -189 dbw tracking <1 sec <38 sec <45 sec <0.5 sec Physical Module dimensions 22.0mm (D) x 26.5mm (W) x 3.3mm (H) Supply voltage 3.0V to 3.6V Operating / Storage Temp -30 C to + 80 C / -55 C to +85 C Max Velocity / Altitude 515 ms -1 / 18,000m Max Acceleration / Jerk 4g / 1 gs -1 Accuracy Position: Outdoor/Indoor <5m / <50m typical 3V15 Interfaces Future Options Velocity <0.05ms -1 Serial Timing GPS status External Reset 30 mw (sleep) 435 mw (normal) RTC only Mode < 15 μw 3 UART ports 1 PPS ±25 ns accuracy 3 GPS status outputs (to drive LEDs) Active low Protocols NMEA 0183 USB I 2 C GPIO Reference frequency output Event In External Interrupt ASCII Network Assist Future Firmware Upgrade Future Firmware Upgrade Future Firmware Upgrade Future Firmware Upgrade Future Firmware Upgrade Future Firmware Upgrade Table 4 - Q20 Module Performance Specification QINETIQ/FST/I&C/SPEC044447/2.0 Page 12

13 4 Mechanical Specification 4.1 Dimensions / -0.2 mm FREQ OUT VCC TIMEMARK DIG_GND Reserved V8_TEST LED VBATT LED Reserved LED Reserved TDI 23 TCK 24 JTAGSEL 25 TDO 26 TMS EXT CLOCK 9 MODE 8 COM 3 TX 7 COM 3 RX 6 COM 2 TX ± 0.1 mm / -0.2 mm 2V8_TEST 28 5 COM 2 RX RF_GND 29 4 COM 1 TX RF_GND 30 3 COM 1 RX RF_IN 31 2 nreset RF_GND 32 1 ntrst 0.86mm 0.87mm ± 0.1 mm Shielding Can PCB Figure 3 - Q20 Module Mechanical Outline 0.38mm 3.22 ± 0.1 mm 4.2 Specification Parameter Specification Tolerance Unit Length / -0.2 mm Width / -0.2 mm Thickness 3.22 ±0.1 mm Pitch connector pad 1.35 mm Width connector pad 0.88 mm Weight 2.5 grams Table 5 - Q20 Module Mechanical Specification QINETIQ/FST/I&C/SPEC044447/2.0 Page 13

14 4.3 PCB Outline Figure 4 Q20 PCB Outline 4.4 Recommended Layout Footprint Figure 5 Q20 Recommended PCB Layout QINETIQ/FST/I&C/SPEC044447/2.0 Page 14

15 4.5 Electrical Connections Pin Number Name Type Description 1 ntrst JTAG Reset 2 nreset External Reset 3 COM 1 RX I COM 1 Serial Data Input 4 COM 1 TX O COM 1 Serial Data Output 5 COM 2 RX I COM 2 Serial Data Input 6 COM 2 TX O COM 2 Serial Data Output 7 COM 3 RX I COM 3 Serial Data Input 8 COM 3 TX O COM 3 Serial Data Output 9 MODE Discrete Reserved: HD Software Only 10 EXTERNAL CLOCK I Build dependant 11 Reserved Reserved: Tie to Vcc with 3K3 resistor 12 Reserved Reserved: Tie to Vcc with 3K3 resistor 13 VBATT PWR +1.8V to +5.5V Backup power for RTC 14 1V8_Test PWR +1.8V DC Digital Power Test Point 15 DIG_GND PWR Digital Ground 16 VCC PWR +3.15V Power Input 17 FREQ OUT O Reserved: Timing Software Only 18 TIMEMARK O 1 PPS Output 19 Reserved DO NOT USE 20 LED 3 O GPS status LED 3 21 LED 2 O GPS status LED 2 22 LED 1 O GPS status LED 1 23 TDI JTAG Data In 24 TCK JTAG Clock 25 JTAGSEL JTAG Select 26 TDO JTAG Data Out 27 TMS JTAG Mode Select 28 2V8_Test PWR +2.8V DC Digital Power Test Point 29 RF_GND PWR RF Ground 30 RF_GND PWR RF Ground 31 RF_IN PWR RF Input 32 RF_GND PWR RF Ground Table 6 - Q20 Module Pin Allocations QINETIQ/FST/I&C/SPEC044447/2.0 Page 15

16 5 Electrical Specification 5.1 Absolute Maximum Ratings Parameter Symbol Min Max Units Power Supply Voltage VCC V Battery Backup Voltage VBATT V Input Pin Voltage V IN V Table 7 - Q20 Module Absolute Maximum Ratings! Warning Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. Q20 is not protected against over-voltage or reversed voltages. Voltage spikes exceeding the power supply voltage specification given in the table above must be reduced by using appropriate protection diodes. 5.2 Operating Conditions Parameter Symbol Min Max Units Power Supply Voltage VCC V Power Supply Voltage Ripple VCC PP 70 mv Backup Battery Voltage VBATT 1.8 V CC V Input Pin Voltage V IN 0 V CC V Input Pin Low Voltage V IN_LOW 0.15 V Input Pin High Voltage V IN_HIGH V CC V Output Pin Low Voltage V OUT_LOW 0.4 V Output Pin High Voltage V OUT_LOW 0.67 x V CC V Table 8 - Q20 Module Operating Conditions! Warning The VBATT supply shall be constrained to be no higher than VCC. If VBATT exceeds VCC, 50μA 150μA current will continually be drained from the VBATT supply. Additionally, there is a risk that I 2 C bus will not operate correctly and that custom settings (e.g. Baud Rate) will be lost.! Warning Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability. QINETIQ/FST/I&C/SPEC044447/2.0 Page 16

17 5.3 Q20 Module Pin I/O Details Pin Name O/P (ma) Open Collector Schmitt I/P Bias F TYP 5V Tolerant COMx TX [0:2] 4 No Out Only None 230k - COMx RX [0:2] In Only - No Up - Yes nreset In Only - Yes Up - Yes TIMEMARK 6 No No None 1M Yes ntrst In Only - No Up - Yes TMS In Only - No Up - Yes TCK In Only - No Up - Yes TDI In Only - No Up - Yes TDO 6 No Out Only Up 1M Yes JTAGSEL In Only - No Up - Yes EXT CLOCK In Only M No Table 9 - Q20 Module Pin I/O Details 5.4 RF Input Parameters Parameter Frequency Typical -40 C to +80 C +25 C Insertion loss max db Input filter min db attenuation min db min db min db Max power in-band dbm Table 10 Q20 Module RF Input Parameters QINETIQ/FST/I&C/SPEC044447/2.0 Page 17

18 6 Interfaces 6.1 Outline Description Serial Interface Three UARTs are provided in the Q20 and are of the 16C550 type with 16 deep FIFOs on their receive and transmit buffers. They support fully programmable, individually selectable, baud rates up to 230,400 baud. The UARTs provide: Network connectivity (e.g. network assist) User environment (application. software) Developer access All UARTs support direct connection to an external IrDA transmitter/receiver. Although the UARTs support a variable number of data bits, only 8 data bit transfers are required. Because the UARTs only have 16 deep FIFOs, interrupt response can be an issue at high baud rates. Each UART has 5 interrupt outputs that are combined to form 3 interrupt sources for the interrupt controller. An interrupt is generated when either a character is received or the FIFO remains unemptied for the timeout period; when the transmit buffer can except more data; or when modem status changes or errors occur. All of the individual causes of interrupt in a UART can be masked within that UART. Outputs from the UARTs are non-inverted, and at CMOS level. In quiescent state the UART transmit is held to the marking (HIGH) level. The UART receive is biased HIGH. Figure 6 - Q20 Module Transmit Timing Reserved Reserved for future firmware upgrade. QINETIQ/FST/I&C/SPEC044447/2.0 Page 18

19 6.2 Detailed Pin Description Pin 1 ntrst JTAG active low reset. Input only (biased high), 5 V tolerant Pin 2 nreset External reset active low with Schmitt trigger input (input is triggered on high-tolow transition). This is the hard reset input and is used to completely reset the Q20 module. It is recommended that when asserted, nreset is held low for at least 1ms. A hard reset occurs when the nreset signal is asserted low or at power on. During a hard reset the following actions happen: Pin 3 COM 1 RX the Q20 is set to run from the PLLCLK input the PLL is set to its default frequency GPIO functions are set to default the RTC counter is reset COM 1 serial port - receive signal. Input only (biased high), 5 V tolerant Pin 4 COM 1 TX COM 1 serial port - transmit signal. Output only, unbiased push-pull output I OUT(MAX) = 4 ma Pin 5 COM 2 RX COM 2 serial port - receive signal. Input only (biased high), 5 V tolerant Pin 6 COM 2 TX COM 2 serial port - transmit signal. Output only, unbiased push-pull output I OUT(MAX) = 4 ma Pin 7 COM 3 RX COM 3 serial port - receive signal. Input only (biased high), 5 V tolerant Pin 8 COM 3 TX COM 3 serial port - transmit signal. Output only, unbiased push-pull output I OUT(MAX) = 4 ma Pin 9 MODE Reserved for High Dynamic (HD) software Pin 10 EXT CLOCK External clock input - available as a hardware option instead of the internal TCXO F IN = 20 MHz. DC coupled clipped sine wave, 0.8V Min / 1.2V Typ / 2.2V Max Pin 11 Reserved Reserved for future firmware upgrade. Tie to Vcc with 3K3 resistor Pin 12 Reserved Reserved for future firmware upgrade. Tie to Vcc with 3K3 resistor QINETIQ/FST/I&C/SPEC044447/2.0 Page 19

20 Pin 13 VBATT Battery backup input for Real Time Clock VBATT MAX = Vcc VBATT MIN = 1V8 I OPERATE = 2.8µA Vcc = 3V15) Pin 14 1V8_Test Test point for the 1V8 power for the digital baseband circuitry - derived on-board the Q20 module. This can be used as a low current output at 1V8. I OUTMAX = 25mA Pin 15 DIG_GND Electrical ground for the baseband digital circuitry Pin 16 VCC Primary power for the Q20 module. All input power (except battery backup for the real time clock VBATT) is derived from this input Pin 17 FREQ OUT Reserved for timing software Pin 18 TIMEMARK 1Pulse Per Second, rising edge aligned to UTC second rollover, pulse length 100 μs Pin 19 Reserved Reserved for future firmware upgrade Pin 20 LED 3 LED 3 is configured as a GPS status LED output drive which pulses to indicate the number of satellites tracked for which valid ephemeris data is available Pin 21 LED 2 LED 2 is configured as a GPS status LED output drive which pulses to indicate the number of satellites tracked for which valid ephemeris data is not available Pin 22 LED 1 LED 1 is configured as a GPS status LED output drive which pulses when power is applied, but no navigation solution is available Pin 23 TDI JTAG data in. Input only (biased high), 5 V tolerant Pin 24 TCK JTAG clock. Input only (biased high), 5 V tolerant Pin 25 JTAGSEL JTAG select. Input only (biased high), 5 V tolerant Pin 26 TDO JTAG data out. Output only (biased high), 5 V tolerant I OUT(MAX) = 6 ma Pin 27 TMS QINETIQ/FST/I&C/SPEC044447/2.0 Page 20

21 JTAG mode select. Input only (biased high), 5 V tolerant Pin 28 2V8_Test Test point for the 2V8 power for the RF circuitry - derived on-board the Q20 module.! Note: TEST ONLY. Do not use as a 2V8 source Pin 29 RF_GND Electrical ground for the RF front end circuitry Pin 30 RF_GND Electrical ground for the RF front end circuitry Pin 31 RF_IN RF input from 50-ohm impedance antenna. This input is AC coupled (see Appendix A - Q20 module circuit diagram)! Note: The provision of an electrical supply to power an external antenna with an active low noise amplifier is not supported on the Q20 module Pin 32 RF_GND Electrical ground for the RF front end circuitry QINETIQ/FST/I&C/SPEC044447/2.0 Page 21

22 7 References [1] QINETIQ/FST/ICD035773/2.6, Q20 GPS Receiver Module Interface Control Document, November Abbreviations 1 PPS One Pulse Per Second AGC Automatic Gain Control AHB ARM High-speed Bus APB ARM Peripheral Bus A-to-D Analogue to Digital C/A-code GPS Coarse/Acquisition-code dbi decibel isotropic dbw decibel Watts EEPROM Electrically Erasable Programmable Read-Only Memory ESD Electro-Static Discharge FFT Fast Fourier Transform FIFO First In First Out GNSS Global Navigation Satellite System GPIO General Purpose Input Output GPS Global Positioning System Hz Hertz (cycles per second) ICD Interface Control Document IF Intermediate Frequency IRQ Interrupt Request L1 Link 1 frequency ( MHz) LED Light Emitting Diode LNA Low Noise Amplifier MHz Mega Hertz (10 6 cycles per second) mw Milli Watt (10-3 Watt) NCO Numerically Controlled Oscillator NMEA National Marine Electronics Association PCB Printed Circuit Board PDOP Position Dilution Of Precision PLL Phase Lock Loop ppm parts per million PRN Pseudo Random Noise PVT Position, Velocity, Time RF Radio Frequency SiGe Silicon-Germanium SPI Serial Peripheral Interface TBC To Be Confirmed TCXO Temperature Compensated Crystal Oscillator UTC Universal Time Co-ordinated QINETIQ/FST/I&C/SPEC044447/2.0 Page 22

23 9 Glossary Acquisition C/A-code Cold start Fix Hot start Sensitivity Signal to Noise Tracking Warm start The initial process of aligning a spread spectrum receiver's local pseudo random code sequence with the corresponding sequence received from the transmitter Coarse/Acquisition-code. A unique (per satellite) pseudorandom code used to modulate the GPS carrier. The C/A-code is 1023 bits long and repeats every millisecond (1.023 MHz chipping rate). C/A-code is currently transmitted only on the L1 frequency of MHz. A Cold Start is defined as starting the acquisition process using no previous GPS almanac, ephemeris, and degraded time and position data. The generation of a single GPS based position solution. This may include the time to acquire sufficient satellite signals (usually four) to calculate a position solution, and to demodulate ephemeris data from the navigation data stream. A Hot Start is defined as starting the acquisition process using a valid almanac, valid ephemeris, position to better than 1 km accuracy and time to better than 1 ms accuracy. The smallest RF signal received that can be used to provide a useful output. In the case of a GPS receiver this is the lowest signal level that can be used to contribute to a position solution. The dimensionless ratio of bit energy to noise plus interference energy accumulated over the period of one bit. Maintaining the alignment of the incoming GPS satellite signal with the receiver s replica code. A Warm Start is defined as starting the acquisition process using a valid almanac, position better than 10 km accuracy and time better than 1s accuracy. QINETIQ/FST/I&C/SPEC044447/2.0 Page 23

24 A Q20 Module Minimum Application Circuit A.1 Passive Antenna Passive Antenna (5mm max from Q20 module) 17 FREQ OUT 18 TIMEMARK 19 Reserved 20 LED 3 21 LED 2 22 LED 1 23 TDI 24 TCK 25 JTAGSEL 26 TDO 27 TMS 28 2V8_TEST 29 RF_GND 30 RF_GND 31 RF_IN 32 RF_GND VCC 16 DIG_GND 15 1V8_TEST 14 VBATT 13 Reserved 12 Reserved 11 EXT CLOCK 10 MODE 9 COM 3 TX 8 COM 3 RX 7 COM 2 TX 6 COM 2 RX 5 COM 1 TX 4 COM 1 RX 3 nreset 2 ntrst 1 3K3 3K3 Backup Battery RS232 Level Shifter VCC Figure 7: Minimum Application Circuit Passive Antenna QINETIQ/FST/I&C/SPEC044447/2.0 Page 24

25 A.2 Active Antenna C ANT 1N0 Active Antenna V ANT Fuse 50mA L ANT 47N 17 FREQ OUT 18 TIMEMARK 19 Reserved 20 LED 3 21 LED 2 22 LED 1 23 TDI 24 TCK 25 JTAGSEL 26 TDO 27 TMS 28 2V8_TEST 29 RF_GND 30 RF_GND 31 RF_IN 32 RF_GND VCC 16 DIG_GND 15 1V8_TEST 14 VBATT 13 Reserved 12 Reserved 11 EXT CLOCK 10 MODE 9 COM 3 TX 8 COM 3 RX 7 COM 2 TX 6 COM 2 RX 5 COM 1 TX 4 COM 1 RX 3 nreset 2 ntrst 1 3K3 3K3 Backup Battery RS232 Level Shifter VCC Figure 8: Minimum Application Circuit Active Antenna QINETIQ/FST/I&C/SPEC044447/2.0 Page 25