Nagpur, INDIA Nagpur, INDIA

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1 Power Quality Problems Study On IEEE 14 Bus System And Their Mitigation Using UPQC With Different Control Schemes (Methodology for deciding the most sensitive load and voltage sag mitigation) Vikas Singh M.Tech(Integrated Power System) VNIT Nagpur, INDIA Nita.R.Patne Assistant Professor (Electrical Engineering Dept.) VNIT Nagpur, INDIA Abstract-In little more than ten years, electricity power quality has grown from obscurity to a major issue. Power quality is among the main things that is emphasized and is taken into consideration by utilities in order to meet the demands of their customer. At each passing day this issue has becoming more serious and at the same time the user s demand on power quality also gets more critical.thus it is essential to establish a power quality monitoring system to detect power quality disturbance. Several research studies regarding the power quality have been done before and their aims frequently concentrated on the collection of raw data for a further analysis, so the impacts of various disturbances can be investigated. This thesis deals with the implementation of fact device UPQC on IEEE 14 BUS system. Different control schemes have been suggested for UPQC. Also a methodology is shown for determining the most sensitive bus and the most sensitive load. UPQC is installed between the sensitive bus and the load with three different control schemes and results are shown for different types of fault at different-different locations. Also a comparison is shown between all the control schemes. Keywords: UPQC, Voltage Sag,Voltage Swell, Power Quality. Hysteresis control,unit vector template generation technique,pwm technique D I. INTRODUCTION UE to the extensive use of power electronic based equipments/loads almost in all areas, the point of common coupling (PCC) could be highly distorted [1]-[3]. The switching ON/OFF of high rated load connected to PCC may result into voltage sags or swells on the PCC. There are several sensitive loads, such as computer or microprocessor based AC/DC drive controller, with good voltage profile requirement; can function improperly or sometime can lose valuable data or in certain cases get damaged due to these voltage sag and swell conditions. One of the effective approaches is to use a unified power quality conditioner (UPQC) at PCC to protect the sensitive loads. A UPQC is a combination of shunt and series APFs, sharing a common dc link [1-3], [6-10]. It is a versatile device that can compensate almost all power quality problems such as voltage harmonics, voltage unbalance, voltage flickers, voltage sags & swells, current harmonics, current unbalance, reactive current, etc. The Unified Power Quality Conditioner (UPQC) has evolved to be one of the most comprehensive custom power solutions for power quality issues relating to non-linear harmonic producing loads and the effect of utility voltage disturbance on sensitive industrial loads. To investigate the performance of the proposed control schemes for the UPQC, simulations are carried out and validated with experimental results II. SYSTEM CONFIGURATION[6] The system configuration for UPQC is shown in the Fig.1.The voltage at PCC may be or may not be distorted depending on the other non-linear loads connected at PCC. Also, these loads may impose the voltage sag or swell condition during their switching ON and/or OFF operation. The UPQC is installed in order to protect a sensitive load from all disturbances. The UPQC consists of two voltage source inverters connected back to back, sharing a common dc link. Each inverter is realized by using six IGBT switches. One inverter is connected parallel with the load, acts as shunt APF, helps in compensating load harmonic current, Figure.1 Block Diagram of UPQC 1

2 reactive current and maintain the dc link voltage at constant level. The second inverter is connected in series with the line using series transformers, acts as a controlled voltage source maintaining the load voltage sinusoidal and at desired constant voltage level. III. STEADY- STATE POWER FLOW ANALYSIS[6] The UPQC is controlled in such a way that the voltage at load bus is always sinusoidal and at desired magnitude.in the following analysis the load voltage is assumed to be in phase with terminal voltage even during voltage sag and swell condition.in this particular condition, the series APF could not handle reactive power and the load reactive power is supplied by shunt APF alone[5]. Figure. 2 Equivalent Circuit of a UPQC The source voltage, terminal voltage at PCC and load voltage are denoted by Vs, V t and V L respectively. The source and load currents are denoted by i s and i L respectively. The voltage injected by series APF is denoted by V Sr, whereas the current injected by shunt APF is denoted by i Sh. Taking the load voltage, V L, as a reference phasor and suppose the lagging power factor of the load is Cos L then we can write;[5] V L =V L 0 0 (1) I L =I L - L (2) Vt=V L (1+k) 0 0 (3) Where factor k represents the fluctuation of source voltage, defined as, k= Vt VL VL The voltage injected by series APF must be equal to, V Sr =V L Vt= kv L 0 0 (5) The UPQC is assumed to be lossless and therefore, the active power demanded by the load is equal to the active power input at PCC. The UPQC provides a nearly unity power factor source current, therefore, for a given load condition the input active power at PCC can be expressed by the following equations, Pt=P L (6) Vt.i S =V L.i L.cosφ L (7) V L (1+k).i S =V L.i L.cosφ L (8) i S =i L /(1+k)*cosφ L (9) The above equation suggests that the source current i S depends on the factor k, since φ L and i L are load (4) characteristics and are constant for a particular type of load. The complex power absorbed by the series APF can be expressed as, S S r =V Sr.i S * (10) P Sr =V Sr.i S. cosφs =-k.v L.i S.cosφs (11) Q Sr =VS r.i S.sinφ S (12) φ S = 0, since UPQC is maintaining unity power factor P Sr = V Sr.i S = k.v L.i S (13) Q Sr 0 (14) The complex power absorbed by the shunt APF can be expressed as, S Sh =V L.i Sh * (15) The current provided by the shunt APF, is the difference between the input source current and the load current, which includes the load harmonics current and the reactive current. Therefore, we can write; i S h = i S i L (16) i Sh = i S 00 i L φ L (17) i Sh =i S ( i L.cosφ L j i L.sinφ L ) (18) i Sh =(i S i L.cosφ L ) + j i L.sinφ L (19) P Sh =V L.i Sh.cosφs h =V L.(i S i L.cosφ L ) (20) Q Sh = V L.i Sh.sinφs h V L.i L.sinφ L (21) When a sag is detected such that Vs2 < Vs1 (rated), then for UPQC-Q, Vinj is calculated from as.[21] Vinj2 = (Vs12 Vs22) Now from PWM method 2Vinj = MI (Vdc/2), where MI is the desired modulation index (MI). Therefore, MI = (2 2.Vinj)/Vdc If x is the p. u. sag to be mitigated, minimum dc link voltage would be Vdc= 2 (2 )* (x(2-x)) * Vs1, for maximum value of MI =1 (taking the injection transformer turns ratio to be 1:1). IV. CONTROL SCHEMES FOR UPQC The control strategy is basically the way to generate reference signals for both shunt and series APF. The effectiveness of the UPQC depends on its ability to follow the reference signals with a minimum error to compensate the voltage sag and swell or any other undesirable condition. The series APF acts as a controlled voltage source. The shunt APF acts as a control source for maintaining the DC link voltage. The shunt APF also provides required var to the load such that the power factor at PCC is unity and only fundamental active power is supplied by the source. The voltage injected by series APF can be varied from 0 o to360 o.the series injected voltage has to be in phase (out of phase) with PCC voltage to compensate voltage sag swell. A. Different Control Schemes for UPQC Hystersis Control for Series and Shunt APF[18] Unit Vector Template Generation(UVTG) Technique for Series and Shunt APF[16],[18] Sinusoidal Pulse Width Modulation( SPWM) Technique for Series and Shunt APF[24][6] 2

3 V. IEEE 14 BUS TEST SYSTEM The IEEE 14 Bus Test Case represents a portion of the American Electric Power System (in the Midwestern US) as of February, A much-xeroxed paper version of the data was kindly provided by Iraj Dabbagchi of AEP and entered in IEEE Common Data Format by Rich Christie at the University of Washington in August Table No.2 Bus No. IEEE Bus Voltages (kv) Simulation Results (kv) VI..METHODOLOGY FOR DECIDING THE LOCATION OF UPQC Figure.5 IEEE 14 Bus System A. SYSTEM VARIFICATION FROM LOAD FLOW AND SIMULATION Table No.1 BUS NO Actual Value Bus Voltage From Load Bus Voltages from Simulation (p.u) (p.u) Flow(p.u) As our test system is the IEEE 14 BUS system which has 22 lines and 14 buses. Bus 1 is Slack Bus and Buses 2,3,6,8 are the generator buses. All the buses except bus 1 contains loads also. So it is important to decide that which bus is the most critical bus. For deciding the location of UPQC a fault based technique is suggested. The bus which is always affected by the faults, no matter where the fault is taking place in the system, is called as most critical bus and the load connected to that bus is called as the most critical load. The location of UPQC is decided in two steps : A. STEP 1 : At first we created the 3 phase fault at the midpoint of each line for a short period, as the 3 phase fault is the most severe one. Then we measured the voltages of all the buses except the generator and slack bus. Then we selected the 2 most critical lines. They are called critical because when we created the fault on these lines, the effect of 3 phase fault was most severe and they are affecting the most number of buses in the system. After preparing the table for these results we selected the line 7-9 and line 9-10 as the most critical lines. B. STEP 2 : After selecting the bus 9-10 & 7-9 as most critical line, we created the different types of faults at 5-5 % distance on these line. We plotted the graph between the distance and the voltage magnitude. After analyzing all the graphs and tables, we prepared the table for all conditions which shows that during all types of faults which buses are mostly affected. 3

4 VII. ANALYSIS FROM ABOVE RESULTS Sr.No FaultType Buses with 1 3Phase fault 2 PhaseA fault 3 PhaseA-B fault sag 4,7,9,10,11,14 7,9,10, 11,14 7,9,10 11,14 Line 7-9 Most Critical Line 9-10 Most Critical 7,9,10 9,10 7,9,10 9,10 7,9,10 9,10 Table. No.3 A. Conclusion from above Results Above table shows that bus 9 and bus 10 are the most critical buses because they are always suffering from sag created by different types of faults at different different locations. But we chose bus 9 as the most critical bus as larger load is connected at that bus. Fig Hysteresis Control VIII. SIMULATION RESULTS WITH DIFFERENT CONTROL SEHEMES A. Load And Bus Voltages During Fault Condition Figure Waveforms at Load Side with Hysteresis Controller Figure.8.1 Source and Load side wave forms During fault condition C. SPWM Based Series And Shunt Controller B. Hystersis Based Series And Shunt Controller 4

5 Figure SPWM based Controller Figure UVTG Technique Figure Load side waveforms with SPWM Technique D. Unit Vector Template Generation Technique Figure Load Side Waveforms with UVTG Technique E. CONCLUSION If the sags are more frequent and for a very short duration then it is better to use Hysteresis 5

6 Controller.since it is faster and in-sensitive to system parameters with inherent peak current limiting capability. Also it is easy to implement and in closed loop, offers current protection with excellent dynamic response. It ensures the elimination of higher order harmonics of the load without the need of any additional filter circuits. SPWM technique takes more simulation time and it takes more time to maintain dc link voltage. If the duration of sag is more but not occurring frequently then it is better to use SPWM technique If the sags are more frequent and for a very short duration and the load is most sensitive then it is better to use Hysteresis controller Unit vector template generation technique is more accurate and precise as we are generating a pu. Reference signal and then locking the phase other wise results are similar to hysteresis control. References 1. H. Akagi, New trends in active filters for improving power quality, Proceedings of the 1996 International Confe, Vol.1, Jan 1996, pp B. Singh, K. Al-Haddad, A. Chandra, A Review of Active Power Filters for Power Quality Improvement, IEEE Trans on Industrial Electronics, Vol. 45, No.5, Oct1999, pp Khadkikar V, Agarwal P, Chandra A, Barry A O and Nguyen T.D, A simple new control technique for unified power quality conditioner (UPQC), Harmonics and Quality of Power, th International Conference on Sept.2004, pp Vinod Khadkikar, A.Chandra, A.O. Barry, T.D. Nguyen Steady state power flow analysis of unified power quality conditioner (UPQC), Proceedings of International conference on Industrial Electronics and Control Applications (ICIECA), 2005, pp [M.A. Hannan, Azah Mohamed, PSCAD/EMTDC simulation of unified series shunt compensator for power quality improvement, IEEE Transactions on power delivery, Vol.20, No.2, 2005, pp Analysis of power flow in upqc under voltage sag and swell condition V. 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