SYNCHRONOUS DRAM MODULE

Transcription

1 SYNCHRONOUS DRAM MODULE 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM MT2LSDT432U 6MB MT4LSDT832UD 32MB MT4LSDT632UD 64MB MT4LSDT3232UD 28MB For the latest data sheet, please refer to the Micron Web site: Features -pin, dual in-line memory module (DIMM) PC - and PC33-compliant 6MB (4 Meg x 32), 32MB (8 Meg x 32), 64MB (6 Meg x 32), and 28MB (32 Meg x 32) Utilizes 25 MHz and 33 MHz SDRAM components Single +3.3V power supply Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths:, 2, 4, 8, or full page Auto Precharge and Auto Refresh Modes 6MB, 32MB, and 64MB modules; 64ms, 4,96-cycle refresh (5.625µs refresh interval); 28MB modules; 64ms, 8,92-cycle refresh (7.8µs refresh interval) LVTTL-compatible inputs and outputs Serial Presence-Detect (SPD) Gold edge contacts Table : CL = CAS (READ) Latency Timing Parameters Figure : -Pin DIMM (MO 6) Standard.in. (25.4mm) Options Marking Package -pin DIMM (standard) G -pin DIMM (lead-free) Y Timing (Cycle Timing) 7.5ns (33 MHz) -75 8ns (25 MHz) -8 ns ( MHz) - PCB Standard.in. (25.4mm) SPEED GRADE CLOCK FREQUENCY ACCESS TIME CL = 2 CL = 3 SETUP TIME HOLD TIME MHz 5.4ns 5.4ns.5ns.8ns MHz 6ns 6ns 2ns ns - MHz 9ns 7.5ns 2ns ns Table 2: Address Table MODULE DENSITY 6MB 32MB 64MB 28MB Refresh Count 4K 4K 4K 8K Device Banks 4 (BA BA) 4 (BA BA) 4 (BA BA) 4 (BA BA) Device Configuration 64Mb (4 Meg x 6) 64Mb (4 Meg x 6) 28Mb (8 Meg x 6) 256Mb (6 Meg x 6) Device Row Addressing 4K (A A) 4K (A A) 4K (A A) 8K (A A2) Device Column Addressing 256 (A A7) 256 (A A7) 52 (A A8) 52 (A A8) Module Ranks (S#, S2#) 2 (S#, S2#, S#, S3#) 2 (S#, S2#, S#, S3#) 2 (S#, S2#, S#, S3#) 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 24 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

2 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Table 3: Part Numbers PART NUMBER DENSITY CONFIGURATION SYSTEM BUS SPEED MT2LSDT432UG-75 6MB 4 Meg x MHz MT2LSDT432UY-75 6MB 4 Meg x MHz MT2LSDT432UG-8 6MB 4 Meg x MHz MT2LSDT432UY-8 6MB 4 Meg x MHz MT2LSDT432UG- 6MB 4 Meg x 32 MHz MT2LSDT432UY- 6MB 4 Meg x 32 MHz MT4LSDT832UDG-75 32MB 8 Meg x MHz MT4LSDT832UDY-75 32MB 8 Meg x MHz MT4LSDT832UDG-8 32MB 8 Meg x MHz MT4LSDT832UDY-8 32MB 8 Meg x MHz MT4LSDT832UDG- 32MB 8 Meg x 32 MHz MT4LSDT832UDY- 32MB 8 Meg x 32 MHz MT4LSDT632UDG-75 64MB 6 Meg x MHz MT4LSDT632UDY-75 64MB 6 Meg x MHz MT4LSDT632UDG-8 64MB 6 Meg x MHz MT4LSDT632UDY-8 64MB 6 Meg x MHz MT4LSDT632UDG- 64MB 6 Meg x 32 MHz MT4LSDT632UDY- 64MB 6 Meg x 32 MHz MT4LSDT3232UDG-75 28MB 32 Meg x MHz MT4LSDT3232UDY-75 28MB 32 Meg x MHz MT4LSDT3232UDG-8 28MB 32 Meg x MHz MT4LSDT3232UDY-8 28MB 32 Meg x MHz MT4LSDT3232UDG- 28MB 32 Meg x 32 MHz MT4LSDT3232UDY- 28MB 32 Meg x 32 MHz NOTE:. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT2LSDT432UG-8B. 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 2 24 Micron Technology, Inc. All rights reserved.

3 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Table 4: Pin Assignment (-Pin DIMM Front) Table 5: Pin Assignment (-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL Vss 3 A 26 Vss A2 27 CKE A4 28 WE# A6 29 S# A8 3 S2# 42 VDD 6 VDD 8 A 3 VDD BA 32 NC A2 33 NC VDD 34 NC DNU 35 NC 47 Vss MB 23 RFU 36 Vss 48 SDA 2 Vss 24 RFU 37 MB2 49 SCL 25 CK 5 VDD PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 5 Vss 63 A 76 Vss A3 77 CKE A5 78 DNU A7 79 S# A9 8 S3# 92 VDD 56 VDD 68 BA 8 VDD A 82 NC NC 83 NC VDD 84 NC RAS# 85 NC 97 Vss 6 MB 73 CAS# 86 Vss 98 SA 62 Vss 74 RFU 87 MB3 99 SA 75 CK SA2 Figure 2: Module Layout Front View Back View (Not populated for the 6MB module) U U2 U5 U4 U3 PIN PIN 23 PIN 5 PIN PIN 73 PIN 5 Indicates a VDD pin Indicates a VSS pin 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 3 24 Micron Technology, Inc. All rights reserved.

4 Table 6: Pin Descriptions 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Pin numbers may not correlate with symbols; for more information refer to the Pin Assignment tables on page 3 PIN NUMBERS SYMBOL TYPE DESCRIPTION 28, 72, 73 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS# and WE# (along with S#) define the command being entered. 25, 75 CK, CK Input Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 27, 77 CKE, CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides POWER-DOWN and SELF REFRESH operation (all banks idle), or CLOCK SUSPEND operation (burst access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK is disabled during power-down and self refresh modes, providing low standby power. 29, 3, 79, 8 S# S3# Input Chip Select: S# enables (registered LOW) and disablse (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code., 37, 6, 87 MB MB3 Input Input/Output Mask: MB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when MB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (after a two-clock latency) when MB is sampled HIGH during a READ cycle. 9, 68 BA, BA Input Bank Address: BA and BA define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. 3-8, 63-67, 69 7 A A2 Input Address Inputs: A-A2 are sampled during the ACTIVE command (row-address A-A2) and READ/WRITE command (column-address A-A8, with A defining AUTO PRECHARGE) to select one location out of the memory array in the respective bank. A is sampled during a PRE-CHARGE command to determine if both banks are to be precharged (A HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2 5, 7, 38 4, 3 Input/ Data I/Os: Data bus , 52 55, 57 6, 88 9, Output 6, 2, 3, 42, 5, VDD Supply Power Supply: +3.3V ±.3V. 56, 7, 8, 92, 2, 26, 36, 47, 5, 62, 76, 86, 97 VSS Supply Ground. 48 SDA Input/ Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presencedetect portion of the module. 49 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 98- SA SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 23, 24, 74 RFU Reserved for Future Use: These pins should be left unconnected. 22, 78 DNU Do Not Use: These pins are not connected on this module but are assigned pins on the compatible DRAM version , 7, NC Not connected. 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 4 24 Micron Technology, Inc. All rights reserved.

5 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Figure 3: Functional Block Diagram 6MB S# MB MB ML CS# U MH S2# MB MB ML CS# U2 MH RAS# CAS# CKE WE# A-A BA BA VDD VSS RAS#: SDRAMs CAS#: SDRAMs CKE: SDRAMs WE#: SDRAMs A-A: SDRAMs BA: SDRAMs BA: SDRAMs SDRAMs SDRAMs CK CK SCL WP A SPD U5 A U U2 6.8pF pf A2 SA SA SA2 SDA NOTE:. All resistor values are Ω. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at numberguide. Standard modules use the following SDRAM devices: MT48LC8M6A2TG Lead-free modules use the following SDRAM devices: MT48LC8M6A2P 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 5 24 Micron Technology, Inc. All rights reserved.

6 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Figure 4: Functional Block Diagram 32MB, 64MB, 28MB S# S# MB MB S3# S2# MB MB ML CS# U MH ML CS# U2 MH ML CS# U3 MH ML CS# U4 MH NOTE: RAS# CAS# CKE CKE WE# A-A (32MB, 64MB) A-A2 (28MB) BA BA VDD VSS RAS#: SDRAMs CAS#: SDRAMs CKE: SDRAMs U-U2 CKE: SDRAMs U3-U4 WE#: SDRAMs A-A: SDRAMs A-A2: SDRAMs BA: SDRAMs BA: SDRAMs SDRAMs SDRAMs. All resistor values are Ω. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at numberguide. SCL WP CK CK U U2 6.8pF U3 U4 6.8pF SPD U5 A A A2 SA SA SA2 SDA Standard modules use the following SDRAM devices: MT48LC8M6A2TG (32MB); MT48LC6M6A2TG (64MB); MT48LC32M6A2TG (28MB) Lead-free modules use the following SDRAM devices: MT48LC8M6A2P (32MB); MT48LC6M6A2TG (64MB); MT48LC32M6A2TG (28MB) 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 6 24 Micron Technology, Inc. All rights reserved.

7 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM General Description The MT2LSDT432U, MT4LSDT832UD, MT4LSDT632UD, and MT4LSDT3232UD are high-speed CMOS, dynamic random-access, 6MB, 32MB, 64MB, and 28MB memory modules organized in a x32 configuration. These modules use SDRAM devices which are internally configured as quad-bank DRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signal CK). Read and write accesses to the SDRAM module are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed. BA, BA select the device bank; A A (6MB, 32MB, and 64MB) or A A2 (28MB). The address bits registered coincident with the READ or WRITE command (A A7 for 6MB and 32MB; A A8 for 64MB and 28MB) are used to select the starting device column location for the burst access. These modules provide for programmable READ or WRITE burst lengths of, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the PRECHARGE cycles and provide seamless, high-speed, random access operation. These modules are designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs, outputs, and clocks are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal device banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 64Mb, 28Mb, or 256Mb SDRAM component data sheets. Serial Presence-Detect Operation These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,48-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 28 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 28 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I 2 C bus using the DIMM s SCL (clock) and SDA (data) signals. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Mode Register Definition The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 5, Mode Register Definition Diagram, on page 8. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 7 24 Micron Technology, Inc. All rights reserved.

8 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Mode register bits M M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M and M are reserved for future use. For the 28MB module, address A2 (M2) is undefined but should be driven LOW during loading of the mode register. The mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in Table 7, Burst Definition, on page 9. The block is uniquely selected by A Ai when the burst length is set to two; by A2 Ai when the burst length is set to four; and by A3 Ai when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block See note 7 of Table 7, Burst Definition, on page 9 for values of Ai. Full-page bursts wrap within the page if the boundary is reached, as shown in Table 7, Burst Definition, on page 9. Figure 5: Mode Register Definition Diagram 6MB, 32MB, and 64MB Modules A A A9 A8 A7 A6 A5 A4 A3 A2 A A Reserved* WB Op Mode CAS Latency BT Burst Length *Should program M2, M, M =,, to ensure compatibility with future devices. 28MB Module A2 A A 2 *Should program M, M =, to ensure compatibility with future devices. Reserved* Reserved* A9 A8 A7 A6 A5 A4 A3 A2 A A WB Op Mode CAS Latency BT Burst Length M8 - M7 - M3 M6 M5 M4 M6-M Defined - M2 M M M3 = Reserved Reserved Reserved Full Page Mode Register (Mx) Burst Type Sequential Interleaved Address Bus Address Bus Mode Register (Mx) Burst Length CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Operating Mode Standard Operation All other states reserved M3 = Reserved Reserved Reserved Reserved M9 Write Burst Mode Programmed Burst Length Single Location Access 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 8 24 Micron Technology, Inc. All rights reserved.

9 Table 7: Burst Definition 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Figure 6: CAS Latency Diagram BURST LENGTH Full Page (52) NOTE: STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED A A A A2 A A n = A A8 (location y) Cn, Cn+, Cn+2, Cn+3, Cn+4...,...Cn-, Cn... Not Supported. For a burst length of two, A Ai select the block-oftwo burst; A selects the starting column within the block. 2. For a burst length of four, A2 Ai select the block-offour burst; A-A select the starting column within the block. 3. For a burst length of eight, A3 Ai select the block-ofeight burst; A-A2 select the starting column within the block. 4. For a full-page burst, the full row is selected, and A Ai select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a burst length of one, A Ai select the unique column to be accessed, and Mode Register bit M3 is ignored. 7. Ai = A7 for 6MB and 32MB; Ai = A8 for 64MB and 28MB CLK COMMAND CLK COMMAND T READ T READ T NOP tlz T t AC CAS Latency = 2 NOP CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The s will start driving as a result of the clock edge one cycle earlier (n + m - ), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T and the latency is programmed to two clocks, the will start driving after T and the data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. T2 T2 NOP CAS Latency = 3 NOP t OH DOUT tlz tac T3 T3 NOP t OH DOUT T4 DON T CARE UNDEFINED 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 9 24 Micron Technology, Inc. All rights reserved.

10 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Write Burst Mode When M9 =, the burst length programmed via M M2 applies to both READ and WRITE bursts; when M9 =, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Table 8: CAS Latency Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHz) SPEED CAS LATENCY = 2 CAS LATENCY = aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 24 Micron Technology, Inc. All rights reserved.

11 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Commands Table 9, Commands and MB Operation Truth Table provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 64Mb, 28Mb, or 256Mb SDRAM component data sheet. Table 9: Commands and MB Operation Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) S# RAS# CAS# WE# MB ADDR S NOTES COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X READ (Select bank and column, and start READ burst) L H L H L/H 7 Bank/Col X 2 WRITE (Select bank and column, and start WRITE burst) L H L L L/H 7 Bank/Col Valid 4 BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 3 AUTO REFRESH or L L L H X X X 4, 5 SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER L L L L X Op-Code X 6 Write Enable/Output Enable L Active 7 Write Inhibit/Output High-Z H High-Z 7 NOTE:. A A(32MB) or A A2 (64MB, 28MB, and 28MB) provide row address and BA and BA determine which bank is made active. 2. A A8 (6MB and 32MB) or A A8 (64MB and 28MB) provide column address; A HIGH enables the auto precharge feature (nonpersistent), while A LOW disables the auto precharge feature; BA and BA determine which bank is being read from or written to. 3. A LOW: BA and BA determine which bank is being precharged. A HIGH: both banks are precharged and BA and BA are Don t Care. 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are Don t Care except for CKE. 6. A A (32MB) or A A2 (64MB, 28MB, and 28MB) define the op-code written to the Mode Register. 7. Activates or deactivates the s during WRITEs (zero-clock delay) and READs (two-clock delay). 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 24 Micron Technology, Inc. All rights reserved.

12 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Voltage on VDD Supply Relative to VSS V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS V to +4.6V Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Temperature T OPR (Commercial - ambient) C to +65 C Storage Temperature (plastic) C to +5 C Table : DC Electrical Characteristics and Operating Conditions 6MB Notes:, 6; VDD = +3.3V ±.3V PARAMETER/CONDITION SYM MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD V INPUT HIGH VOLTAGE: Logic ; All inputs VIH 2 VDD +.3 V 22 INPUT LOW VOLTAGE: Logic ; All inputs VIL V 22 INPUT LEAKAGE CURRENT: Command and Address II - µa Any input V VIN VDD CK, MB II2 - µa 33 (All other pins not under test = V) S# II3-5 5 µa OUTPUT LEAKAGE CURRENT: s are disabled; V VOUT VDD IOZ -5 5 µa 33 OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VOH 2.4 V VOL.4 V Table : DC Electrical Characteristics and Operating Conditions 32MB, 64MB, 28MB Notes:, 6; notes appear on page 8; VDD = +3.3V ±.3V PARAMETER/CONDITION SYM MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD V INPUT HIGH VOLTAGE: Logic ; All inputs VIH 2 VDD +.3 V 22 INPUT LOW VOLTAGE: Logic ; All inputs VIL V 22 INPUT LEAKAGE CURRENT: Command and Address II -2 2 µa Any input V VIN VDD CK, MB II2 - µa 33 (All other pins not under test = V) S# II3-5 5 µa OUTPUT LEAKAGE CURRENT: IOZ - µa s are disabled; V VOUT VDD 33 OUTPUT LEVELS: VOH 2.4 V Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VOL.4 V 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 2 24 Micron Technology, Inc. All rights reserved.

13 Table 2: IDD Specifications and Conditions 6MB Notes:, 6,, 3; notes appear on page 8; VDD = +3.3V ±.3V 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM PARAMETER/CONDITION SYM UNITS NOTES OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = t RC (MIN); CAS latency = 3 SELF REFRESH CURRENT: CKE.2V IDD7 b ma 4 a - Value calculated as one module rank in this operating condition, and all other ranks in Power-Down Mode. b - Value calculated reflects all module ranks in this operating condition. MAX IDD ma 3, 8, 9, 29 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD ma 29 STANDBY CURRENT: Active Mode; CKE = HIGH; S3# = HIGH; All banks active after t RCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 AUTO REFRESH CURRENT: CKE = HIGH; S# = HIGH IDD ma 3, 2, 9, 29 IDD ma 3, 8, 9, 29 t RC = t RC (MIN); CL = 3 IDD ma 3, 2, 8, t RC = 5.625µs; CL = 3 IDD ma 9, 29, 3 SELF REFRESH CURRENT: CKE.2V IDD ma 4 Table 3: IDD Specifications and Conditions 32MB Notes:, 6,, 3; notes appear on page 8; VDD = +3.3V ±.3V PARAMETER/CONDITION SYM UNITS NOTES OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = t RC (MIN); CAS latency = 3 MAX IDD a ma 3, 8, 9, 29 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD2 b ma 29 STANDBY CURRENT: Active Mode; CKE = HIGH; S# = HIGH; All banks active after t RCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 AUTO REFRESH CURRENT: CKE = HIGH; S# = HIGH IDD3 a ma 3, 2, 9, 29 IDD4 a ma 3, 8, 9, 29 t RC = t RC (MIN); CL = 3 IDD5 b, ma 3, 2, 8, t RC = 5.625µs; CL = 3 IDD6 b ma 9, 29, 3 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 3 24 Micron Technology, Inc. All rights reserved.

14 Table 4: IDD Specifications and Conditions 64MB Notes:, 6,, 3; notes appear on page 8; VDD = +3.3V ±.3V 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM PARAMETER/CONDITION SYM UNITS NOTES OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = t RC (MIN); CAS latency = 3 SELF REFRESH CURRENT: CKE.2V IDD7 b ma 4 a - Value calculated as one module rank in this operating condition, and all other ranks in Power-Down Mode. b - Value calculated reflects all module ranks in this operating condition. MAX IDD a ma 3, 8, 9, 29 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD2 b ma 29 STANDBY CURRENT: Active Mode; CKE = HIGH; S# = HIGH; All banks active after t RCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 AUTO REFRESH CURRENT: CKE = HIGH; S# = HIGH IDD3 a ma 3, 2, 9, 29 IDD4 a ma 3, 8, 9, 29 t RC = t RC (MIN); CL = 3 IDD5 b, ma 3, 2, 8, t RC = 5.625µs; CL = 3 IDD6 b ma 9, 29, 3 Table 5: IDD Specifications and Conditions 28MB Notes:, 6,, 3; notes appear on page 8; VDD = +3.3V ±.3V SELF REFRESH CURRENT: CKE.2V IDD7 ma 4 a - Value calculated as one module rank in this operating condition, and all other ranks in Power-Down Mode. b - Value calculated reflects all module ranks in this operating condition. MAX PARAMETER/CONDITION SYM UNITS NOTES OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = t RC (MIN); CAS latency = 3 IDD ma 3, 8, 9, 29 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD ma 29 STANDBY CURRENT: Active Mode; CKE = HIGH; S# = HIGH; All banks IDD ma 3, 2, 9, active after t RCD met; No accesses in progress 29 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 AUTO REFRESH CURRENT: CKE = HIGH; S# = HIGH IDD ma 3, 8, 9, 29 t RC = t RC (MIN); CL = 3 IDD5,8,8,8 ma 3, 2, 8, t RC = 7.825µs; CL = 3 IDD ma 9, 29, 3 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 4 24 Micron Technology, Inc. All rights reserved.

15 Table 6: Capacitance 6MB Note: 2; notes appear on page 8 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM PARAMETER SYMBOL MIN MAX UNITS Input Capacitance: Address and Command CI pf Input Capacitance: CKE CI pf Input Capacitance: CK CI pf Input Capacitance: S# CI pf Input Capacitance: MB CI pf Input/Output Capacitance: CIO 4 6 pf Table 7: Capacitance 32MB, 64MB, and 28MB Note: 2; notes appear on page 8 PARAMETER SYMBOL MIN MAX UNITS Input Capacitance: Address and Command CI 5.2 pf Input Capacitance: CKE CI pf Input Capacitance: CK CI pf Input Capacitance: S# CI pf Input Capacitance: MB CI5 5.2 pf Input/Output Capacitance: CIO 8 2 pf 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 5 24 Micron Technology, Inc. All rights reserved.

16 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Table 8: SDRAM Component AC Electrical Characteristics Notes: 5, 6, 8, 9,, 3; notes appear on page 8 AC CHARACTERISTICS PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES Access time from CLK (positive CL = 3 t AC ns 27 edge) CL = 2 t AC ns Address hold time t AH.8 ns Address setup time t AS ns CLK high-level width t CH ns CLK low-level width t CL ns Clock cycle time CL = 3 t CK ns 22 CL = 2 t CK 5 ns 22 CKE hold time t CKH.8 ns CKE setup time t CKS ns CS#, RAS#, CAS#, WE#, M hold time t CMH.8 ns CS#, RAS#, CAS#, WE#, M setup time t CMS ns Data-in hold time t DH.8 ns Data-in setup time t DS ns Data-out high-impedance time CL=3 t HZ ns CL = 2 t HZ ns Data-out low-impedance time t LZ 2 ns Data-out hold time (load) t OH ns Data-out hold time (no load) t OH N.8.8 n/a ns 28 ACTIVE to PRECHARGE command period t RAS 44 2, 5 2, 6 2, ns 32 ACTIVEto ACTIVE command period t RC ns AUTO REFRESH period t RCAR ns ACTIVE to READ or WRITE delay t RCD ns Refresh period (8,92 cycles) t REF ms PRECHARGE command period t RP ns ACTIVE bank A to ACTIVE bank B command RRD ns period Transition time t T.3.2 ns 7 WRITE recovery time t WR CLK + 7ns CLK + 7ns CLK + 7ns ns 24 Exit SELF REFRESH to ACTIVE command t XSR ns 2 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 6 24 Micron Technology, Inc. All rights reserved.

17 . Table 9: AC Functional Characteristics Notes: 5, 6, 8, 9,, 3; notes appear on page 8 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM PARAMETER SYMBOL UNITS NOTES READ/WRITE command to READ/WRITE command t CCD t CK 7 CKE to clock disable or power-down entry mode t CKED t CK 4 CKE to clock enable or power-down exit setup mode t PED t CK 4 M to input data delay t D t CK 7 M to data mask during WRITEs t M t CK 7 M to data high-impedance during READs t Z t CK 7 WRITE command to input data delay t DWD t CK 7 Data-in to ACTIVATE command t DAL t CK 5, 2 Data-in to precharge t DPL t CK 6, 2 Last data-in to BURST STOP command t BDL t CK 7 Last data-in to new READ/WRITE command t CDL t CK 7 Lastdata-intoPRECHARGEcommand t RDL t CK 6, 2 LOAD MODE REGISTER command to ACTIVE or REFRESH MRD t CK 25 command Data-out to high-impedance from PRECHARGE CL = 3 t ROH t CK 7 command CL = 2 t ROH t CK 7 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 7 24 Micron Technology, Inc. All rights reserved.

18 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Notes. All voltages referenced to VSS. 2. This parameter is sampled. VDD = VD = +3.3V; f = MHz, T A = 25 C; pin under test biased at.4v.. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range ( C T A 7 C) is ensured. 6. An initial pause of µs is required after powerup, followed by two Auto Refresh commands, before proper device operation is ensured. The two Auto Refresh command wake-ups should be repeated any time the tref refresh requirement is exceeded. 7. AC characteristics assume t T = ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at.5v with equivalent load: Q 5pF. t HZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet t OH before going High-Z.. AC timing and IDD tests have VIL = V and VIH = 3V, with timing referenced to.5v crossover point. If the input transition time is longer than ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the.5v crossover point. 2. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 3. IDD specifications are tested after the device is properly initialized. 4. Timing actually specified by t CKS; clock(s) specified as a reference only at minimum cycle rate. 5. Timing actually specified by t WR plus t RP; clock(s) specified as a reference only at minimum cycle rate. 6. Timing actually specified by t WR. 7. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 8. The IDD current will decrease or decrease in a proportional amount by the amount the frequency is altered for th etest condition. 9. Address transitions average one transition every two clocks. 2. CLK must be toggled a minimum of two times during this period. 2. Based on t CK = 33 MHz for -75, t CK = 25 MHz for -8, and t CK = MHz for VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including t WR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget ( t RP) begins 7ns after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC specifies three clocks. 27. t AC for -75 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. t CK = 7.5ns for -75, t CK = 8ns for -8, and t CK = 5ns for CKE is HIGH during refresh command period t RFC(MIN), else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 3. Refer to device data sheet for timing waveforms. 32. The value of t RAS used in -3E speed grade modules is calculated from t RC - t RP. 33. Leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 8 24 Micron Technology, Inc. All rights reserved.

19 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, Data Validity, and Figure 8, Definition of Start and Stop). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 7: Data Validity SPD Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 9, Acknowledge Response from Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. Figure 8: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 9: Acknowledge Response from Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 9 24 Micron Technology, Inc. All rights reserved.

20 Table 2: EEPROM Device Select Code Most significant bit (b7) is sent first 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b b Memory Area Select Code (two arrays) SA2 SA SA RW Protection Register Select Code SA2 SA SA RW Table 2: EEPROM Operating Modes MODE RW BIT WC BYTES INITIAL SEQUENCE Current Address Read VIH or VIL Start, Device Select, RW = RandomAddressRead VIH or VIL Start, Device Select, RW=, Address VIH or VIL RESTART, Device Select, RW= Sequential Read VIH or VIL Similar to Current or Random Address Read Byte Write VIL START, Device Select, RW = Page Write VIL 6 START, Device Select, RW = Figure : SPD EEPROM t F t HIGH t R SCL t LOW t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO SDA IN t AA t DH t BUF SDA OUT UNDEFINED 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 2 24 Micron Technology, Inc. All rights reserved.

21 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Table 22: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDD V INPUT HIGH VOLTAGE: Logic ; All inputs VIH VDD x.7 VDD +.5 V INPUT LOW VOLTAGE: Logic ; All inputs VIL - VDD x.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA VOL.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI µa OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO µa STANDBY CURRENT: SCL = SDA = VDD -.3V; All other inputs = VSS or VDD ISB 3 µa POWER SUPPLY CURRENT: SCL clock frequency = KHz IDD 2 ma Table 23: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SCL LOW to SDA data-out valid t AA.2.9 µs Time the bus must be free before a new transition can start t BUF.3 µs Data-out hold time t DH 2 ns SDA and SCL fall time t F 3 ns 2 Data-in hold time t HD:DAT µs Start condition hold time t HD:STA.6 µs Clock HIGH period t HIGH.6 µs Noise suppression time constant at SCL, SDA inputs t I 5 ns Clock LOW period t LOW.3 µs SDA and SCL rise time t R.3 µs 2 SCL clock frequency f SCL 4 KHz Data-in setup time t SU:DAT ns Start condition setup time t SU:STA.6 µs 3 Stop condition setup time t SU:STO.6 µs WRITE cycle time t WRC ms 4 NOTE:. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time ( t WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN 2 24 Micron Technology, Inc. All rights reserved.

22 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Table 24: Serial Presence-Detect Matrix 6MB, 32MB / : Serial Data, driven to HIGH / driven to LOW BYTE DESCRIPTION ENTRY (VERSION) MT2LSDT432U MT4LSDT832UD Number of Bytes Used by Micron Total Number of SPD Memory Bytes Memory Type SDRAM Number of Row Addresses 2 C C 4 Number of Column Addresses Number of Module Ranks or Module Data Width Module Data Width (continued) 8 Module Voltage Interface Levels LVTTL 9 SDRAM Cycle Time, t CK (CAS Latency = 3) 7.5ns (-75) 8ns (-8) ns (-) SDRAM Access From Clock, t AC (CAS Latency = 3) 5.4ns (-75) 6ns (-8) 7.5ns (-) Module Configuration Type None 2 Refresh Rate/Type 5.625µs/Self SDRAM Width (Primary SDRAM) 8 4 Error-Checking SDRAM Data Width 5 Minimum Clock Delay, t CCD t CK 6 Burst Lengths Supported, 2, 4, 8, Page 8F 8F 7 Number of Banks on SDRAM Device CAS Latencies Supported 2, CS Latency 2 WE Latency 2 SDRAM Module Attributes Unbuffered 22 SDRAM Device Attributes: General Attributes E E 23 SDRAM Cycle Time, t CK (CAS Latency = 2) ns (-75/-8) A A 5ns (-) F F 24 SDRAM Access From Clock, t AC, (CAS Latency = 2) 6ns (-75/-8) 6 6 9ns (-) SDRAM Cycle Time, t CK (CAS Latency = ) Not Supported 26 SDRAM Access From Clock, t AC, (CAS Latency = ) Not Supported 27 Minimum Row Precharge Time, t RP 2ns (-75/-8) 4 4 3ns (-) E E 28 Minimum Row Active to Row Active, t RRD 5ns (-75) F F 2ns (-8/-) Minimum RAS# to CAS# Delay, t RCD 2ns (-75/-8) 4 4 3ns (-) E E 3 Minimum RAS# Pulse Width, t RAS 44ns (-75) 2C 2C 5ns (-8) ns (-) 3C 3C 3 Module Rank Density 6MB Command Address Setup, t AS.5ns (-75) 5 5 2ns (-8/-) Command Address Hold, t AH.8ns (-75) ns (-8/-) 75 8 A A aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN Micron Technology, Inc. All rights reserved.

23 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Table 24: Serial Presence-Detect Matrix 6MB, 32MB (Continued) / : Serial Data, driven to HIGH / driven to LOW ENTRY BYTE DESCRIPTION (VERSION) MT2LSDT432U MT4LSDT832UD 34 Data Signal Input Setup, t DS.5ns (-75) 5 5 2ns (-8/-) Data Signal Input Hold, t DH.8ns (-75) 8 8 ns (-8/-) 36-4 Reserved Bytes 4 Device Minimum Active/Auto-Refresh Time, t RC 66ns (-75) 7ns (-8) 66ns (-) A A 42 6 Reserved Bytes 62 SPD Revision REV Checksum for Bytes -62 (-75) (-8) (-) 64 Manufacturer's JEDEC ID Code MICRON 2C 2C 65-7 Manufacturer's JEDEC Code (Cont.) FF FF 72 Manufacturing Location -2 -C -C 73-9 Module Part Number (ASCII) Variable Data Variable Data 9 PCB Identification Code Identification Code (Continuted) 93 Year of Manufacture in BCD Variable Data Variable Data 94 Week of Manufacture in BCD Variable Data Variable Data Module Serial Number Variable Data Variable Data Manufacturer-Specific Data (RSVD) A5 F6 DD A6 F7 DE 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN Micron Technology, Inc. All rights reserved.

24 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Table 25: Serial Presence-Detect Matrix 64MB, 28MB / : Serial Data, driven to HIGH / driven to LOW BYTE DESCRIPTION ENTRY (VERSION) MT4LSDT632UD MT4LSDT3232UD Number of Bytes Used by Micron Total Number of SPD Memory Bytes Memory Type SDRAM Number of Row Addresses 2 or 3 C D 4 Number of Column Addresses Number of Module Ranks Module Data Width Module Data Width (continued) 8 Module Voltage Interface Levels LVTTL 9 SDRAM Cycle Time, t CK (CAS Latency = 3) 7.5ns(-75) 8ns (-8) ns(-) SDRAM Access From Clock, t AC (CAS Latency = 3) 5.4(-75) 6ns (-8) 7.5ns (-) Module Configuration Type None 2 Refresh Rate/Type 5.625µs, 7.8µs/ 8 82 Self 3 SDRAM Width (Primary SDRAM) 8 4 Error-Checking SDRAM Data Width 5 Minimum Clock Delay, t CCD t CK 6 Burst Lengths Supported, 2, 4, 8, Page 8F 8F 7 Number of Banks on SDRAM Device CAS Latencies Supported 2, CS Latency 2 WE Latency 2 SDRAM Module Attributes Unbuffered 22 SDRAM Device Attributes: General Attributes E E 23 SDRAM Cycle Time, t CK (CAS Latency = 2) ns (-75/-8) A A 5ns (-) F F 24 SDRAM Access From Clock, t AC, (CAS Latency = 2) 6ns (-75/-8) 6 6 9ns (-) SDRAM Cycle Time, t CK (CAS Latency = ) Not Supported 26 SDRAM Access From Clock, t AC, (CAS Latency = ) Not Supported 27 Minimum Row Precharge Time, t RP 2ns (-75/-8) 4 4 3ns (-) E E 28 Minimum Row Active to Row Active, t RRD 5ns (-75) F F 2ns (-/-8) Minimum RAS# to CAS# Delay, t RCD 2ns (-75/-8) 4 4 3ns (-) E E 3 Minimum RAS# Pulse Width, t RAS 44ns (-75) 2C 2C 5ns (-8) ns (-) 3C 3C 3 Module Rank Density 32MB or 64MB 8 32 Command Address Setup, t AS.5ns (-75) 5 5 2ns (-8/-) Command Address Hold, t AH.8ns (-75) ns (-8/-) 75 8 A A aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN Micron Technology, Inc. All rights reserved.

25 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Table 25: Serial Presence-Detect Matrix 64MB, 28MB (Continued) / : Serial Data, driven to HIGH / driven to LOW ENTRY BYTE DESCRIPTION (VERSION) MT4LSDT632UD MT4LSDT3232UD 34 Data Signal Input Setup, t DS.5ns (-75) 5 5 2ns (-8/-) Data Signal Input Hold, t DH.8ns (-75) 8 8 ns (-8/-) 36-4 Reserved Bytes 4 Device Minimum Active/Auto-Refresh Time, t RC 66ns (-75) 7ns (-8) 66ns (-) A A 42 6 Reserved Bytes 62 SPD Revision REV. 2 or Checksum For Bytes -62 (-75) (-8) (-) 64 Manufacturer's JEDEC ID Code MICRON 2C 2C 65-7 Manufacturer's JEDEC Code (Cont.) FF FF 72 Manufacturing Location -2 -C -C 73-9 Module Part Number (ASCII) Variable Data Variable Data 9 PCB Identification Code Identification Code (Continuted) 93 Year of Manufacture in BCD Variable Data Variable Data 94 Week of Manufacture in BCD Variable Data Variable Data Module Serial Number Variable Data Variable Data Manufacturer-Specific Data (Rsvd) AB FC E3 B6 2 EE 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN Micron Technology, Inc. All rights reserved.

26 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Figure : -Pin DIMM Dimensions 6MB Front View (9.34) (9.4).25 (3.8) MAX.79 (2.) R (2X).8 (3.) (2X) U U2 U5.7 (7.78) TYP.5 (25.53).995 (25.27).8 (3.) TYP.8 (3.) TYP PIN.25 (6.35) TYP.39 (.) R(2X).39 (.) TYP.5 (.27) TYP.28 (3.25).8 (3.) (2X) PIN 5.54 (.37).46 (.7) 2.85 (72.39) Back View No Components This Side of Module PIN PIN 5 NOTE: All dimensions in inches (millimeters); MAX MIN or typical where noted. 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN Micron Technology, Inc. All rights reserved.

27 6MB (x32, SR); 32MB, 64MB, 28MB (x32, DR) -PIN SDRAM UDIMM Figure 2: -Pin DIMM Dimensions 32MB, 64MB, and 28MB Front View (9.34) (9.4).57 (4.) MAX.79 (2.) R (2X).8 (3.) (2X) U U2 U5.7 (7.78) TYP.5 (25.53).995 (25.27).8 (3.) TYP.8 (3.) TYP PIN.25 (6.35) TYP.39 (.) R(2X).39 (.) TYP.5 (.27) TYP.28 (3.25).8 (3.) (2X) PIN 5.54 (.37).46 (.7) 2.85 (72.39) Back View U4 U3 NOTE: All dimensions in inches (millimeters); PIN PIN 5 MAX MIN or typical where noted. Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 8 S. Federal Way, P.O. Box 6, Boise, ID , Tel: prodmktg@micron.com, Internet: Customer Comment Line: Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 95aef8948ad4 SD2_4C4_8_6_32x32UDG.fm - Rev. A 2/4 EN Micron Technology, Inc. All rights reserved.