Digital Self-Control Technique Applied to a High Frequency Isolated Pre-Regulator with Power Factor Correction

Transcription

1 Digital Self-Control Technique Applied to a High Frequency Isolated Pre-Regulator with Power Factor Correction P.P. Praça, L.D.S. Bezerra, G.A.L. Henn, R.N.A.L. Silva, R.A. da Câmara, L.H.S.C. Barreto, R.P. Torrico-Bascopé, D.S.liveira Jr Energy and Control Processing Group - GPEC / Department of Electrical Engineering / Universidade Federal do Ceará Centro de Tecnologia - Campus do Pici, Bl.705 Fortaleza-CE, Brazil, Phone: lbarreto@dee.ufc.br / rene@dee.ufc.br / paulopp@dee.ufc.br / demercil@dee.ufc.br Abstract- This paper presents a high frequency isolated preregulator using the self-control technique, which aims to provide a 400Vdc link with input power factor correction. The main feature of self-control technique, as the CC one, is the direct loop feedback from the input current, using the converter parameters for the current loop control. The input voltage sample is not necessary, as in several others PFC theories. The technique was carried out using a DSPIC from MICRCHIP. A kw prototype was assembled and its experimental waveforms will be presented on this paper. Keywords Self-control technique, UPS, Pre-Regulator, Digital Control. I. INTRDUCTIN Uninterruptable Power Systems are constantly used on applications where providing energy to the load is critical. Major of online UPS uses a low frequency transformer in order to isolate the grid from the others energy processing stages. However, the use of this kind of transformer causes a considerable increase on the volume, weight, and cost of the structure [1]. The use of UPS without an incorporated transformer could be a solution, as in [] and [3], however this structures are more susceptible to noises, voltage peaks, and transients [4]. During the last years, the evolution of the semiconductors, as diodes, transistors, IGBTs, and MSFETS, allowed high frequency isolation structures to become attractive on UPS applications [5]-[11]. Along with the evolution of the semiconductors, the use of faster processing controllers, as DSPs, FPGAs, and DSPICs, is becoming more and common on power electronics applications. So, the use of more polished digital control techniques with better responses than the analogical ones has made the microprocessors to suffer a great breakthrough on the last years. This works presents a structure for a high frequency isolation pre-regulator using power factor control technique, named self-control, which uses fewer sensors and is easy to be digitally implemented. The control of all energy processing stages of the preregulator (chopper, boost, and supervision), was developed on a MICRCHIP DSPIC30F3011, which the good processing capacity, low cost, and good programming interface enabled the implementation of a 1kW prototype. All the description of the processing stages and the project of the self-control for the PFC and output voltage regulation will be presented on the next section. Experimental waveforms prove the effectiveness of the used technique. II. PRPSED PRE-REGULATR CIRCUIT The adopted topology for the high frequency isolation preregulator is the same as in [1]. Figure 1 shows the UPS diagram. As it can be seen from that figure, the proposed systems is composed basically by two converters, where the first one is an isolated chopper, and the second one is a boost on the secondary side of the high frequency transformer. The chopper converter operates with duty cycle constant and equal to approximately 50%, and switching frequency 30kHz, being these values set on the controller DSPIC, which also generates the gate pulses and the soft-start operation. The main function of the chopper converter on this structure is to isolate the transformer primary-side sinusoidal voltage from the secondary one, in high frequency, which allows a great decrease on the structure weight and volume. As can be observed, the proposed system can operate with input voltage of 110Vac or 0Vac, which can be done by making a selection on the switch named SS. A boost converter, digitally controlled by a DSPIC, composes the second stage of the pre-regulator. This converter provides the DC link necessary to implement an inverter, and also corrects the system power factor. All the UPS supervision system and the monitoring of the grid (overvoltage and undervoltage control), grid fault, batteries bank activating, voltage loop control, PFC, and softstart from the chopper switches are performed by just one DSPIC /09/$ IEEE 854

2 Figure 1. High frequency isolation pre-regulator diagram. III. SELF-CNTRL ALGRITHM The self-control strategy is very attractive due to its intrinsic characteristic of using fewer sensors for measurements acquisitions, as this technique bases itself only on the boost converter inductor current acquisition and an output DC voltage sampling. Thus, the proposed strategy consists in generating a regulated output voltage Vo directly from the input current sampling. Figure shows the boost converter structure using this technique. The constant gain K makes the peak current of the As can be seen from Figure 3, the peak current is directly sampled from the circuit, and multiplied by a K gain, and calculated in order to make its value inside the triangular modulator voltage band. This value is then subtracted from the modulator amplitude, and the result composes an inverted rectified sinusoidal waveform. This signal is timed by the result from the voltage loop and then compared with a sawtooth modulator, generating the switching PWM pulses [5]. c L1 D Vcd 0 t SB1 + Cout + R V Vbus 0 t - d K Driver 1-D Voltage Controller dy dx Vref Figure. Proposed voltage pre-regulator topology. converter input to be inserted on an acceptable band of values for the PWM modulator. The Figure 3 block diagram presents the details of this structure. Figure 3. Self-Control structure. Figure 4. Supervision system block diagram. The developed control algorithm aims the UPS supervision and the output voltage control, keeping the input power factor approximately unitary. n the other hand, finding cheaper and faster processors was a pretty tough challenge to develop the whole system. As shown on the experimental results section, the choice of DSPIC 30F3010 proven to be viable and with an excellent response. Figure 4 shows the block diagram of the developed algorithm for the bus supervision and the chopper switches drives, while figure 5 presents the block diagram of the self-control algorithm /09/$ IEEE 855

3 The first step is to measure the boost converter input current and the output voltage. The acquisitions are made inside the interruption of the A/D converter, which make four measurements of each parameter. Next step is to multiply the constant K by the input current Iin. A limiter block is inserted on the algorithm to avoid variable saturation. Subsequently the PI controller characteristic equation from the voltage loop is calculated and another limiter block is inserted. Finally, the result from the input current loop is multiplied bu the output voltage loop (K.Iin). Then, the complementary duty cycle is implemented on the algorithm and its pulse is sent to the boost switch Sboost. IV. SELF-TUNING DESIGN The self-control strategy is based on the boost converter gain equation. This equation, presented in (1), relates the input and output voltages in function of the complementary duty cycle. It is desirable to impose a resistive characteristic to the input current. In order to obtain this equivalent resistance, the equation () shows a relation between power and RMS voltage. Equation (3) is a simplification of expression (). ( ) V 1 D = V (1) in ( 1 ) V D V V = IN = Rin = I I P ( 1 ) IN _ rms sense IN IN = VP D I = sense K I V P IN Where V p is the converter input peak voltage, P IN is the input nominal power, and V is the nominal output voltage. Figure 6 shows the curves of K in function of the processed power. In order to maintain a constant output voltage, the gain K needs to be varied. This variation will occur by changes on the load power and/or on the input voltage. It is possible to establish a minimum value of K and use the voltage loop as an adjuster element for the correct self-control operating point, by timing the current and voltage loops. Aiming to develop a faster and more efficient controller with reduced number of interested variables, the self-control technique has a considerably easy implementation project and a good performance on applications which requires that the input current follows the input voltage waveform. However, the main focus of this work is the digitally implementation of the self-control applied to a boost preregulator for power factor correction and output voltage control of a 1kW prototype. sense () (3) K Figure 5. Self-control block diagram. Pout=Pnom Pout=Pnom/ Pout=Pnom/4 Pout=Pnom/ Peak input voltage Figure 6. K as function of output power and peak input voltage. The self-tuning theory determines that the converter parameters and characteristics must be applied to project the current control loop. It is not necessary the generation of a reference signal for this control. The reference is generated by the power circuit itself, without being necessary to sample the converter input voltage, as usual made [6]. Figure 7 shows the proposed structure /09/$ IEEE 856

4 Figure 7. Bridgeless boost with self-tuning controller and the DSPIC hardware. utput power Mains input voltage utput voltage AC input frequency Switching frequency utput capacitance Boost inductance TABLE I Boost converter parameters P o = kw V 1 = 110Vac V o = 400Vdc f r = 60Hz f s = 30kHz C o = 1000uF L IN = 3.3mH Current Feedback gain K = 0.04 The classical input current control strategy consists in sampling the input voltage and multiplying it by the voltage loop control variable, generating a current reference with the same waveform as the input voltage. An error signal is also generated by the difference between the current sample and the reference, which passes through a controller and thus generating the switches duty cycle. Such approach leads to a increase on the number of components, if compared to the self-tuning strategy. The self-tuning strategy, however, aims to generate converter the output voltage directly from the current sample, without being necessary to approximate the variables for small signals. As can be verified in [5], the output voltage is determined by the complementary duty cycle. The voltage polarity is defined by the current direction. According with [5], the expression to obtain the gain K for the feedback of the current control was given by (3). The equation (4) shows the transfer function of the plant. G P P SE + V ( s). P. K Δ K ( s) C. V RSE P s P V ( s) = = V ( s R C 1) Where VP is the peak voltage, P is the output power, C is the capacitance of the output capacitor and K is the gain (4) given by equation (3). The strategy explained above was implemented in a DSPIC (MICRCHIP DSPIC30F3011), which was the responsible for the whole control of the switches and the data collection from the analogical signals. The boost converter parameters can be observed in table 1. As it can be seen from table 1, the sample gain is calculated using equation 1. However, to be used in the DSPIC, the equation must be converted in such a way that controller can interpret. To do so, it is necessary to add a set of gains, for example, the A/D converter gain, the modulator gain, the current sensor gain, etc. The A/D converter used by the controller has a 10 bits resolution, the current sensor (AGILLENT ACS75SCA-50) gain is 40mV/A and the modulator gain is determined by the following equations: G A/ D 104bits = = 04.8 Bits / V (5) 5V 1 G PWM = PDCmax (6) Where G A/D is the gain of the A/D converter, G PWM is the gain of the modulation and PDCmax is the value to be loaded on the DSPIC register to the projected switching frequency. Thus, the new K value to be implemented on the program is given by (7) and, for the voltage loop control, the adopted structure by the controller was a PI, as described by equation (8): Kamostr = GACS. GA/ D. GPWM. K (7) s + wz Cv ( S) = A s (8) In order to specify the parameters of the PI controller of the voltage loop control, the adopted criterions can be the same as in the classical control, making one pole on the origin, to reduce the static gain, and positioning one zero on one decade under the crossing frequency. w = 60 / 4 = 15 Hz w = w /10 = 1,5Hz (9) C Z C The parameter A from equation (8) can be obtained looking on the bode diagram presented on figure 8. This value is acquired looking after the necessary gain to force the openloop gain to cross the zero db on desired crossing frequency (15Hz). The gain value in this case is Figure 8 shows de bode diagrams from: the plant G p (S), the controller C(S), and from the open loop control system FTMA(S), with a phase margin of 80 degrees, a sample gain K amostr of,47 (using a Q5 fixed point notation this value goes to 141 decimal), a K 1 gain of (in Q3 is , which incorporates the ADC gain), and a gain K of (in Q3 is ). Those values of the controller were obtained by using bilinear mapping (tustin s method) [16], with a sample time of 33µs /09/$ IEEE 857

5 I sensor D medio Figure 9. Sinusoidal input current through the sensor (channel 1-1V/div, 4.964ms) and average switch duty cycle (channel - 1V/div, 4.964ms). Figure 8. Bode plot of the boost converter (Gp(z)) plant, plant and voltage sensor gain/phase (Gp(Z).Hv(Z)) and open loop plot (FTMA(z)). Taking into account the previously calculated parameters K amostr, K 1 and K, and using the trapezoidal approximation for the conversion of the controller into the discrete plan, the following structure can be achieved [15]: U( K) = U( K 1) + K. E( K) + K. E( K 1) (10) 1 Where U(K), U(K-1), E(K) and E(K-1) are, respectively, the current input, the previous input, the current error, and the previous error. Applying this equation with the previous calculated gains leads to the implemented controller: Figure 10. Input current through the sensor (channel 1-1V/div, 4.964ms) and average duty cycle on the switch (channel - 1V/div, 4.964ms). UK ( ) = UK ( 1) EK ( ) EK ( 1) (11) U ( K) = U ( K 1) E ( K) E ( K 1) (1) Q3 Q3 Q3 Q0 Q3 Q0 Using the Q notation to manipulate the developed program variables, the resulting parameters can be seen in equation 1. V. EXPERIMENTAL RESULTS Experimental results for a kw prototype are shown in following. Figure 9 presents the input current through the current sensor, with an offset voltage of.5v inherent to the sensor, and the average duty cycle on the switch, while Figure 9 shows the behavior of the duty cycle on the self-control for a triangular carrier current signal. It must be noticed from figures 9 and 10 that the adopted control strategy makes the switching duty cycle signal to follow the input reference signal, whatever is the carrier waveform. Figure 11 presents the converter input voltage and current with a measured power of 103W. As can be seen in Figure 11, the input voltage and current are in the same phase, which proves the power factor correction control effectiveness. Figure 11. Input voltage (channel 1-100V/div, 5ms) and current (channel - 0A/div, 5ms). Figure 1 presents voltage and current waveforms on the secondary side of the transformer, which has a high (30kHz) and a low (10Hz) frequency component, with an amplitude of 300V ( 150Vrms). Figure 13 shows the converter output voltage, with a nominal voltage as specified on table 1. Figure 14 presents the system behavior submitted to a load step of 4% (700W to 1000W). From this figure, it can be observed the voltage control loop acting on the current loop making the output voltage to follow the nominal one /09/$ IEEE 858

6 Figure 1. Secondary side voltage (channel 1-00V/div, 4ms). Figure 15. utput voltage (channel 1-100V/div, 500ms) and input current (canal - 10A/div, 500ms). V out I out Figure 13. Boost converter output voltage (channel 1-100V/div, 50ms) and output current (canal - A/div, 50ms). Figure 16. Efficiency VI. CNCLUSIN A novel application for the self-tuning algorithm was successfully developed for a pre-regulator with high frequency isolation. This new controller has some interesting features, like simplicity and robustness, becoming a good choice for high power applications with a wide input range. Experimental results were satisfactory as expected. The chosen processor seemed to be very effective for this application. The technique used was very simple and easy to be implemented on digital controllers, being possible to be expanded for mid and high-end DSPs and FPGAs on future. The measured converter efficiency was 9%. Figure 14. Load step change. utput voltage (channel 1-100V/div, 500ms) and output current (channel - A/div, 500ms ). Figure 15 presents the behavior of the output voltage and input current waveforms for a load step change from 700W to 1000W. The system efficiency can be observed on Figure 16, where can be observed that the efficiency is 9% at nominal power. REFERENCES [1] F. Botterón and H. Pinheiro, A three-phase UPS that complies with the standard IEC , IEEE Trans. Ind. Electron., vol. 54, no. 4,pp , Aug [] J.H. Choi, J.-M. Kwon, J.-H. Jung, and B.-H. Kwon, Highperformance online UPS using three-leg type converter, IEEE Trans. Ind. Electron.,vol. 5, no. 3, pp , Jun [3] C.C. Yeh and M. D. Manjrekar, A reconfigurable uninterruptible power supply system for multiple power quality applications, IEEE Trans.Power Electron., vol., no. 4, pp , Jul /09/$ IEEE 859

7 [4] R. Koffler, Transformer or transformerless UPS?, Power Eng. J., vol. 17, no. 3, pp , Jun./Jul [5] K. Hirachi, J. Yoshitsugu, K. Nishimura, A. Chibani, and M. Nakaoka, Switched-mode PFC rectifier with high-frequency transformer link for high-power density single phase UPS, in Proc. IEEE Power Electron.Spec. Conf., 1997, vol. 1, pp [6] R. Yamada et al., High-frequency isolation UPS with novel SMR, in Proc. IEEE Ind. Electron., Control, Instrum. Conf., 1993, vol., pp [7] H. Pinheiro and P. K. Jain, Series-parallel resonant converter UPS with capacitive output DC bus filter for powering HFC networks, IEEE Trans.Power Electron., vol. 17, no. 6, pp , Nov [8] N. Vázquez, C. Aguilar, J. Arau, R. Cáceres, I. Barbi, and J. A. Gallegos, A novel uninterruptible power supply system with active power factor correction, IEEE Trans. Power Electron., vol. 17, no. 3, pp , May 00. [9] M. A. Rooij, J. A. Ferreira, and J. D. Van Wyk, A novel unity power factor low-emi uninterruptible power supply, IEEE Trans. Ind. Appl., vol. 34, no. 4, pp , Jun. Aug [10] G. V. Torrico-Bascopé and I. Barbi, Isolated flyback-current-fed push pull converter with power factor correction, in Proc. Brazilian Power Electron. Conf., 1997, vol. 1, pp [11] A. Ikriannikov and S. Cuk, Power factor correction shifting of input 60 Hz rectification to the secondary of isolation transformer, in Proc. Brazilian Power Electron. Conf., 1999, vol. 1, pp [1] Torrico-Bascopé, R. P.; liveira, D. S..; Branco, C. G. C.; Antunes, F. L. M. A UPS with 110-V/0-V Input Voltage and High-Frequency Transformer Isolated, IEEE Transactions n Industrial Electronics, Vol. 55, No. 8, August 008. [13] Branco, C. G. C.; Cruz, C. M. T. A Non-Isolated Single Phase n- Line Ups With Universal Input utput Voltage, ISIE 005 IEEE International Symposium on Industrial Electronics, 005. [14] RASHID, M. H. Power Electronics Handbook. Ed. Academic Press, 001. [15] Czeslau L. Barczak, Controle Digital de Sistemas Dinâmicos. 1ª Ediction. São Paulo. Ed. Edgard Blucher, [16] K. Astrom; T. Hagglund. PID Controllers: Theory, Design, and Tuning. a Ediction. USA [17] Ben-Yaakov, S., Zeltser, I. The Dynamics of a PWM Boost Converter with Resistive Input, IEEE Transactions on Industrial Electronics, Vol. 46, No. 3, June [18] D. Borgonovo and S. Mussa, Single-phase boost pfc voltage-doubler self-controlled using FPGA, in Power Electronics Specialists Conference, 008, pp [19] S. Mussa and H. Mohr, Voltage-doubler rectifier with pfc, regulation and balancing of the output voltages using dsp, in Brazilian Power Electronics Conference (CBEP 001), 001, pp [0] D. Borgonovo, J. P. Remor, A. J. Perin, and I. Barbi, A self-controlled power factor correction single-phase boost pre-regulator, in Power Electronics Specialists Conference, 005, pp [1] D. Borgonovo, J. Perin, and S. Mussa, A self-controlled single-phase voltage-doubler boost using FPGA, in Brazilian Power Electronics Conference (CBEP 007), 007, pp [] Dixon, L., Average current mode control of switching power supplies, Application Note U-140. Unitrode [3] Choi, N-C., Seo, M-H., J., Power factor correction circuit having an error signal multiplies by a current signal, United States Patent no 5,949,9, [4] Borgonovo, D., Modeling and Control of Three-Phase PWM Rectifiers, Florianopolis 005, Doctorate Thesis, INEP, UFSC. [5] Remor, J.P., Autocontrole de Corrente Aplicado ao Conversor Boost Monofasico, para Correção de Fator de Potencia, Florianopolis 004, Master Thesis, INEP, UFSC. [6] Torrico-Bascopé, R. P.; Sá JR, E. M.; Branco, C. G. C.; Antunes, F. L. M. PFC Pre-regulator with High Frequency Isolation Using Full- Bridge Chopper for UPS Applications, In: INDUSCN 004 VI Conferência de Aplicações Industriais, Vol. 1, /09/$ IEEE 860