PID Digital Control Applied to a High Voltage Gain Converter with Soft-Switching Cells

Transcription

1 PID Digital Control Applied to a High Voltage Gain Converter with Soft-Switching Cells R.N.A.L. Silva, G.A.L. Henn, P.P. Praça, R.A. da Câmara, L.H.S.C. Barreto, D.S. Oliveira Jr. Energy and Control Processing Group - GPEC / Department of Electrical Engineering / Universidade Federal do Ceará Centro de Tecnologia - Campus do Pici, Bl.705 Fortaleza-CE, Brazil, Phone: lbarreto@dee.ufc.br Abstract - This paper presents the control strategy and the experimental results of a high voltage gain converter with softswitching cell. The PID compensator is digitally implemented using a PIC 6F877 microcontroller, which guarantees the regulation of the output voltage, instead of load variations. Low switching stress, ZCS operation for auxiliary switches and ZVS for main switches, and high efficiency are expected. Theoretical analysis, operation principle and topology details are presented and validated through experimental results. I. INTRODUCTION Different technological applications use many DC voltage levels. In order to obtain these levels, Power Electronics has been developed to obtain new topologies, generating countless circuits that derive from the six basic structures: buck, boost, buck-boost, cúk, sepic, and zeta []. The main characteristic from the boost converters is that the average output voltage is higher than the input one. However, the conventional configurations are not capable to offer such high gain required by some applications, where the output voltage is about five or ten times higher than the input voltage, as by operating with high duty cycle, the converter tends to instability. The challenge to generate an output voltage of 80Vdc to 400Vdc, used as input of inverters, UPS, and another applications, from low input voltage (Vdc to 48Vdc), has been studied for some time, creating different solutions in order to overcome this drawback []. Converters with high static gain based on the boost-flyback topology are presented in [3-5]. The main advantage from this topology is the low switch voltage stress. However, the input current is pulsed, being necessary an LC filter. A high voltage gain converter with switched-capacitor was proposed in [6] and [7], which allow a voltage gain of about three times. However, this structure is only adequate for low power applications, and high voltage stress across the switches results on the use of many capacitors. In [8], the converter presents low input current ripple and voltage stress on the switches. However, high current flows through the series capacitors at high power levels. Topologies of three-state commutation cell have been presented in [9-]. The advantages from [0] are: non-pulsed and low rippled input current, and the doubled frequency operation of the input inductor /0/$ IEEE The presence of an additional switch allows a voltage stress lower than half output voltage, naturally clamped by the output filter capacitor, allowing a low series resistance MOSFET, improving its efficiency. Despite of the good performance, this converter will not work with duty cycle lower than 0.5. In [], the voltage gain is obtained using a voltage multiplier cell. A voltage doubler is used as output stage of an interleaved boost converter with coupled inductors in []. In [3], the converter operates in CCM. The switches S and S can work in ZCS, due to the leakage inductance, and in DCM during the first and the third stages. Instead of the DCM operation of the inductors, the input current keeps continuous. However, for high power loads, the switches do not commutate in ZCS mode. Besides, this converter presents misbalancing between the inductors currents. In general, converters that do not use soft-switching cells have high switching losses, as the switches turn on and off with the whole load current. The continuing search for projects optimization that operates with low conduction or commutation switching losses generates the development of new topologies. The cell presented in [4] guarantees the nondissipative commutation of switches, which allow efficiency improvement and the EMI reduction. Besides, this topology operates with fix frequency. The disadvantage is the need to implement an auxiliary circuit to isolate the auxiliary switch drive pulse. A new active soft-switching cell with the addiction of two auxiliary commutation circuits to the interleaved boost converter was proposed in [5]. The main switches are turned-on in ZCS and turned-off in ZVS mode, while the auxiliary circuit switch do not cause extra voltage on the main switches. Besides, there is no need of adding an extra inductor on the auxiliary circuit. However, the presence of two auxiliary switches makes the circuit complex and hard to be implemented. There is also the presence of circulating current and the increase of conduction losses. A quadratic boost converter associated to a non-dissipative soft-switching cell (BOOST-QPWM-ZCS-SR) is presented in [6]. This converter can operate with large voltage scale and no isolation between the power and the control stages ate required. However, the series association of the switch with the diode increases the conduction losses. 99

2 Ts Ts ton toff VS ton toff Figure. High voltage gain boost converter with soft-switching cell. Digital control has been more and more used recently due to its associated advantages, as low cost, fewer components to be used, and easy control update and adjustment without modifying the hardware. The main focus of this paper is to present the project and the implementation from the digital control of a soft-switching high voltage gain boost converter, shown in Fig. [7]. II. VSa VS VSa Ts Figure 3. Signals from the control circuit. According to Fig. 3: CONTROL STRATEGY A. Voltage Control Loop This section presents the control strategy used in order to guarantee the stability of the converter output voltage, instead of load variations. The block diagram of the voltage loop control is illustrated in Figure. The controller equations are: Vref,5 () H ( s) = = = 0, 0388 Vo 80 V0 = C ( s) Fm G ( s) (Vref Va ) () Where H(s) is the transfer function of the controlled signal transductor, responsible for sampling the output voltage Vo, while Va is its sample and must be adjusted to the reference voltage, Vref. C(s) is the transfer function of the compensator, and is responsible for stabling the closed loop system, which provides the control voltage. Fm is the modulator signal, which converts the control signal into a PWM signal with determined duty cycle, and G(s) is the system transfer function. This technique consists in sampling the output voltage and comparing it to a reference, which generates an error voltage. This error serves as a parameter to the compensator, providing the control voltage, which, after the modulation, provides PWM pulses for driving switches, with adjusted duty cycle for stabling output voltage on the desired level. The obtained signals from the control circuit are presented on Fig. 3. ton = toff ' (3) toff = ton ' (4) ton = D Ts (5) ton ' = ( D ) Ts (6) According to the triangle similarity: Δvc Ts = vc ton ' (7) vc Δvc (8) ton ' = Ts From (4): ton ' = ( D ) Ts (9) vc Δvc (0) From (8) and (9): D = The voltage variation implicates the duty cycle variation: D = () Δvc vc The modulator gain is given by: Fm = Δvc () In order to avoid the phase introduction of -80º, it is considered that the modulator negative signal is cancelled by the signal inversion of the compensator. Thus: Fm = Figure. System block diagram. 993 Δvc (3)

3 B. Compensator Project The compensator project aims to guarantee the system stability. The first step is to determine the transfer function that relations output voltage with duty cycle (4). The same function used for the basic boost converter has been adopted [8-9]. V s in Lb ( D ) R ( D ) 0 G (s) = L C L b Bosst _ eq b s + s + R0 ( D ) ( D ) Figure 5. Bode diagram of the non-compensated system; (a) Gain (b) Phase (4) In order to control the voltage loop, it was chosen a PID compensator. The PID transfer function is given by (). The equivalent capacitor Cfan is the value seen by the source, and it is calculated as follows: CFeq = CF + CF + CF (5) CFeq =, 04mF (6) Following the energy conservation principle: CBoost _ eq VBoost = CFeq VBoostAG CBoost _ eq =, CBoost _ eq = 8,36mF Substituting the projected values in (4): 0, 003 s + 3,3 G( s) =, s +, s + (7) D ω0 = CBoost _ eq Lb (9) f z = f z = (0) () Fig. 5 illustrates the Bode diagram of FTLAsc(s). It can be noticed the small gain in lower frequencies, an inclination higher than -0dB/dec on crossing frequency, and phase margin near of zero. Thus, the non-compensated system tends to instability. () The poles and zeros allocation criterions of the PID compensator are: the zeros must be allocated on the zero frequency of the right semi-plane, assuring an -0dB/dec inclination when crossing the zero of the function: (8) Fig. 4 presents the Bode diagram of the system transfer function (0). It is important to notice that the converter presents a zero on the right semi-plane, which can direct the system to instability. The second step is to calculate the open loop transfer function, FTLAsc(s): FTLAsc ( s ) = G ( s ) Fm H ( s ) s + s + Rc Cb Rb Ca Rc C (s) = Ra R + Rb s s + a Ra Rb Ca ω0 π = 36, 48 Hz (3) (4) One of the poles of C(s) must be allocated in origin, minimizing the static error during the permanent regime, while the other pole is allocated in a frequency ten times higher than the natural system frequency ωo: f p = 0 f p = 0 ω0 = 364, 76 Hz π (5) (6) The crossing frequency is allocated one decade under the zero-crossing frequency on the right semi-plane. f cr = f z = 3, 643Hz 0 (7) f cr 4 Hz (8) The equations that define the compensator parameters are: Kv = f z = f z = Figure 4. Bode diagram of the system transfer function; (a) Gain (b) Phase f p = Rc Ra π Rc Cb Ra + Rb π Ra Rb Ca Substituting the calculated values on equation (): 994 (9) (30) (3)

4 C (s) =,99 s s +,53 05 s + 9 s (3) By making some approximations, the equation to be introduced on the microcontroller is given by: U ( k ) = U ( k ) U ( k ) + The Bode diagram of the open loop transfer function with the compensator, FTLAcc(s), is shown in Fig. 7, where can be observed that the function has a phase margin of 3º and a gain near to -0dB/dec, which has proven to be experimentally stable. C. Digital control project In order to implement the digital control of the proposed system, it is necessary to make the compensator function discrete. To do that, the transfer function must be transferred from the s-plane to the z-plane. Also, it must be added to the system the blocks of the gain relative to the A/D and the D/A converter. Figure 7. Compensated system Bode diagram; (a) Gain; (b) Phase. C ( s ) = GADC Cd ( s ) GDAC (33) Where: GADC = 04b 5V (34) GDAC = 5V 55b (35) Thus: Cd ( s ) = Cd ( s ) = C (s) 4 0, 76 s + 33,8 s + 3, s + 9s (36) (37) In order to convert the compensator transfer function from the s-plane to the z-plane, the software MATLAB was used, by using the Tustin method, with a sample time of 00μs. Cdisc ( z ) = Cdisc ( z ) = U (z) e(z) 0, 688 z,8 z + 0,5646 z, 67 z + 0, 67 (38) (39) The next step is to transform the controller transfer function in state equation form, as follows: U ( k ) =, 67 U ( k ) 0, 67 U ( k ) + +0, 688 e ( k ),8 e ( k ) + 0,5649 e ( k ) 6 e(k ) e ( k ) + e ( k ) 0 0 III. (4) EXPERIMENTAL RESULTS This topic presents the experimental results from the nondissipative snubber commutation cell applied to the high voltage gain converter with digital control. The system has an input voltage of 6 Vdc and output voltage of 80 Vdc, making possible to feed a 0 VRMS AC system. The prototype was assembled to supply a linear 500 W load. Switching frequency is 50 khz. Fig. 9 presents the input and the output voltage when the input is only 6Vdc, and the output is still regulated on 80Vdc, proving the effectiveness of the proposed converter, where a voltage gain of about eleven times is obtained. Fig. 0 presents the voltage and the current waveforms through the main switch S. It can be observed from that Fig. that this switch only starts to conduct in ZVS mode. It is also important to emphasize that the voltage stress through that switch is only Vout/3. Fig. presents the voltage and the current waveforms through the auxiliary switch Sa. It can be noticed that the this switch only starts to conduct in ZCS mode, which verifies the non-dissipative characteristic from the used soft-switching cell. Fig. shows the following waveforms: current through Sa, and the voltages across Cr and Cr. From that Fig., it can be observed the turning-on of Sa; the resonance between Cr and Cr, causing the discharging of Cr and the charging of Cr; and the voltage across Cr reaching zero before the current through Sa disappear. Following, this current reaches zero, turning-off Sa, while Lb starts to be discharged and the voltage across Cr is discharged by ILb until it reaches zero. It must be noticed that the same waveforms are valid to the other soft-switching cell, composed by Sa, Cr3, and Cr4. Fig. 3 shows the behavior of output voltage and current applying a load step from 500W to 50W, where the output voltage suffers an initial rising of 30V (6.67%). Fig. 4 presents the waveforms of output voltage and current for a load step from 50W to 500W, where the output voltage suffers an initial rising of 5V (3.88%). Fig. 5 presents the efficiency curve from the converter operating with and without the soft-switching cell. It must be observed that a high efficiency is achieved from low to nominal power. Also, this figure proves the effectiveness from the soft-switching cell, which has made the converter to work with efficiency around 4% higher than the hardswitching converter. (40) 995

5 Figure. Current through Sa and voltages across Cr and Cr Figure 9. Input and output voltages Figure 3. Output voltage and current under load step from 500W to 50W Figure 0. Voltage and current through the main switch S Figure. Voltage and current through the auxiliary switch Sa Figure 4. Output voltage and current under load step from 50W to 500W 996

6 ,0 0,98 0,96 0,94 0,9 0,9 0,88 0,86 0,84 0,8 0,8 With Cell Without Cell [9] [0] [] Power (W) [] Figure 5. Comparison of the efficiency curve between the converter operating with and without the soft-switching cell [3] IV. CONCLUSION An interleaved boost converter with high voltage gain and non-dissipative soft-switching snubber cell with digital control was presented. The main advantages of the topology are: large voltage step-up, low voltage stress on the switches, low switching losses, and high efficiency. These features make this converter to be far suitable for applications where high voltage gain and great efficiency are expected. The theoretical analysis and model validation from the high voltage gain boost through experimental results is presented, as the ones from the non-dissipative snubber cell, verifying the expected characteristics from the converter. The controller, digitally implemented, proved to be very effective, as it has guaranteed a stable output DC bus on 80V level, as expected, reducing the components used and being very simple to implement. [4] [5] [6] [7] [8] REFERENCES [] [] [3] [4] [5] [6] [7] [8] Mello, L. F. P., Análise e Projeto de Fontes Chaveadas Ed. São Paulo: Érica, 996. G. A. L. HENN, L. H. S. C. BARRETO, D. S. Oliveira Jr., E. A. S. da Silva, A Novel Bidirectional Interleaved Boost Converter with High Voltage Gain, IEEE Applied Power Electronics Conference and Exposition, APEC 008, pp , Feb K. C. Tseng,, T. J. Liang, Novel high-efficiency step-up converter, IEE Proceedings. Electric. Power Applications., vol. 5, no., pp 890, Mar 004. R. J. Wai, R.Y. Duan, High-efficiency DC/DC converter with high voltage gain IEE Proceedings Electronic. Power Applications, vol. 5, no. 4, pp , July 005. J. W. Baek, M. H. Ryoo, T. J. Kim, D. W. Yoo, J. S. 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