12-Bit, Parallel Input DIGITAL-TO-ANALOG CONVERTER

Transcription

1 For most current data sheet and other product information, visit 12-Bit, Parallel Input DIGITAL-TO-ANALOG CONVERTER FEATURES LOW POWER: 2.5mW FAST SETTLING: 7µs to 1 LSB 1mV LSB WITH 4.95V FULL-SCALE RANGE COMPLETE WITH REFERENCE 12-BIT LINEARITY AND MONOTONICITY OVER INDUSTRIAL TEMP RANGE ASYNCHRONOUS RESET TO V APPLICATIONS PROCESS CONTROL DATA ACQUISITION SYSTEMS CLOSED-LOOP SERVO-CONTROL PC PERIPHERALS PORTABLE INSTRUMENTATION DESCRIPTION The is a 12-bit digital-to-analog converter (DAC) with guaranteed 12-bit monotonicity performance over the industrial temperature range. It requires a single +5V supply and contains an input register, latch, 2.435V reference, DAC, and high speed rail-to-rail output amplifier. For a full-scale step, the output will settle to 1 LSB within 7µs. The device consumes 2.5mW (.5mA at 5V). The parallel interface is compatible with a wide variety of microcontrollers. The accepts a 12-bit parallel word, has a double-buffered input logic structure and provides data readback. In addition, two control pins provide a chip select (CS) function and asynchronous clear (CLR) input. The CLR input can be used to ensure that the output is V on power-up or as required by the application. The is available in a 2-lead SSOP package and is fully specified over the industrial temperature range of 4 C to +85 C. V DD Ref 12-Bit DAC 12 CLR LOADDAC DAC Register 12 Input Register CS R/W 12 I/O Buffer D D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D11 DGND International Airport Industrial Park Mailing Address: PO Box 114, Tucson, AZ Street Address: 673 S. Tucson Blvd., Tucson, AZ 8576 Tel: (52) Twx: Internet: Cable: BBRCORP Telex: FAX: (52) Immediate Product Info: (8) SBAS Burr-Brown Corporation PDS-152B Printed in U.S.A. March, 1999

2 SPECIFICATIONS ELECTRICAL At T A = 4 C to +85 C, and V DD = +5V, unless otherwise noted. E EB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 Bits ACCURACY Relative Accuracy (1) 2 ±1/ ±1/4 +1 LSB Differential Nonlinearity Guaranteed Monotonic 1 ±1/ ±1/4 +1 LSB Zero-Scale Error Code H LSB Full Scale Voltage Code FFF H V ANALOG OUTPUT Output Current Code 8 H ±5 ±7 ma Load Regulation R LOAD 42Ω, Code 8 H 1 3 LSB Capacitive Load No Oscillation 5 pf Short-Circuit Current ±2 ma Short-Circuit Duration GND or V DD Indefinite DIGITAL INPUT Data Format Parallel Data Coding Straight Binary Logic Family CMOS Logic Levels V IH.7 V DD V V IL.3 V DD V I IH ±1 µa I IL ±1 µa DYNAMIC PERFORMANCE Settling Time (2) (t S ) To ±1 LSB of Final Value 7 µs DAC Glitch 5 nv-s Digital Feedthrough 2 nv-s POWER SUPPLY V DD V I DD V IH = 5V, V IL = V, No Load, at Code H.5 1 ma Power Dissipation V IH = 5V, V IL = V, No Load mw Power Supply Sensitivity V DD = ±5%.1.4 %/% TEMPERATURE RANGE Specified Performance C Same specification as for E. NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 2

3 PIN CONFIGURATION PIN DESCRIPTIONS Top View SSOP PIN LABEL DESCRIPTION 1 CLR Reset. Resets the DAC register to zero. Active LOW. Asynchronous input. 2 V DD Postive Power Supply 3 DAC Output Voltage CLR V DD AGND DGND DB11 (MSB) DB1 DB9 DB8 DB E LOADDAC CS R/W DB (LSB) DB1 DB2 DB3 DB4 DB5 DB6 4 AGND Analog Ground 5 DGND Digital Ground 6 DB11 Data Bit 11, MSB 7 DB1 Data Bit 1 8 DB9 Data Bit 9 9 DB8 Data Bit 8 1 DB7 Data Bit 7 11 DB6 Data Bit 6 12 DB5 Data Bit 5 13 DB4 Data Bit 4 14 DB3 Data Bit 3 15 DB2 Data Bit 2 16 DB1 Data Bit 1 17 DB Data Bit, LSB 18 R/W Read and Write Control 19 CS Chip Select. Active LOW. 2 LOADDAC Loads the internal DAC register. The DAC register is a transparent latch and is transparent when LOADDAC is LOW (regardless of the state of CS or CLK). ABSOLUTE MAXIMUM RATINGS (1) V DD to GND....3V to 6V Digital Inputs to GND....3V to V DD +.3V to GND....3V to V DD +.3V Power Dissipation mW Thermal Resistance, θ JA C/W Maximum Junction Temperature C Operating Temperature Range... 4 C to +85 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s) C NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MINIMUM RELATIVE DIFFERENTIAL SPECIFICATION PACKAGE ACCURACY NONLINEARITY TEMPERATURE DRAWING ORDERING TRANSPORT PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER (1) NUMBER (2) MEDIA E ±2 ±1 4 C to +85 C 2-Lead SSOP 334 E Rails " " " " " " E/1K Tape and Reel EB ±1 ±1 4 C to +85 C 2-Lead SSOP 334 EB Rails " " " " " " EB/1K Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1 devices per reel). Ordering 1 pieces of E/1K will get a single 1-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. 3

4 TIMING DIAGRAMS CS t WCS t WS twh CS t RCS R/W t LWD R/W t RDS t RDH LOADDAC t DZ t DS t DH Data Out Data Valid Data In t CSD Data Output Timing Digital Input Timing TIMING SPECIFICATIONS T A = 4 C to +85 C SYMBOL DESCRIPTION MIN TYP MAX UNITS t RCS CS LOW for Read 2 ns t RDS R/W HIGH to CS LOW 1 ns t RDH R/W HIGH after CS HIGH ns t DZ CS HIGH to Data Bus 1 ns in High Impedance t CSD CS LOW to Data Bus Valid 1 16 ns t WCS CS LOW for Write 5 t WS R/W LOW to CS LOW ns t WH R/W LOW after CS HIGH 5 ns t DS Data Valid to CS LOW ns t DH Data Valid after CS HIGH 5 ns t LWD LOADDAC LOW 5 ns LOGIC TRUTH TABLE INPUT DAC R/W CS LOADDAC REGISTER REGISTER MODE L L L Write Write Write L L H Write Hold Write Input H L H Read Hold Read Input X H L Hold Update Update X H H Hold Hold Hold X = Don t Care. 4

5 TYPICAL PERFORMANCE CURVES At T A = +25, and V DD = 5V, unless otherwise specified. Output Voltage (V) OUTPUT SWING vs LOAD k 1k 1k Load Resistance (Ω) Delta (mv) PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT 1k 1 85 C (mv) 1 25 C 1 4 C.1 Data = H Current (ma) BROADBAND NOISE SUPPLY CURRENT vs LOGIC INPUT VOLTAGE Noise Voltage (1mV/div) Code = FFF H BW = 2MHz Supply Current (ma) Time (2µs/div) Logic Voltage (V) PSR (db) POWER SUPPLY REJECTION vs FREQUENCY Data = FFF H V DD = 5V ±2mV AC V DD Minimum (V) MINIMUM SUPPLY VOLTAGE vs LOAD V FS = 1 LSB Data = FFF H 1 1 1k 1k 1k 1M Frequency (Hz) Output Load Current (ma) 5

6 TYPICAL PERFORMANCE CURVES (CONT) At T A = +25, and V DD = 5V, unless otherwise specified. Output Current (ma) SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE Positive Current Limit Output Voltage (V) Data = 8 H Output tied to I SOURCE Negative Current Limit Supply Current (ma) SUPPLY CURRENT vs TEMPERATURE V LOGIC = 3.5V Data = FFF H No Load V DD = 5.25V V DD = 5.V.5 V DD = 4.75V Temperature ( C) MID-SCALE GLITCH PERFORMANCE MID-SCALE GLITCH PERFORMANCE LOADDAC LOADDAC (2mV/div) (2mV/div) 7FF H to 8 H 8 H to 7FF H Time (5ns/div) Time (5ns/div) LARGE-SIGNAL SETTLING TIME RISE TIME DETAIL C L = 11pF R L = No Load LD 1V/div LD Output Voltage (1mV/div) Time (2µs/div) Time (1µs/div) 6

7 TYPICAL PERFORMANCE CURVES (CONT) At T A = +25, and V DD = 5V, unless otherwise specified. FALL TIME DETAIL 1. OUTPUT VOLTAGE NOISE vs FREQUENCY Data = FFF H Output Voltage (1mV/div) LD Noise (µv/ Hz) 1..1 Time (1µs/div) k 1k 1k Frequency (Hz) Output Voltage Change (mv) LONG-TERM DRIFT ACCELERATED BY BURN-IN 144 Units min avg max Number of Units TOTAL UNADJUSTED ERROR HISTOGRAM T.U.E = ΣINL = Z S + FS Sample Size = 3 Units T A = +25 C Hours of Operation at +15 C FULL-SCALE VOLTAGE vs TEMPERATURE Avg + 3σ No Load Sample Size = 3 3 ZERO-SCALE VOLTAGE vs TEMPERATURE Full-Scale Output (V) Avg Zero-Scale (mv) Avg 3σ Temperature ( C) Temperature ( C) 7

8 TYPICAL PERFORMANCE CURVES (CONT) At T A = +25, and V DD = 5V, unless otherwise specified. 2. LINEARITY ERROR vs DIGITAL CODE (at +25 C) 2. DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE (at +25 C) Linearity Error (LSBs) Differential Linearity Error (LSBs) Code Code 1 LINEARITY ERROR vs DIGITAL CODE (at +85 C) 1 DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE (at +85 C) Linearity Error (LSBs).5.5 Differential Linearity Error (LSBs) Code Code 1 LINEARITY ERROR vs DIGITAL CODE (at 4 C) 1 DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE (at 4 C) Linearity Error (LSBs).5.5 Differential Linearity Error (LSBs) Code Code 8

9 OPERATION The is a 12-bit digital-to-analog converter (DAC) complete with an input shift register, DAC register, lasertrimmed 12-bit DAC, on-board reference, and a rail-to-rail output amplifier. Figure 1 shows the basic operation of the. INTERFACE Figure 1 shows the basic connection between a microcontroller and the. The interface consists of a Read/Write (R/W), data, and a load DAC signal (LOADDAC). In addition, a chip select (CS) input is available to enable the when there are multiple devices. The data format is Straight Binary. An asynchronous clear input (CLR) is provided to simplify start-up or periodic resets. Table I shows the relationship between input code and output voltage. Full-Scale Range = 4.95V Least Significant Bit = 1mV DIGITAL INPUT CODE ANALOG OUTPUT STRAIGHT OFFSET BINARY (V) DESCRIPTION FFF H Full Scale 81 H Midscale + 1 LSB 8 H Midscale 7FF H Midscale 1 LSB H Zero Scale TABLE I. Digital Input Code and Corresponding Ideal Analog Output. The digital data into the is double-buffered. This means that new data can be entered into the DAC without disturbing the old data and the analog output of the converter. At some point after the data has been entered into the serial shift register, this data can be transferred into the DAC register. This transfer is accomplished with a HIGH to LOW transition of the LOADDAC pin. However, the LOADDAC pin makes the DAC register transparent. If new data becomes available on the bus register while LOADDAC is LOW, the DAC output voltage will change as the data changes. To prevent this, CS must be returned HIGH prior to changing data on the bus. At any time, the contents of the DAC register can be set to H (analog output equals V) by taking the CLR input LOW. The DAC register will remain at this value until CLR is returned HIGH and LOADDAC is taken LOW to allow the contents of the input register to be transferred to the DAC register. If LOADDAC is LOW when CLR is taken LOW, the DAC register will be set to H and the analog output driven to V. When CLR is returned HIGH, the DAC register and the analog output will respond accordingly. DIGITAL-TO-ANALOG CONVERTER The internal DAC section is a 12-bit voltage output device that swings between ground and the internal reference voltage. The DAC is realized by a laser-trimmed R-2R ladder network which is switched by N-channel MOSFETs. The DAC output is internally connected to the rail-to-rail output operational amplifier. E Clear 1 CLR LOADDAC 2 Load DAC +5V + 1µF.1µF V to +4.95V V DD AGND CS R/W DB Chip Select Read/Write 5 DGND DB DB11 DB1 DB2 DB Data Bus Data Bus 8 DB9 DB DB8 DB DB7 DB6 11 FIGURE 1. Basic Operation of the. 9

10 R-2R DAC 2R Output Amplifier Bandgap Reference 2.435V Buffer 2R 2R R R R 1 R 2 R 2R 2R FIGURE 2. Simplified Schematic of Analog Portion. OUTPUT AMPLIFIER A precision, low-power amplifier buffers the output of the DAC section and provides additional gain to achieve a V to 4.95V range. The amplifier has low offset voltage, low noise, and a set gain of 1.682V/V (4.95/2.435). See Figure 2 for an equivalent circuit schematic of the analog portion of the. The output amplifier has a 7µs typical settling time to ±1 LSB of the final value. Note that there are differences in the settling time for negative-going signals versus positivegoing signals. The rail-to-rail output stage of the amplifier provides the full-scale range of V to 4.95V while operating on a supply voltage as low as 4.75V. In addition to its ability to drive resistive loads, the amplifier will remain stable while driving capacitive loads of up to 5pF. See Figure 3 for an equivalent circuit schematic of the amplifier s output driver and the Typical Performance Curves section for more information regarding settling time, load driving capability, and output noise. P-Channel V DD POWER SUPPLY A BiCMOS process and careful design of the bipolar and CMOS sections of the result in a very low power device. Bipolar transistors are used where tight matching and low noise are needed to achieve analog accuracy, and CMOS transistors are used for logic, switching functions and for other low power stages. If power consumption is critical, it is important to keep the logic levels on the digital inputs (R/W, CLK, CS, LOADDAC, CLR) as close as possible to either V DD or ground. This will keep the CMOS inputs (see Supply Current vs Logic Input Voltages in the Typical Performance Curves) from shunting current between V DD and ground. The power supply should be bypassed as shown in Figure 1. The bypass capacitors should be placed as close to the device as possible, with the.1µf capacitor taking priority in this regard. The Power Supply Rejection vs Frequency graph in the Typical Performance Curves section shows the PSRR performance of the. This should be taken into account when using switching power supplies or DC/DC converters. In addition to offering guaranteed performance with V DD in the 4.75V to 5.25V range, the will operate with reduced performance down to 4.5V. Operation between 4.5V and 4.75V will result in longer settling time, reduced performance, and current sourcing capability. Consult the V DD vs Load Current graph in the Typical Performance Curves section for more information. N-Channel AGND FIGURE 3. Simplified Driver Section of Output Amplifier. 1

11 APPLICATIONS POWER AND GROUNDING The can be used in a wide variety of situations from low power, battery operated systems to large-scale industrial process control systems. In addition, some applications require better performance than others, or are particularly sensitive to one or two specific parameters. This diversity makes it difficult to define definite rules to follow concerning the power supply, bypassing, and grounding. The following discussion must be considered in relation to the desired performance and needs of the particular system. A precision analog component requires careful layout, adequate bypassing, and a clean, well-regulated power supply. As the is a single-supply, +5V component, it will often be used in conjunction with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance. The has separate analog ground and digital ground pins. The current through DGND is mostly switching transients and are up to 4mA peak in amplitude. The current through AGND is typically.5ma. For best performance, separate analog and digital ground planes with a single interconnection point to minimize ground loops. The analog pins are located adjacent to each other to help isolate analog from digital signals. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. A solid analog ground plane around the D/A package, as well as under it in the vicinity of the analog and power supply pins, will isolate the D/A from switching currents. It is recommended that DGND and AGND be connected directly to the ground planes under the package. If several s are used, or if sharing supplies with other components, connecting the AGND and DGND lines together at the power supplies once, rather than at each chip, may produce better results. The power applied to V DD should be well regulated and lownoise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between V DD and. As with the GND connection, V DD should be connected to a +5V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1µF and.1µf capacitors shown in Figure 4 are strongly recommended and should be installed as close to V DD and ground as possible. In some situations, additional bypassing may be required such as a 1µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors all designed to essentially lowpass filter the +5V supply, removing the high frequency noise (see Figure 4). +5V Power Supply +5V Digital Circuits +5V GND GND 1µF + + 1µF.1µF V DD AGND Optional Other Analog Components DGND FIGURE 4. Suggested Power and Ground Connections for a Sharing a +5V Supply with a Digital System with a Single Ground Plane. 11

12 PACKAGE OPTION ADDENDUM 25-Dec-215 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan E ACTIVE SSOP DB 2 7 Green (RoHS & no Sb/Br) E/1K ACTIVE SSOP DB 2 1 Green (RoHS & no Sb/Br) E/1KG4 ACTIVE SSOP DB 2 1 Green (RoHS & no Sb/Br) EB ACTIVE SSOP DB 2 7 Green (RoHS & no Sb/Br) EB/1K ACTIVE SSOP DB 2 1 Green (RoHS & no Sb/Br) EBG4 ACTIVE SSOP DB 2 7 Green (RoHS & no Sb/Br) EG4 ACTIVE SSOP DB 2 7 Green (RoHS & no Sb/Br) (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CU NIPDAU Level-3-26C-168 HR -4 to 85 E CU NIPDAU Level-3-26C-168 HR -4 to 85 E CU NIPDAU Level-3-26C-168 HR -4 to 85 E CU NIPDAU Level-3-26C-168 HR -4 to 85 E B CU NIPDAU Level-3-26C-168 HR -4 to 85 E B CU NIPDAU Level-3-26C-168 HR -4 to 85 E B CU NIPDAU Level-3-26C-168 HR -4 to 85 E Device Marking (4/5) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

13 PACKAGE OPTION ADDENDUM 25-Dec-215 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

14 PACKAGE MATERIALS INFORMATION 15-Sep-217 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A (mm) B (mm) K (mm) P1 (mm) W (mm) Pin1 Quadrant E/1K SSOP DB Q1 EB/1K SSOP DB Q1 Pack Materials-Page 1

15 PACKAGE MATERIALS INFORMATION 15-Sep-217 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) E/1K SSOP DB EB/1K SSOP DB Pack Materials-Page 2

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