DESCRIPTION APPLICATIONS. Ground, +1.8V, +3.3V. Control Inputs. TEPro. Channelized DS3 Access Device TXC Host interface

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1 Device Channelized DS3 Access Solution FEATURES Complete single-chip channelized DS3 solution RISC processor with royalty-free DD-AMPS firmware (Drivers, Data link, Alarms, Messaging, Performance/configuration objects, and Signaling) Host communication via royalty-free, messagebased, POSIX-compatible API Integrated 672 DS0 x 4,096 time slot cross connect supports grooming, broadcast, off-bus hairpinning, and bonding Integrated DS1/E1 cross connect Integrated G.747 function to Mux/De-Mux 21 E1s to/from DS3. 28 DS1 or 21 E1 line interfaces or 1 DS3 line interface Combination of unframed DS1/E1, transmission DS1/E1, link channel interface (LCI), and either MVIP or H.100/H.110 as terminal side interfaces Selectable DS3 clear channel functionality On-chip maintenance of 15-minute performance objects per IETF RFCs 2495, 2496, and Supports 56 raw HDLC,* 2 SS7,* or 28 ISDN-PRI* signaling channels (*Future firmware + API release) Two DS1/E1 monitor ports for monitoring any DS1/E1 clock and data Test Access Port (IEEE boundary scan) +3.3 volt input/output leads, +5 volt tolerant +3.3 volt and +1.8 volt power supplies 456-lead plastic ball grid array package (27 mm x 27 mm); pin- and API-compatible with T3BwP (TXC-06826) DESCRIPTION () is a system-on-chip (SoC) device that supports the requirements of next-generation channelized DS3 access systems. integrates an M13 multiplexer, G.747 Mux/De-Mux framer, 28 DS1 / 21 E1 framers, T1/E1 cross connect and a 672 DS0 x 4,096 time slot cross connect with an embedded high-performance microprocessor to provide a complete channelized DS3 solution on a single chip. The embedded processor firmware handles device drivers, data links, alarms, messaging, MIB performance objects, and signaling functions and allows communication to an external host via high-level API messages. Embedded firmware is provided by TranSwitch and loaded from an external serial EEPROM at device boot-up. Host API source code is also provided by TranSwtich. can be configured to support a variety of modes of operation, which allows for design flexibility. supports a combination of unframed DS1/E1, transmission DS1/E1 and H.100/H.110 bus or MVIP interfaces on the terminal side and either DS3 or DS1/E1 on the line side. For TDM applications, all 672 DS0 channels can be switched to any of the 4,096 H.100/H.110 bus time slots. can also be enabled to provide DS3 C-bit parity for unchannelized services. The on-chip firmware provides the control and management plane functionality to the host to configure, control and monitor all DS3, DS1, E1, DS0 and digital cross connect functions. The standards-based MIB functionality is provided for network management. APPLICATIONS T-carrier termination equipment: muxes, inverse muxes, cross connects, groomers CT (Computer Telephony) network interface boards VoP (Voice over Packet/Cell) gateways MSADs (Multi-Service Access Devices) DSLAMs (Digital Subscriber Loop Access Multiplexers) ECUs (Echo Cancellation Units) Proprietary TranSwitch Corporation Information for use Solely by its Customers LINE SIDE DS1/E1/DS3 interface, LIU control & Indication Ground, +1.8V, +3.3V Boot EEPROM JTAG clock, and data Test Access Port US Patent No. 5033,064; 5,040,170; 5,289,507; 5,615,237; 6,456,595 US and foreign Patients issued or pending Copyright 2003 TranSwitch Corporation is a trademark of TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation MVIP is a registered trademark of GO-MVIP, Inc. SLC is a registered trademark of AT&T 145 DS1/E1 Monitor Port Control Inputs Channelized DS3 Access Device Host interface 175 TERMINAL SIDE Transmission, Unframed DS1/E1 MVIP, H.100/H.110, LCI Document Number: -MB, Ed. 3 TranSwitch Corporation 3 Enterprise Drive Shelton, Connecticut Tel: Fax: USA information documents contain information on products in their formative or design phase of development. Features, characteristic data and other specifications are subject to change. Contact TranSwitch Applications Engineering for current information on this product.

2 Proprietary TranSwitch Corporation Information for use Solely by its Customers TABLE OF CONTENTS Section Page List of Figures... 3 List of Tables... 3 Overview... 4 Standard Documents... 7 TranSwitch Documents... 7 Features... 8 Line Side DS3 Interface... 8 Line Side 28 DS1 or 21 E1 Interfaces... 8 Terminal Side Interfaces and Cross Connect Functionality... 8 On-Chip RISC Processor and Firmware... 9 Host Software... 9 General... 9 Multi-Channel HDLC Microprocessor Interface Other Lead Diagram Lead Descriptions Absolute Maximum Ratings and Environmental Limitations Thermal Characteristics Power Requirements Input, Output and Input/Output Parameters Timing Characteristics Operation Line Interface Port System Ports DS1 Cross connect DS0 Time Slot Interchange (TSI) Link Channel Interface (LCI) DS3 C-bit Interface Service DART Control Port PRBS Generator and Analyzer DS0 Remote Loopback DS1 Monitor Port Multi-Channel HDLC (Future Firmware + API release for 64 Mode) Microprocessor Interface Clock and Framing Pulse Input/Output Leads Hardware Reset Firmware Reset Initial State of System Interface Output Leads JTAG Background Information Firmware/Software Architecture Overview Applications Package Information Ordering Information Related Products Standards Documentation Sources List of Data Sheet Changes * Please note that TranSwitch provides documentation for all of its products. Current editions of many documents are available from the Products page of the TranSwitch Web site at Customers who are using a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. -MB, Ed. 3-2 of 104 -

3 Proprietary TranSwitch Corporation Information for use Solely by its Customers LIST OF FIGURES Figure Page 1 High Level Block Diagram lead Plastic Ball Grid Array Package Lead Diagram DS3 Receive Timing DS3 Transmit Timing DS1/E1 NRZ Receive Interface Timing (External Transceiver) DS1/E1 NRZ Transmit Interface Timing (External Transceiver) Receive Highway Timing - Transmission Mode (Recovered Receive Line Clock) Receive Highway Timing - Transmission Mode (System Clock) Transmit Highway Timing - Transmission Mode Receive Highway Timing - MVIP Mode Transmit Highway Timing - MVIP Mode H.100/H.110 Data Bus Timing DS3/NxDS0 Clear Channel Tx Direction Timing DS3/NxDS0 Clear Channel Rx Direction Timing Read Instruction Timing for Serial EEPROM Interface MHz/2 MHz Clock and 8 khz Framing Pulse Monitor Interface Timing DS3 LIU LCV and EXZ Timing C-Bit Receive Interface Timing C-Bit Transmit Interface Timing Boundary Scan Timing Master Mode: Intel Microprocessor Write/Read Timing Master Mode: Motorola Microprocessor Write/Read Timing Master Mode: A/D Mux Write/Read Timing Slave Mode: Intel Microprocessor Read Cycle Timing Slave Mode: Intel Microprocessor Write Cycle Timing Slave Mode: Motorola Microprocessor Read Cycle Timing Slave Mode: Motorola Microprocessor Write Cycle Timing Slave Mode: A/D Mux Write/Read Timing - Intel Mode Slave Mode: A/D Mux Write/Read Timing - Moto Mode System Interface Framing Format for DS1 Transmission Mode System Interface Framing Format for E1 Transmission Mode System Interface Format for DS1 MVIP Mode System Interface Format for E1 MVIP Mode Data and Signaling Highways - 8 Mbit/s H.100/H.110 Mode Example of System Port Assignment DS0 Remote Loopback Code Sequence Generator Boundary Scan Top-Level Block Diagram Software/Hardware Interaction for Software Interfaces Telephony Application Using the Complete DS3 Remote Access Concentrator Using the Lead Plastic Ball Grid Array Package LIST OF TABLES Table Page 1 Operation Mode Setup for Line Port Lead Assignment of Line Ports T1 Signaling State Signaling Mapping to/from the Signaling Highway Lead Assignment of System Port of MB, Ed. 3

4 Proprietary TranSwitch Corporation Information for use Solely by its Customers OVERVIEW is a highly integrated System-on-Chip (SoC) solution for supporting the requirements of nextgeneration channelized DS3 access systems. An integrated M13 multiplexer, G.747 Mux/De-Mux block, DS1 framers, DS1/E1 and DS0 cross connects, and a high-performance RISC processor with embedded firmware provided by TranSwitch make a complete channelized DS3 solution. The on-chip processor for is controlled by the host via a high-level message-based API (Application Program Interface), reducing the software integration effort and providing flexibility to address feature enhancements and standards changes through firmware upgrades. The on-chip firmware provides the control and management plane functionality to the host to configure, control, and monitor the DS3, DS1/E1, DS0, and cross connect functions. The standards-based MIB object functionality is provided for network management. 28 DS1/21 E1 Line Interfaces DS3 Lines Interface DART Control port DS3/DS1/E1 Line Interfaces DS1/E1 DS 3 DS3 LIU Control M13/ G /21 DS1/E1 Framer * * DS1/E1 cross Connect DS0 cross Connect Control Memory System Interfaces 28 DS1 / 21 E1, Unframed, Transmission, MVIP, H.100/H.110, LCI TXC Microprocessor Bus Microprocessor Interface Microprocessor Interface Mail Box Link Manager Processor EEPROM Interface JTAG Interface DS1/E1 Line Monitoring Control Modes Serial EEPROM JTAG DS1 Line Monitoring Control Leads Figure 1. High Level Block Diagram Figure 1 shows the block diagram for. The main blocks shown are: M13/G.747, DS1/E1 Framer, Serialto-Parallel converter, DS1/E1/DS0 cross connect, and Link Manager processor (LMPro). External interfaces include 28 terminal side system interface ports (supporting H.100/H.110, MVIP, transmission, link channel interface, and unframed modes), 28 DS1/21 E1 line side ports or one DS3 line side port, a serial EEPROM interface for firmware and initial configuration data, a local microprocessor bus used to control external devices, two monitor ports to monitor any two DS1s/E1s, a control port to control the TranSwitch DART DS3 LIU, and a JTAG port for test access. For channelized DS3 applications, the DS1/E1 framer line side ports are M13/G.747 multiplexed to the DS3 line port; the terminal side DS1/E1 ports may individually be used for direct M13/G.747 access. -MB, Ed. 3-4 of 104 -

5 Proprietary TranSwitch Corporation Information for use Solely by its Customers The M13/G.747 framer/multiplexer block is similar to the TranSwitch M13X DS3/DS1 mux/demux device (TXC-03305) with additional G.747 functionality. The DS3 framer provides M frame and M sub-frame framing with AIS and LOS detection; DS3 loopbacks; and access to the C-bits with processing of the FEAC channel (C3), PMDL path maintenance data link (full duplex HDLC controller over C13, C14 and C15), and FEBE (C10, C11 and C12). DS3 X-bit access, loss of signal, loss of frame, AIS, idle, C-bit parity (C7, C8 and C9) and P-bit parity are detected and generated. This block can operate in M13 mode or in a mode where the 21 C-bits are used for stuff control of the 7 DS2s. DS2 framing (7 instances) is provided either all at a fixed rate (C-bit parity mode at kbit/s) or M13 mode. Each DS2 framer and multiplexer handles four DS1 signals. DS1 loss of signal and DS1 loopbacks are provided under control of the FEAC channel or the DS2 stuff control bits (C-bits). 7 G.747 blocks are provided each with a G.747 frame (6.312 Mbit/s signal) input and 3 outgoing E1 tributaries. The transmit DS1/E1 signals are multiplexed directly from the DS1/E1 framer blocks. The receive DS1/E1 signals are demultiplexed and fed to the DS1 framer blocks via a dejitter buffer or with demultiplexing jitter, depending on application. The DS1/E1 framer block is a TranSwitch IP core similar to the TranSwitch T1Fx8 octal T1 framer device (TXC-03108) and E1Fx8 octal E1 framer device (TXC-03109). Automatic performance report message generation, automatic SF/ESF detection, trunk conditioning, deep FDL slip buffers, one-second shadow registers, and interrupt on signaling change-of-state are accomplished by the RISC processor. Framing is provided to the DS1/E1 line ports or the M13. Alarm detection/generation, CAS/RBS signaling debounce and access/insertion/extraction, slip buffering, facility data link (FDL) support, and diagnostic support using loopbacks/prbs generator/analyzer, etc., are provided. The terminal side supports MVIP, H.100/H.110, transmission, LCI, and unframed modes with clock, frame, data, and signaling leads. Common clock and frame signals are provided in MVIP and H.100/H.110 modes. DS1/E1 line access is provided using NRZ coding. The control of the TranSwitch DART DS3 LIU is fully supported in hardware and software. The Link Manager RISC processor (LMPro) performs the following control and management plane functions: 1. Host interface using internal or external message queues 2. Device initialization, configuration, and control 3. Alarm detection and propagation 4. Far end alarm generation 5. Performance monitoring of near end and far end at DS1/E1 and DS3 rates 6. Performance reporting for near and far end (e.g., DS1 PRMs in ESF mode, DS3 FEBE in C-bit parity mode) 7. Execution of maintenance and diagnostic requests from host or far end (e.g., loopbacks) 8. Maintenance of configuration and 15-minute performance MIB objects The flexible architecture supports a variety of modes of operation determined by the firmware provided with the device. supports a combination of unframed DS1/E1, transmission DS1/E1, LCI, and H.100/H.110 or MVIP system interfaces on the terminal side. The line side interface is either DS3, which interfaces directly with a DS3 LIU such as the TranSwitch DART (TXC-02030), or DS1/E1, which interfaces directly with a DS1/E1 LIU or an AAL1/2 device such as the TranSwitch COBRA (TXC-05427C). The can also provide C-bit parity unchannelized service at a Mbit/s rate. The integrated TSI (time slot interchange) allows for grooming, concentration, switching, and multiplexing, internal hairpinning, bonding, and broadcast. When configured in MVIP mode, any of the 672 DS0 channels can be switched to any two time slots across all MVIP highways. When configured in H.100/H.110 mode, any of the 672 DS0 channels can be switched to any two time slots across all H.100/H.110 highways. This allows for multiple s and other H.100/H.110 devices to be interconnected via a single H.100/H.110 bus. - 5 of MB, Ed. 3

6 Proprietary TranSwitch Corporation Information for use Solely by its Customers The can switch any line side DS1/E1 to any terminal side DS1/E1 via the DS1/E1 cross connect when configured in unframed mode or transmission mode. The provides multiple flexible data signal paths between line-side and terminal-side port interfaces: Data flow from DS3 line to DS1/E1 terminal port (H.100/H.110, MVIP, LCI, and transmission modes): DS3 Line <--> M13/G.747 <--> DS1/E1 Framer <--> Cross Connect <--> DS1/E1 Terminal Port Data is received and transmitted using the DS3 line port. The M13/G.747 multiplexes/demultiplexes DS1/E1 signals from/to the 28 DS1 or 21 E1 framers. The data can be switched using either the DS1/E1 or DS0 cross connect depending on the terminal side interface mode selected. Data flow from DS3 line to DS1/E1 terminal port bypassing DS1/E1 framer (unframed mode): DS3 Line <--> M13/G.747 <--> Cross Connect <--> DS1 Terminal Port Data is received and transmitted using the DS3 line port. The M13/G.747 multiplexes/demultiplexes data from/to the 28 DS1s to 21 E1s. The DS1/E1 signals bypass the DS1/E1 framer in unframed mode. The DS1s/E1s are switched using the DS1/E1 cross connect. When the DS1/D1 bypass mode is selected, the DS1/E1 performance monitoring function is also fully supported in the Rx direction. Data flow from DS1/E1 line to DS1/E1 terminal port (H.100/H.110, MVIP, LCI, and transmission modes): DS1/E1 Line <--> DS1/E1 Framer <--> Cross Connect <--> DS1/E1 Terminal Port Data is received and transmitted using the 28 DS1 or 21 E1 line ports. The M13/G.747 block is bypassed. Each DS1/E1 signal is transmitted/received via the DS1/E1 framers. The data can be switched using either the DS1/E1 or DS0 cross connect depending on the terminal side interface mode selected. Data flow from DS1/E1 line to DS1/E1 terminal port bypassing the DS1/E1 framer (unframed mode): DS1/E1 Line <--> Cross Connect <--> DS1/E1 Terminal Port Data is received and transmitted using the 28 DS1 line ports. The M13/G.747 block is bypassed. The DS1/E1 signals bypass the DS1/E1 framer in unframed mode. The DS1s/E1s are switched using the DS1/E1 cross connect. When the DS1/D1 bypass mode is selected, the DS1/E1 performance monitoring function is also fully supported in the Rx direction. Data flow from DS3 line to DS3 clear channel terminal port: DS3 Line <--> M13 <--> DS3 clear channel terminal port The data are received and transmitted using the DS3 line port. When this function is enabled, the data are transmitted via the M13 in clear channel mode (framing and C-bits only) at a Mbit/s rate. The T1/E1 framers are bypassed. The is pin-to-pin compatible to T3BwP device. The addition function offered in are: E1 support G.747 support: mux/de-mux 21 E1 s to/from DS3 The microprocessor can be operated either in master mode or slave mode with integrated mail box Supports raw HDLC, ISDN-PRI, and SS7 message-based signaling at layers 1 and 2 (future firmware + API release) Transmission mode - The Rx clock and frame pulse can be either output or input - Frame pulse period can be either 3 msec or 9 msec. The is configured, controlled, and monitored via a message-based, POSIX-compatible host API. Source code and a portation guide are provided by TranSwitch. IEEE Boundary Scan is provided, with BYPASS, IDCODE, EXTEST and SAMPLE/PRELOAD instructions. -MB, Ed. 3-6 of 104 -

7 Proprietary TranSwitch Corporation Information for use Solely by its Customers STANDARD DOCUMENTS The device has been designed to meet the latest industry standards. ANSI T , Digital Hierarchy - Electrical Interfaces. ANSI T , Digital Hierarchy - Format Specifications. ANSI T , Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring. ANSI T CORE 1998, Network and Customer Installation Interfaces - DS1 Electrical Interface. ANSI T , Network-to-Customer Installation- DS3 Metallic Interface Specification. AT&T PUB 62411, Accunet T1.5 Service Description and Interface Specification. AT&T PUB 54016, Requirements for Interfacing Digital Terminal Equipment To Services Employing the Extended Superframe Format, Sept Bellcore (Telcordia) TR-TY , Digital Interface Between the SLC 96 Digital Loop Carrier System and a Local Digital Switch. GR-499-CORE, Transport Systems Generic Requirements (TSGR): Common Requirements, (Issue 1, Dec. 1995). IEEE Standard Test Access Port and Boundary-Scan Architecture, May MVIP, H-MVIP Multi-Vendor Integration Protocol. Working Document, April Enterprise Computer Telephony Forum, H.100/H.110 Rev. 1.0 Hardware Compatibility Spec. CT Bus. ITU-T O.151 Error Performance Measuring Equipment Operating at the Primary Rate and Above. 10/92. ITU-T O.152 Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and Nx64 kbit/s ITU-T G.703 Physical/Electrical Characteristics of Hierarchical Digital Interface, 1993 ITU-T G.704 Synchronous Frame Structures Used at Primary and Secondary Hierarchical Levels, 1988 and 1991 ITU-T G.706 Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G , 1991 and ITU-T G.711 Pulse Code Modulation (PCM) of Voice Frequencies, ITU-T G.735 Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s and Offering Synchronous Digital Access at 384 kbit/s and/or 64 kbit/s. ITU-T G.747 Second Order Digital Multiplex Equipment operating at 6312 kbit/s and Multiplexing Three Tributaries at 2048 kbit/s, 1988 ITU-T G.775 Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria ITU-T G.823 The Control of Jitter and Wander within Digital Networks Which are Based on the 2048 kbit/s Hierarchy ITU-T I.431and Amendment 1 ISDN User-Network Interfaces. Primary Rate User-Network Interface - Layer 1 Specification with Amendment of TRANSWITCH DOCUMENTS API User s Reference Guide Portation Guide - 7 of MB, Ed. 3

8 Proprietary TranSwitch Corporation Information for use Solely by its Customers FEATURES The device includes the following features: LINE SIDE DS3 INTERFACE M13 block provides all of the functionality found in the TranSwitch M13X device (TXC-03305) and adds G.747 muxing capability DART LIU control port - Provides control to the TranSwitch DART (TXC-02030) LIU device Framing and C-bit support for unchannelized (cell/packet) traffic at Mbit/s rate. LINE SIDE 28 DS1 OR 21 E1 INTERFACES Includes Tx and Rx Data (NRZ), Tx and Rx Clock, and Rx BPV or LOS. TERMINAL SIDE INTERFACES AND CROSS CONNECT FUNCTIONALITY Integrated DS0 TSI allows for grooming, concentration, multiplexing, internal hairpinning, bonding, broadcast, and switching of any DS0 to any two TDM bus (MVIP or H.100/H.110) time slots. A time slot written in frame N is read back out in frame N+1. Integrated DS1/E1 cross connect - Any line side DS1/E1 may be switched to any terminal side DS1/E1 when configured in unframed mode or transmission mode. DS1/E1 terminal port - Unframed Mode - DS1 Transmission Mode: - Rx clock and Rx frame pulse can be either output or input - Framing pulse period can be either 3 msec or 9 msec - Through DS1 cross connect; bypass DS0 TSI - E1 Transmission Mode: - Rx clock and Rx frame pulse can be either output or input MHz plus 2 msec multi-frame pulse for E1 - Through DS1 cross connect; bypass DS0 TSI - MVIP Mode: - Through DS0 TSI MHz plus 125 µs frame pulse - H.100/H Through DS0 TSI MHz plus 125 µs frame pulse Terminal ports can be configured to operate in unframed DS1/E1, transmission DS1/E1, LCI, and either H.100/H.110 or MVIP TDM bus modes H.100/H.110 operation as bus slave - Edge error and frame error detection - Bus clock source selection, monitoring, and automatic switching - Hardware and software support for hot-swap per PICMG 2.1 R1.0 -MB, Ed. 3-8 of 104 -

9 Proprietary TranSwitch Corporation Information for use Solely by its Customers ON-CHIP RISC PROCESSOR AND FIRMWARE RISC processor-based SoC with embedded DD-AMPS (Drivers, Data link, Alarms, Messaging, Performance/configuration objects, and Signaling) firmware On-chip maintenance of configuration and 15-minute performance MIB objects per IETF RFCs 2495, 2496, and 2494 Firmware and default configuration loaded via serial EEPROM interface HOST SOFTWARE High-level message-based, POSIX-compatible API host interface Support for standard MIBs Source code and portation guide provided by TranSwitch upon request GENERAL Boundary scan +3.3 volt input/output circuit power supply, +1.8V core power supply +3.3 volt input/output leads, +5 volt tolerant Maximum power dissipation of 2.1 Watts 456-lead PBGA (27 mm x 27 mm) package Maintenance: DS3 local loopback and remote line loopback via the TranSwitch DART device DS1/E1 remote line and payload loopback and DS1 local loopback NxDS0 channel loopback, NxDS0 local loopback NxDS0 remote loopback: detect loop-up (Fractional DS1 (2 7-1)) / loop-down (Fractional DS1 (2 7-1) inverted) sequences; setup/remove NxDS0 channel loopback according to loop-up/loop-down sequences; initiate loop-up/loop-down sequence Pseudo-Random Binary Sequence (PRBS) generator and analyzer - PRBS generator and analyzer per DS1 line: QRSS (2 20-1); ; ; PRBS generator and analyzer for either NxDS0 or DS3: ; QRSS (2 20-1); ; ; 32-bit code word - Indicator for lock, out of lock. - OOL counter The following features are independently selectable for each of the DS1/E1 framers: Framing Modes: Bypass mode For E1 channels: ITU-T G.706 ( 91) frame alignment detection and loss of alignment declaration Thirty-two 64 kbit/s time slots Basic Frame structure per ITU-T G.704 Time-Slot 0 (TS0)/CRC-4 Multiframe per ITU-T G Two Frame Alignment Signal (FAS) selectable algorithms (Standard and Frame Hold-off; - 9 of MB, Ed. 3

10 Proprietary TranSwitch Corporation Information for use Solely by its Customers G.704/G.706) - CRC-4 Generation/Check - CRC-4 and non CRC-4 multiframing manual (G.706 and ETSI ) and automatic (TBR 4 and ITAAB) interworking - Re-frame on Excessive CRC Errors (>914 per second) Programmable Frame Synchronization - Transparent, CRC-4 disabled, CRC-4 enabled, CRC-4 enabled with E bit alarms - I.431 E bit support option. TS16/Signaling Multiframe synchronization and alarm - Two selectable algorithms (Standard and Enhanced) Programmable Out of Frame Control - 3 or 4 FAS in error, 3 FAS/3 NFAS - or 4 FAS/ 4 NFAS in error Full ETSI compliant automatic alarm gen Full ETSI compliant National bit support (future firmware + API release) For T1 channels: D4 SF (Superframe Format) framing based on Ft-only, Fs-only, or both Fs and Ft frame bits ESF (Extended Superframe Format) framing based on FPS bits with or without a valid CRC-6 SLC-96 SF mode supported Option for automatic SF (Fs and Ft)/ ESF (FPS and CRC-6) framing pattern search Programmable out of frame control: 2 out of 4, 5, or 6 frame bits For J1 channels: Full implementation of standards (JT 704, JT 707) Line Code: NRZ: Clock edge, clock in/out selection, and data inversion options Receive/Transmit Dejitter Buffers: 64-bit with bypass option For E1 Channels: Meets ITU G.823 jitter tolerance, G.735/6 for jitter generation, and G.735/6/8/9 for jitter transfer For T1 Channels: Meets ATT PUB and GR 499 Signaling: E1: Common Channel Signaling (CCS) - Time Slot 16 -MB, Ed of 104 -

11 Proprietary TranSwitch Corporation Information for use Solely by its Customers Channel Associated Signaling (CAS) in time slot 16 - with signaling bits inversion option of transmit or receive substitution (sent as 1111) option to prevent transmitting mimics of TS16 multiframe pattern DS1: A, AB (SF) A, AB, ABCD (ESF) 9-state mode A, AB, 9-state AB signaling for ANSI T.403 Rob or SLC-96 applications (SF) Signaling Access and Processing: Manipulation of signaling bits - Per time slot/ds0 individual signaling freeze option - Microprocessor read and substitute capability for trunk conditioning - Rx and Tx independent control - Per time slot/ds0 enable with read and substitution in both Rx and Tx direction for call control and trunk conditioning E1/T1 Signaling Freeze on LOS, LOMF, OOF and Line AIS Signaling debounce option (programmable number of multiframes) Signaling change of state interrupt and activity register indication Clock Management: Use any of three reference clocks: BITS, local stratum, one of twenty-eight recovered T1/E1 clocks Terminal-side and line-side clocks on Rx and Tx, each independent Transmit and Receive Slip Buffers: Full frame (30 or 31 time slots depending on CAS or CCS operation plus time slot 0 and 24 DS0 plus framing bit) storage with bypass option Two frame slip buffers for each of receive and transmit paths, with independent bypass Per DS0 enable (independent receive and transmit) with microprocessor read and substitution in both receive and transmit directions Per DS0 inversion in transmit and receive directions (after slip buffer) E1/T1 Intact Mode (slip buffering of an unframed E1/T1) Framed slips (time slots 0 through 31/ DS0 channels) or block slips capability E1/T1 freeze option through write option to individual time slots/ds0s For E1 framer, time slot 0 Freeze option with microprocessor rewrite capability Maintenance Functions: Loopbacks: - Local with AIS to transmit line option - Line remote (all time slots/ds0s) - 11 of MB, Ed. 3

12 Proprietary TranSwitch Corporation Information for use Solely by its Customers - Payload remote loopback - Time slot/ds0 remote loopbacks - Transmission/detection of SF loop codes (loop-up and loop-down) Pattern generation/detection per E1/T1 - PRBS/Code word Generator/Analyzer to share with different channels: , , , QRSS(2 20-1) pseudorandom patterns or 32 bit code word - Monitoring point options: At decoder output; at transmit slip buffer output - All 1's option only in the information bits - Transmit AIS/AIS-CI - Transmit RAI/RAI-CI Pattern generation/detection per time slot/ds0 - A-Law or Mu-law digital milliwatt from a common generator in place of data for any time slot/ds0 - Programmable idle code insertion in place of data for any time slot/ds0 via slip buffer access - Force/detect programmable codes via write/read of the slip buffer RAM - Time slot loopback activate/ de-activate generation/detection covering ANSI T PRBS Generator/Analyzer (2 7-1, inverted) pseudorandom patterns - Any group of time slots/ds0 - PRBS/Code word Generator/Analyzer with any group of time slots/ds0s: , , , QRSS(2 20-1) pseudorandom patterns or 32 bit code word Error and alarm insertion capability - BPV - CRC-4/6 - FAS/nFAS/F bit - LOS. (all 0 s) - AIS (all 1 s) - AUXP for E1 lines Per-national-bit byte code read and write synchronized to a multiframe (E1 lines) Alarm Indications and Monitoring: Full ETSI compliant automatic alarm generation (E1 only) Programmable alarm generation and consequent actions LOS, Loss of Signal with programmable detect and recovery periods (G.775 and ETSI ) for E1 lines and covering ANSI T1.231 for T1 lines OOF, Out of Frame (G.704/G.706/ANSI T1.403) RAI (yellow), Remote Frame Alarm Line AIS (blue), all 1's Received selectable thresholds to meet G.775 or I.431/ETSI TS16 AIS Detection (E1 only) Signal Multiframe Error (E1 only) Slip alarm for transmit or receive slip event Line Code Violation counter with excessive zeros count option Sa6 code 0000 detection (E1 only) (future firmware + API release) Sa6 code detectors for ISDN (E1 only) (future firmware + API release) -MB, Ed of 104 -

13 Proprietary TranSwitch Corporation Information for use Solely by its Customers Sa7 code detection (E1 only) (future firmware + API release) Auxiliary pattern detector for ISDN (E1 only) (future firmware + API release) Detect, count and force CRC-6 (ESF only) (DS1 only) RAI-CI and AIS-CI support (DS1 only) (future firmware + API release) Detect and force frame slips LOS, Line AIS, TS16 AIS, OOF, AUXP, TX Slip, RX Slip, Signaling Change, and RAI are latched and shadowed (TS16 alarms optionally included with TS0 alarms) Performance Monitoring: Far End Block Error (E bit) counter Far End Block Error for ISDN TE (Sa6 code 0010) counter (future firmware + API release) Far End Block Error for ISDN T interface (Sa6 code 0001) counter (future firmware + API release) Frame Alignment Error counter CRC-4 Multiframe Error counter Facility Data Link (FDL) HDLC controller Automatic generation and reception of PRM (for DS1 only) Maintenance of performance MIB objects per RFC 2495 The following features are selectable for the M13 mux: DS3 Framing Functions: Framing on 4 F-bits in M Subframe Framing on 3 M-bits in M Frame Far end SEF/AIS indication in M13 mode Monitor RAI condition for both M13 and C-bit parity modes P-bit parity generation, monitoring, and counting (16-bit) C-bit parity or M13 mode selection C-bit parity unchannelized mode ( Mbit/s clear channel) FEAC channel (C3): read access of FEAC word, write access to set loopbacks; FEAC word detection of codes; loopbacks and alarms RAI indication (DS3 and DS1 alarms) C-bit access: - C1 identification - C-bit parity (C7-9) generation, checking, and counting - C-bit Path Maintenance Data Link (PMDL) HDLC controller (C13-15) - FEBE generation (on M, F or C parity error), detection, and counting - 13 of MB, Ed. 3

14 Proprietary TranSwitch Corporation Information for use Solely by its Customers Multiplexing/Demultiplexing Functions: 4 DS1s into a DS2 using stuff bit control (DS2 C-bits) 7 DS2s into a DS3 using stuff bit control (DS3 C-bits) or C-bit parity mode DS3 into 7 DS2s using stuff bit control (majority vote DS3 C-bits) or C-bit parity mode DS2 into 4 DS1s using stuff bit control (majority vote DS2 C-bits) G.747 Demultiplexer Features: G.747 OOF status bits for each G.747 framed channel. (OOF declared per G.747) Synchronization and de-stuffing to G.747 Rx Remote Alarm bits for each G.747 channel When G.747 OOF is detected Rx E1 AIS is automatically inserted into the corresponding E1 channels Incoming payload loopback request on G.747/E1s detected by monitoring stuff control bits (T1 only), or FEAC codes (for E1 and T1) Alarms and Fault monitoring: Detect and force: DS3 AIS (optional unframed 1010 or 11110), DS3 IDLE (framed 1100), DS3 FEAC alarms (all codes in C-bit parity mode), DS3 RAI, P-bit parity errors, C-bit parity errors, FEBE, and DS2 RAI Detect: DS3 Out of Frame, Loss of Signal, and Severely Errored Frame Performance Monitoring: Path Maintenance Data Link (PMDL) HDLC controller Maintenance of performance MIB objects per RFC MB, Ed of 104 -

15 Proprietary TranSwitch Corporation Information for use Solely by its Customers MULTI-CHANNEL HDLC - DS1 data structure: FDL channel via M bits: 4 kbit/s rate Bit-oriented code messages. SLC-96: C-/M-/A-/S-bits data link - E1 Data Structure: HDLC link 4/8/12/16/20 kbit/s in Time slot 0 - Additional DS0 HDLC Channels (future firmware + API release): One DS0 HDLC channel per T1/E1 line: any time slot of the T1/E1 can be mapped into an HDLC channel DS0 HDLC channels can be used for raw HDLC, ISDN, or SS7 applications (future firmware + API release). MICROPROCESSOR INTERFACE 8-bit Motorola or Intel Address/Data buses access mode 16-bit Multiplexed Address/Data bus access mode When the A/D mode is selected, the interface can be configured to support little endian (LE) or big endian (BE) operation Operates in slave mode (with internal mail box) or master mode (with external mail box) Mode operations selected during the initial device configuration via EEPROM OTHER Two DS1/E1 monitor ports Ability to tristate all outputs for in-circuit testing IEEE boundary scan - 15 of MB, Ed. 3

16 Proprietary TranSwitch Corporation Information for use Solely by its Customers LEAD DIAGRAM 26 V SS V SS V DD-IO V DD-INT V DD-INT V DD-IO V SS V SS V DD-INT V DD-INT V DD-IO V DD-INT V DD-INT V DD-IO V DD-INT V DD-INT V SS V SS V DD-IO V DD-INT V DD-INT V DD-IO AV SS AV SS AV SS V DD-INT V DD-IO V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V DD-INT V DD-INT V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V DD-IO V SS V SS V SS V SS V SS V SS V DD-INT V DD-INT V DD-IO AV DD AV SS AV SS AV SS AV DD AV DD 5 4 V DD-IO V DD-INT V DD-INT V DD-IO V SS V SS V DD-INT V DD-INT V DD-IO V DD-INT V SS V SS A B C D E F G H J K L M N P R T U V W Y AA AC AB Note:This is the top view. The leads are solder balls. See Figure 43 for package information. This view is rotated relative to the bottom view in Figure 43. AD AE AF Figure lead Plastic Ball Grid Array Package Lead Diagram -MB, Ed of 104 -

17 Proprietary TranSwitch Corporation Information for use Solely by its Customers LEAD DESCRIPTIONS POWER SUPPLY AND GROUND ( LEADS) Symbol Lead No. /P* Type Name/Function V DD-INT E7, E11, E12, E16, E19, G22, H5, L5, L22, M22, R5, T5, T22, W22, Y5, AB8, AB11, AB15, AB16, AB20 V DD-IO E8, E15, E20, G5, H22, M5, R22, W5, Y22, AB7, AB12, AB19 V SS A1, A26, E13, E14, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, N5, N11, N12, N13, N14, N15, N16, N22, P5, P11, P12, P13, P14, P15, P16, P22, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, AB13, AB14, AF1, AF26 P P P Digital VDD, Internal: +1.8 volt power supply, ±5% Digital VDD, Input/Output: +3.3 volt power supply, ±5% Digital Ground VSS: 0 volt reference AV DD AE23, AF23, AF24 P Analog VDD: +1.8 volt power supply, ±5% AV SS AB21, AC21, AC22, AD21, P Analog Ground AVSS: 0 volt reference AD22, AE22 * Note: I=Input; O=Output; P=Power, T=Tristate LINE SIDE SIGNAL, INDICATION AND CONTROL (145 LEADS) Note: Leads shown with dual symbols are used for either DS1 or DS3 signals, depending on the application. Symbol Lead No. /P Type Name/Function RE3G L1 I TTL3V d Test Lead: Should be tied low (100 ohm pull down to digital ground recommended). TE3G M4 I TTL3V d Test Lead: Should be tied low (100 ohm pull down to digital ground recommended). TDS3D M3 O CMOS3V 8 ma TDS3C M2 O CMOS3V 8 ma Transmit DS3 Line Data Output: Transmit C-bit parity or M13 formatted DS3 data is clocked out of the on rising edges of the transmit clock (TDS3C). Transmit DS3 Line Clock Output (TDS3C): A MHz clock output which is derived from the external transmit clock input signal (XCK), or from RDS3C when loop timing is selected. When XCK fails, the automatically switches to the RDS3C clock input instead of MB, Ed. 3

18 Proprietary TranSwitch Corporation Information for use Solely by its Customers Symbol Lead No. /P Type Name/Function RDS1D1/ RE1D1/ RDS3D RDS1D2/ RE1D2/LCV RDS1D3/ RE1D3/EXZ RDS1D4/ RE1D4/ DLOS RDS1D5/ RE1D5/ ALOS M1 I TTL3V Receive DS1 Line Data Input 1 (RDS1D1): This lead carries the receive NRZ data input signal for DS1 line 1. Receive E1 Line Data Input 1 (RE1D1): This lead carries the receive NRZ data input signal for E1 line 1. Receive DS3 Line Data Input (RDS3D): This lead carries the DS3 receive NRZ data input signal. Receive Mbit/s data is clocked into the on rising edges of the receive clock (RDS3C). N2 I TTL3V Receive DS1 Line Data Input 2 (RDS1D2): This lead carries the receive NRZ data input signal for DS1 line 2. Receive E1 Line Data Input 2 (RE1D2): This lead carries the receive NRZ data input signal for E1 line 2. DS3 Line Coding Violation Input (LCV): This lead is high when the providing DS3 LIU device (i.e., DART) detects that incoming data violated B3ZS coding for bipolar violations or when three or more consecutive zeros occur in the input data stream. P2 I TTL3V Receive DS1 Line Data Input 3 (RDS1D3): This lead carries the receive NRZ data input signal for DS1 line 3. Receive E1 Line Data Input 3 (RE1D3): This lead carries the receive NRZ data input signal for E1 line 3. DS3 Line Excessive Zeros Input (EXZ): This lead is low when the providing DS3 LIU device (i.e., DART) detects that three or more consecutive zeros occur in the input data stream for B3ZS coding. R1 I TTL3V Receive DS1 Line Data Input 4 (RDS1D4): This lead carries the receive NRZ data input signal for DS1 line 4. Receive E1 Line Data Input 4 (RE1D4): This lead carries the receive NRZ data input signal for E1 line 4. DS3 Line Digital LOS Input (DLOS): This lead is low when the providing DS3 LIU device (i.e., DART) detects digital LOS. R4 I TTL3V Receive DS1 Line Data Input 5 (RDS1D5): This lead carries the receive NRZ data input signal for DS1 line 5. Receive E1 Line Data Input 5 (RE1D5): This lead carries the receive NRZ data input signal for E1 line 5. DS3 Line Analog LOS Input (ALOS): This lead is low when the providing DS3 LIU device (i.e., DART) detects analog LOS. -MB, Ed of 104 -

19 Proprietary TranSwitch Corporation Information for use Solely by its Customers Symbol Lead No. /P Type Name/Function RDS1D6/ RE1D6/ DS3BIST RDS1D7/ RE1D7/ CDT RDS1D8- RDS1D21/ RE1D8- RE1D21 RDS1D22- RDS1D28 RDS1C1/ RE1C1/ RDS3C T3 I TTL3V Receive DS1 Line Data Input 6 (RDS1D6): This lead carries the receive NRZ data input signal for DS1 line 6. Receive E1 Line Data Input 6 (RE1D6): This lead carries the receive NRZ data input signal for E1 line 6. DS3 LIU Built-In Self Test Input (DS3BIST): An active low pulse to indicate an invalid PRBS pattern. This lead is high when a valid unframed PRBS pattern is detected by the providing DS3 LIU device (i.e., DART). U2 I TTL3V Receive DS1 Line Data Input 7 (RDS1D7): This lead carries the receive NRZ data input signal for DS1 line 7. Receive E1 Line Data Input 7 (RE1D7): This lead carries the receive NRZ data input signal for E1 line 7. Transmit C-Bit Data (CDT): The transmit gapped clock (CCKT) is provided for clocking in the following C-bits from this lead: C2, C4, C5, C6, C16, C17, C18, C19, C20, and C21. This lead must be set to high when it is not used for C-bit input. U4, V3, W2, V5, AA1, AB1, AB2, AB3, AA5, AD2, AB5, AF2, AC5, AE4 AF4, AC7, AD7, AE7, AF7, AF8, AF9 I TTL3V Receive DS1 Line Data Inputs 8-21: These leads carry the receive NRZ data input signal for DS1 lines 8 to 21. These leads should be tied high or low when using DS3 line mode. Receive E1 Line Data Inputs 8-21: This lead carries the receive NRZ data input signal for E1 line 8 to 21. These leads should be tied high or low when using DS3 line mode. I TTL3V Receive DS1 Line Data Inputs (RDS1D22-28): These leads carry the receive NRZ data input signal for DS1 lines 22 to 28. These leads should be tied high or low when using DS3 line mode. N3 I TTL3V Receive DS1 Line Clock Input (RDS1C1): An input for the 1544 khz recovered clock from the external line interface transceiver for DS1 line 1. The API determines the clock edge on which the received line signals are to be clocked in. Receive E1 Line Clock Input (RE1C1): An input for the 2048 khz recovered clock from the external line interface transceiver for E1 line 1. The API determines the clock edge on which the received line signals are to be clocked in. Receive DS3 Line Clock Input (RDS3C): An input for the MHz recovered clock from the DS3 external line interface. This clock is used as the time base for demultiplexing the DS3 data. When the loop timing feature is active (via LPTIME), or when the DS3 external transmit clock (XCK) fails, this clock becomes the transmit clock of MB, Ed. 3

20 Proprietary TranSwitch Corporation Information for use Solely by its Customers Symbol Lead No. /P Type Name/Function RDS1C2- RDS1C21/ RE1C2- RE1C21 RDS1C22- RDS1C28 RBPVn LOSn (n=1-28) TDS1D1/ TE1D1/ RAIS TDS1D2/ TE1D2/ RXDIS P1, P4, R3, T2, U1, V1, V2, V4, W3, W4, AA2, AA3, AA4, AD1, AC3, AD3, AE2, AD4, AF3, AC6 AD6, AE6, AC8, AD8, AC9, AE9, AB10 N4, N1, P3, R2, T1, T4, U3, U5, W1, Y1, Y2, Y3, Y4, AC1, AC2, AB4, AE1, AC4, AE3, AB6, AD5, AE5, AF5, AF6, AB9, AE8, AD9, AC10 I TTL3V Receive DS1 Line Clock Inputs 2-21: Input for the 1544 khz recovered clock from the external line interface transceiver for DS1 lines These leads should be tied high or low when using DS3 line mode. Receive E1 Line Clock Input s 2-21: Input for the 2048 khz recovered clock from the external line interface transceiver for E1 lines These leads should be tied high or low when using DS3 line mode. I TTL3V Receive DS1 Line Clock Inputs 2-28 (RDS1C22-28): Input for the 1544 khz recovered clock from the external line interface transceiver for DS1 lines These leads should be tied high or low when using DS3 line mode. I TTL3V Receive Bipolar Violation Indication Input for DS1/E1 line n: The RBPVn lead provides an input for indications of external bipolar violations detected in the external line interface transceiver. A high indicates a bipolar violation, and increments the internal 16-bit coding violation counter. A bipolar violation is clocked in on rising edges of the receive line clock RDS1Cn/RE1Cn. These leads should be tied low if not used. The LOSn lead is shared with BPVn allowing LOS to be detected from an external LIU input. C7 O CMOS3V 2 ma B6 O CMOS3V 2 ma Transmit DS1 Line Data Output 1 (TDS1D1): This lead carries the transmit NRZ data output signal for DS1 line 1. Transmit E1 Line Data Output 1 (TE1D1): This lead carries the transmit NRZ data output signal for E1 line 1. DS3 LIU Receive AIS Enable Output (RAIS): When RAIS is low, it enables generation of framed DS3 AIS on the receiver outputs of the connected DS3 LIU (i.e., DART). Transmit DS1 Line Data Output 2 (TDS1D2): This lead carries the transmit NRZ data output signal for DS1 line 2. Transmit E1 Line Data Output 2 (TE1D2): This lead carries the transmit NRZ data output signal for E1 line 2. DS3 LIU Receive Output Disable Output (RXDIS): When RXDIS is low, it forces the receiver RP/RD and RN outputs of the connected DS3 LIU (i.e., DART) to a low state. -MB, Ed of 104 -

21 Proprietary TranSwitch Corporation Information for use Solely by its Customers Symbol Lead No. /P Type Name/Function TDS1D3/ TE1D3/ TRLBK TDS1D4/ TE1D4/ LNLBK TDS1D5/ TE1D5/ ZERO TDS1D6/ TE1D6/ DSXDIS TDS1D7/ TE1D7/ TEST0 TDS1D8/ TE1D8/ TEST1 D7 O CMOS3V 2 ma B5 O CMOS3V 2 ma D6 O CMOS3V 2 ma C4 O CMOS3V 2 ma B4 O CMOS3V 2 ma B3 O CMOS3V 2 ma Transmit DS1 Line Data Output 3 (TDS1D3): This lead carries the transmit NRZ data output signal for DS1 line 3. Transmit E1 Line Data Output 3 (TE1D3): This lead carries the transmit NRZ data output signal for E1 line 3. DS3 LIU Terminal Loopback Enable Output (TRLBK): When TRLBK is low, it enables a digital loopback from the transmitter inputs to the receiver terminal side in the connected DS3 LIU (i.e., DART). Transmit DS1 Line Data Output 4 (TDS1D4): This lead carries the transmit NRZ data output signal for DS1 line 4. Transmit E1 Line Data Output 4 (TE1D4): This lead carries the transmit NRZ data output signal for E1 line 4. DS3 LIU Line Loopback Enable Output (LNLBK): When LNLBK is low, it enables an internal line loopback from the inputs DI1/DI2 to the DOUT or DO1/DO2 outputs in the connected DS3 LIU (i.e., DART). Transmit DS1 Line Data Output 5 (TDS1D5): This lead carries the transmit NRZ data output signal for DS1 line 5. Transmit E1 Line Data Output 5 (TE1D5): This lead carries the transmit NRZ data output signal for E1 line 5. DS3 LIU Transmit Zero cable Enable Output (ZERO): When ZERO is low, it improves the DOUT output mask for short cable length in the connected DS3 LIU (i.e., DART). Transmit DS1 Line Data Output 6 (TDS1D6): This lead carries the transmit NRZ data output signal for DS1 line 6. Transmit E1 Line Data Output 6 (TE1D6): This lead carries the transmit NRZ data output signal for E1 line 6. DS3 LIU Transmit DSX Output Disable (DSXDIS): When DSXDIS is low, it disables the DOUT output and enables the DO1/DO2 outputs in the connected DS3 LIU (i.e., DART). Transmit DS1 Line Data Output 7 (TDS1D7): This lead carries the transmit NRZ data output signal for DS1 line 7. Transmit E1 Line Data Output 7 (TE1D7): This lead carries the transmit NRZ data output signal for E1 line 7. DS3 LIU Test-in 0 Output (TEST0): Use TDS1D7 When TEST0 is low, it enables an internal PRBS generator in the connected DS3 LIU (i.e., DART). Transmit DS1 Line Data Output 8 (TDS1D8): This lead carries the transmit NRZ data output signal for DS1 line 8. Transmit E1 Line Data Output 8 (TE1D8): This lead carries the transmit NRZ data output signal for E1 line 8. DS3 LIU Test-in 1 Output (TEST1): When TEST1 is low, it enables an internal analog terminal side loopback from the TP/TD and TN signals to the receiver outputs in the connected DS3 LIU (i.e., DART) of MB, Ed. 3

22 Proprietary TranSwitch Corporation Information for use Solely by its Customers Symbol Lead No. /P Type Name/Function TDS1D9/ TE1D9/ PAT23 TDS1D10/ TE1D10/ DJSEL0 TDS1D11/ TE1D11/ DJSEL1 B2 O CMOS3V 2 ma D4 O CMOS3V 2 ma C2 O CMOS3V 2 ma Transmit DS1 Line Data Output 9 (TDS1D9): This lead carries the transmit NRZ data output signal for DS1 line 9. Transmit E1 Line Data Output 9 (TE1D9): This lead carries the transmit NRZ data output signal for E1 line 9. DS3 LIU PRBS 2 23 Select Output (PAT23): When PAT23 is low, it selects a pattern for the PRBS analyzer and generator for the connected DS3 LIU (i.e., DART). When this lead is high, it selects a pattern. Transmit DS1 Line Data Output 10 (TDS1D10): This lead carries the transmit NRZ data output signal for DS1 line 10. Transmit E1 Line Data Output 10 (TE1D10): This lead carries the transmit NRZ data output signal for E1 line 10. Dejitter Block Control 0 Output (DJSEL0): One of two DJSEL control leads that control the dejitter buffer/dejitter PLL modes of the connected DS3 LIU (i.e., DART). Transmit DS1 Line Data Output 11 (TDS1D11): This lead carries the transmit NRZ data output signal for DS1 line 11. Transmit E1 Line Data Output 11 (TE1D11): This lead carries the transmit NRZ data output signal for E1 line 11. Dejitter Block Control 1 Output (DJSEL1): One of two DJSEL control leads that control the dejitter buffer/dejitter PLL modes of the connected DS3 LIU (i.e., DART). TDS1D12/ TE1D12/ DIVSEL B1 O CMOS3V 2 ma Transmit DS1 Line Data Output 12 (TDS1D12): This lead carries the transmit NRZ data output signal for DS1 line 12. Transmit E1 Line Data Output 12 (TE1D12): This lead carries the transmit NRZ data output signal for E1 line 12. Divide Select Output (DIVSEL): This lead selects the divisor in the divide-by block in the dejitter PLL of the connected DS3 LIU (i.e., DART). TDS1D13/ TE1D13/ CCKT C1 O CMOS3V 2 ma Transmit DS1 Line Data Output 13 (TDS1D13): This lead carries the transmit NRZ data output signal for DS1 line 13. Transmit E1 Line Data Output 13 (TE1D13): This lead carries the transmit NRZ data output signal for E1 line 13. Transmit C-Bit Clock (CCKT): A gapped clock signal that is provided for clocking in selected transmit C-bit data (CDT). Data is clocked in on positive transitions of this clock. TDS1D14/ TE1D14/ CFMT D2 O CMOS3V 2 ma Transmit DS1 Line Data Output 14 (TDS1D14): This lead carries the transmit NRZ data output signal for DS1 line 14. Transmit E1 Line Data Output 14 (TE1D14): This lead carries the transmit NRZ data output signal for E1 line 14. Transmit C-Bit Framing Pulse (CFMT): This positive framing pulse occurs prior to the C2 bit. -MB, Ed of 104 -